net/hns3: support flow control
This patch adds support for MAC PAUSE flow control and priority flow control(PFC). MAC PAUSE flow control features: All user priorities(up) are mapped to tc0. It supports settings of flow mode and pause time. DCB features: Up can be mapped to other tc driver permits according to business requirement. We can config DCB information and enable PFC by rte_eth_dev_configure interface. Besides, enabling flow control of a priority is supported by rte_eth_dev_priority_flow_ctrl_set interface. we can also set flow mode and pause time by rte_eth_dev_priority_flow_ctrl_set. we do not support manual setting of ETS, but driver equally distributes bandwidth for each tc according to number of used tc. In addition, flow control function by default is turned off to ensure that app startup state is the same each time. Signed-off-by: Huisong Li <lihuisong@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Chunsong Feng <fengchunsong@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Signed-off-by: Hao Chen <chenhao164@huawei.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Wei Hu (Xavier)
Ferruh Yigit
parent
c37ca66f2b
commit
62e3ccc2b9
@ -11,7 +11,9 @@ Multicast MAC filter = Y
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RSS hash = Y
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RSS key update = Y
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RSS reta update = Y
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DCB = Y
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Flow director = Y
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Flow control = Y
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Flow API = Y
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FW version = Y
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Linux UIO = Y
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@ -27,5 +27,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_cmd.c
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SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_rss.c
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SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_flow.c
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SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_fdir.c
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SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_dcb.c
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include $(RTE_SDK)/mk/rte.lib.mk
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1642
drivers/net/hns3/hns3_dcb.c
Normal file
1642
drivers/net/hns3/hns3_dcb.c
Normal file
File diff suppressed because it is too large
Load Diff
166
drivers/net/hns3/hns3_dcb.h
Normal file
166
drivers/net/hns3/hns3_dcb.h
Normal file
@ -0,0 +1,166 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_DCB_H_
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#define _HNS3_DCB_H_
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/* MAC Pause */
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#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
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#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
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#define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
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#define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
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/* SP or DWRR */
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#define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
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#define HNS3_DCB_TX_SCHD_SP_MSK (0xFE)
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enum hns3_shap_bucket {
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HNS3_DCB_SHAP_C_BUCKET = 0,
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HNS3_DCB_SHAP_P_BUCKET,
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};
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struct hns3_priority_weight_cmd {
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uint8_t pri_id;
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uint8_t dwrr;
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};
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struct hns3_qs_weight_cmd {
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uint16_t qs_id;
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uint8_t dwrr;
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};
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struct hns3_pg_weight_cmd {
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uint8_t pg_id;
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uint8_t dwrr;
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};
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struct hns3_ets_tc_weight_cmd {
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uint8_t tc_weight[HNS3_MAX_TC_NUM];
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uint8_t weight_offset;
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uint8_t rsvd[15];
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};
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struct hns3_qs_to_pri_link_cmd {
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uint16_t qs_id;
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uint16_t rsvd;
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uint8_t priority;
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#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
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uint8_t link_vld;
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};
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struct hns3_nq_to_qs_link_cmd {
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uint16_t nq_id;
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uint16_t rsvd;
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#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
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uint16_t qset_id;
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};
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#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
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#define HNS3_DCB_SHAP_IR_B_LSH 0
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#define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
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#define HNS3_DCB_SHAP_IR_U_LSH 8
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#define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
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#define HNS3_DCB_SHAP_IR_S_LSH 12
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#define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
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#define HNS3_DCB_SHAP_BS_B_LSH 16
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#define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
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#define HNS3_DCB_SHAP_BS_S_LSH 21
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struct hns3_pri_shapping_cmd {
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uint8_t pri_id;
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uint8_t rsvd[3];
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uint32_t pri_shapping_para;
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};
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struct hns3_pg_shapping_cmd {
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uint8_t pg_id;
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uint8_t rsvd[3];
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uint32_t pg_shapping_para;
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};
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#define HNS3_BP_GRP_NUM 32
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#define HNS3_BP_SUB_GRP_ID_S 0
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#define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
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#define HNS3_BP_GRP_ID_S 5
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#define HNS3_BP_GRP_ID_M GENMASK(9, 5)
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struct hns3_bp_to_qs_map_cmd {
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uint8_t tc_id;
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uint8_t rsvd[2];
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uint8_t qs_group_id;
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uint32_t qs_bit_map;
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uint32_t rsvd1;
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};
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struct hns3_pfc_en_cmd {
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uint8_t tx_rx_en_bitmap;
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uint8_t pri_en_bitmap;
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};
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struct hns3_port_shapping_cmd {
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uint32_t port_shapping_para;
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};
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struct hns3_cfg_pause_param_cmd {
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t pause_trans_gap;
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uint8_t rsvd;
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uint16_t pause_trans_time;
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uint8_t rsvd1[6];
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/* extra mac address to do double check for pause frame */
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uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
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uint16_t rsvd2;
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};
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struct hns3_pg_to_pri_link_cmd {
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uint8_t pg_id;
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uint8_t rsvd1[3];
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uint8_t pri_bit_map;
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};
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enum hns3_shaper_level {
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HNS3_SHAPER_LVL_PRI = 0,
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HNS3_SHAPER_LVL_PG = 1,
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HNS3_SHAPER_LVL_PORT = 2,
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HNS3_SHAPER_LVL_QSET = 3,
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HNS3_SHAPER_LVL_CNT = 4,
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HNS3_SHAPER_LVL_VF = 0,
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HNS3_SHAPER_LVL_PF = 1,
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};
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struct hns3_shaper_parameter {
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uint32_t ir_b; /* IR_B parameter of IR shaper */
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uint32_t ir_u; /* IR_U parameter of IR shaper */
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uint32_t ir_s; /* IR_S parameter of IR shaper */
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};
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#define hns3_dcb_set_field(dest, string, val) \
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hns3_set_field((dest), \
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(HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH), val)
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#define hns3_dcb_get_field(src, string) \
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hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
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(HNS3_DCB_SHAP_##string##_LSH))
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int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
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int hns3_dcb_configure(struct hns3_adapter *hns);
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int hns3_dcb_init(struct hns3_hw *hw);
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int hns3_dcb_init_hw(struct hns3_hw *hw);
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int hns3_dcb_info_init(struct hns3_hw *hw);
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int
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hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
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int
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hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
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void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw);
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int hns3_dcb_cfg_update(struct hns3_adapter *hns);
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#endif /* _HNS3_DCB_H_ */
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@ -24,6 +24,7 @@
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#include "hns3_ethdev.h"
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#include "hns3_logs.h"
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#include "hns3_regs.h"
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#include "hns3_dcb.h"
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#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
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#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
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@ -2504,6 +2505,12 @@ hns3_init_hardware(struct hns3_adapter *hns)
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goto err_mac_init;
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}
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ret = hns3_dcb_init(hw);
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if (ret) {
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PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
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goto err_mac_init;
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}
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ret = hns3_init_fd_config(hns);
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if (ret) {
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PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
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@ -2627,11 +2634,200 @@ hns3_dev_close(struct rte_eth_dev *eth_dev)
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hw->adapter_state = HNS3_NIC_CLOSED;
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}
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static int
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hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
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fc_conf->pause_time = pf->pause_time;
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/* return fc current mode */
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switch (hw->current_mode) {
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case HNS3_FC_FULL:
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fc_conf->mode = RTE_FC_FULL;
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break;
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case HNS3_FC_TX_PAUSE:
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fc_conf->mode = RTE_FC_TX_PAUSE;
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break;
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case HNS3_FC_RX_PAUSE:
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fc_conf->mode = RTE_FC_RX_PAUSE;
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break;
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case HNS3_FC_NONE:
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default:
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fc_conf->mode = RTE_FC_NONE;
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break;
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}
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return 0;
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}
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static void
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hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
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{
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switch (mode) {
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case RTE_FC_NONE:
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hw->requested_mode = HNS3_FC_NONE;
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break;
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case RTE_FC_RX_PAUSE:
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hw->requested_mode = HNS3_FC_RX_PAUSE;
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break;
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case RTE_FC_TX_PAUSE:
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hw->requested_mode = HNS3_FC_TX_PAUSE;
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break;
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case RTE_FC_FULL:
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hw->requested_mode = HNS3_FC_FULL;
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break;
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default:
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hw->requested_mode = HNS3_FC_NONE;
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hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
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"configured to RTE_FC_NONE", mode);
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break;
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}
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}
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static int
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hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
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int ret;
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if (fc_conf->high_water || fc_conf->low_water ||
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fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
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hns3_err(hw, "Unsupported flow control settings specified, "
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"high_water(%u), low_water(%u), send_xon(%u) and "
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"mac_ctrl_frame_fwd(%u) must be set to '0'",
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fc_conf->high_water, fc_conf->low_water,
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fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
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return -EINVAL;
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}
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if (fc_conf->autoneg) {
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hns3_err(hw, "Unsupported fc auto-negotiation setting.");
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return -EINVAL;
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}
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if (!fc_conf->pause_time) {
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hns3_err(hw, "Invalid pause time %d setting.",
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fc_conf->pause_time);
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return -EINVAL;
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}
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if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
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hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
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hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
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"current_fc_status = %d", hw->current_fc_status);
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return -EOPNOTSUPP;
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}
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hns3_get_fc_mode(hw, fc_conf->mode);
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if (hw->requested_mode == hw->current_mode &&
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pf->pause_time == fc_conf->pause_time)
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return 0;
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rte_spinlock_lock(&hw->lock);
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ret = hns3_fc_enable(dev, fc_conf);
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rte_spinlock_unlock(&hw->lock);
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return ret;
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}
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static int
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hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_pfc_conf *pfc_conf)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
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uint8_t priority;
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int ret;
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if (!hns3_dev_dcb_supported(hw)) {
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hns3_err(hw, "This port does not support dcb configurations.");
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return -EOPNOTSUPP;
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}
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if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
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pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
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hns3_err(hw, "Unsupported flow control settings specified, "
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"high_water(%u), low_water(%u), send_xon(%u) and "
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"mac_ctrl_frame_fwd(%u) must be set to '0'",
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pfc_conf->fc.high_water, pfc_conf->fc.low_water,
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pfc_conf->fc.send_xon,
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pfc_conf->fc.mac_ctrl_frame_fwd);
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return -EINVAL;
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}
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if (pfc_conf->fc.autoneg) {
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hns3_err(hw, "Unsupported fc auto-negotiation setting.");
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return -EINVAL;
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}
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if (pfc_conf->fc.pause_time == 0) {
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hns3_err(hw, "Invalid pause time %d setting.",
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pfc_conf->fc.pause_time);
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return -EINVAL;
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}
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if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
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hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
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hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
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"current_fc_status = %d", hw->current_fc_status);
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return -EOPNOTSUPP;
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}
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priority = pfc_conf->priority;
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hns3_get_fc_mode(hw, pfc_conf->fc.mode);
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if (hw->dcb_info.pfc_en & BIT(priority) &&
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hw->requested_mode == hw->current_mode &&
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pfc_conf->fc.pause_time == pf->pause_time)
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return 0;
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rte_spinlock_lock(&hw->lock);
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ret = hns3_dcb_pfc_enable(dev, pfc_conf);
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rte_spinlock_unlock(&hw->lock);
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return ret;
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}
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static int
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hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
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enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
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int i;
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rte_spinlock_lock(&hw->lock);
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if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
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dcb_info->nb_tcs = pf->local_max_tc;
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else
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dcb_info->nb_tcs = 1;
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for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
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dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
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for (i = 0; i < dcb_info->nb_tcs; i++)
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dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
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for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
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dcb_info->tc_queue.tc_rxq[0][i].base =
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hw->tc_queue[i].tqp_offset;
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dcb_info->tc_queue.tc_txq[0][i].base =
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hw->tc_queue[i].tqp_offset;
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dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
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hw->tc_queue[i].tqp_count;
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dcb_info->tc_queue.tc_txq[0][i].nb_queue =
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hw->tc_queue[i].tqp_count;
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||||
}
|
||||
rte_spinlock_unlock(&hw->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct eth_dev_ops hns3_eth_dev_ops = {
|
||||
.dev_close = hns3_dev_close,
|
||||
.mtu_set = hns3_dev_mtu_set,
|
||||
.dev_infos_get = hns3_dev_infos_get,
|
||||
.fw_version_get = hns3_fw_version_get,
|
||||
.flow_ctrl_get = hns3_flow_ctrl_get,
|
||||
.flow_ctrl_set = hns3_flow_ctrl_set,
|
||||
.priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
|
||||
.mac_addr_add = hns3_add_mac_addr,
|
||||
.mac_addr_remove = hns3_remove_mac_addr,
|
||||
.mac_addr_set = hns3_set_default_mac_addr,
|
||||
@ -2642,13 +2838,17 @@ static const struct eth_dev_ops hns3_eth_dev_ops = {
|
||||
.reta_update = hns3_dev_rss_reta_update,
|
||||
.reta_query = hns3_dev_rss_reta_query,
|
||||
.filter_ctrl = hns3_dev_filter_ctrl,
|
||||
.get_dcb_info = hns3_get_dcb_info,
|
||||
};
|
||||
|
||||
static int
|
||||
hns3_dev_init(struct rte_eth_dev *eth_dev)
|
||||
{
|
||||
struct rte_device *dev = eth_dev->device;
|
||||
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
|
||||
struct hns3_adapter *hns = eth_dev->data->dev_private;
|
||||
struct hns3_hw *hw = &hns->hw;
|
||||
uint16_t device_id = pci_dev->id.device_id;
|
||||
int ret;
|
||||
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
@ -2668,6 +2868,12 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)
|
||||
return 0;
|
||||
|
||||
hw->adapter_state = HNS3_NIC_UNINITIALIZED;
|
||||
|
||||
if (device_id == HNS3_DEV_ID_25GE_RDMA ||
|
||||
device_id == HNS3_DEV_ID_50GE_RDMA ||
|
||||
device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
|
||||
hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
|
||||
|
||||
hns->is_vf = false;
|
||||
hw->data = eth_dev->data;
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@ if arch_subdir != 'x86' and arch_subdir != 'arm' or not dpdk_conf.get('RTE_ARCH_
|
||||
endif
|
||||
|
||||
sources = files('hns3_cmd.c',
|
||||
'hns3_dcb.c',
|
||||
'hns3_ethdev.c',
|
||||
'hns3_fdir.c',
|
||||
'hns3_flow.c',
|
||||
|
||||
Loading…
Reference in New Issue
Block a user