net/ngbe: support Rx queue start/stop
Initializes receive unit, support to start and stop receive unit for specified queues. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
This commit is contained in:
Jiawen Wu
Andrew Rybchenko
parent
001c782330
commit
62fc35e63d
@ -59,6 +59,18 @@ static inline s32 ngbe_mac_get_mac_addr_dummy(struct ngbe_hw *TUP0, u8 *TUP1)
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{
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return NGBE_ERR_OPS_DUMMY;
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}
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static inline s32 ngbe_mac_enable_rx_dma_dummy(struct ngbe_hw *TUP0, u32 TUP1)
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{
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return NGBE_ERR_OPS_DUMMY;
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}
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static inline s32 ngbe_mac_disable_sec_rx_path_dummy(struct ngbe_hw *TUP0)
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{
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return NGBE_ERR_OPS_DUMMY;
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}
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static inline s32 ngbe_mac_enable_sec_rx_path_dummy(struct ngbe_hw *TUP0)
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{
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return NGBE_ERR_OPS_DUMMY;
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}
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static inline s32 ngbe_mac_acquire_swfw_sync_dummy(struct ngbe_hw *TUP0,
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u32 TUP1)
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{
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@ -167,6 +179,9 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)
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hw->mac.start_hw = ngbe_mac_start_hw_dummy;
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hw->mac.stop_hw = ngbe_mac_stop_hw_dummy;
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hw->mac.get_mac_addr = ngbe_mac_get_mac_addr_dummy;
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hw->mac.enable_rx_dma = ngbe_mac_enable_rx_dma_dummy;
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hw->mac.disable_sec_rx_path = ngbe_mac_disable_sec_rx_path_dummy;
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hw->mac.enable_sec_rx_path = ngbe_mac_enable_sec_rx_path_dummy;
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hw->mac.acquire_swfw_sync = ngbe_mac_acquire_swfw_sync_dummy;
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hw->mac.release_swfw_sync = ngbe_mac_release_swfw_sync_dummy;
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hw->mac.setup_link = ngbe_mac_setup_link_dummy;
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@ -536,6 +536,63 @@ void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
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ngbe_release_eeprom_semaphore(hw);
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}
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/**
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* ngbe_disable_sec_rx_path - Stops the receive data path
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* @hw: pointer to hardware structure
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*
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* Stops the receive data path and waits for the HW to internally empty
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* the Rx security block
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**/
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s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
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{
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#define NGBE_MAX_SECRX_POLL 4000
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int i;
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u32 secrxreg;
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DEBUGFUNC("ngbe_disable_sec_rx_path");
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secrxreg = rd32(hw, NGBE_SECRXCTL);
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secrxreg |= NGBE_SECRXCTL_XDSA;
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wr32(hw, NGBE_SECRXCTL, secrxreg);
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for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
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secrxreg = rd32(hw, NGBE_SECRXSTAT);
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if (!(secrxreg & NGBE_SECRXSTAT_RDY))
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/* Use interrupt-safe sleep just in case */
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usec_delay(10);
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else
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break;
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}
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/* For informational purposes only */
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if (i >= NGBE_MAX_SECRX_POLL)
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DEBUGOUT("Rx unit being enabled before security "
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"path fully disabled. Continuing with init.\n");
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return 0;
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}
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/**
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* ngbe_enable_sec_rx_path - Enables the receive data path
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* @hw: pointer to hardware structure
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*
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* Enables the receive data path.
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**/
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s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
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{
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u32 secrxreg;
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DEBUGFUNC("ngbe_enable_sec_rx_path");
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secrxreg = rd32(hw, NGBE_SECRXCTL);
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secrxreg &= ~NGBE_SECRXCTL_XDSA;
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wr32(hw, NGBE_SECRXCTL, secrxreg);
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ngbe_flush(hw);
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return 0;
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}
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/**
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* ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
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* @hw: pointer to hardware struct
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@ -756,6 +813,21 @@ void ngbe_disable_rx(struct ngbe_hw *hw)
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wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
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}
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void ngbe_enable_rx(struct ngbe_hw *hw)
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{
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u32 pfdtxgswc;
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wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
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wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
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if (hw->mac.set_lben) {
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pfdtxgswc = rd32(hw, NGBE_PSRCTL);
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pfdtxgswc |= NGBE_PSRCTL_LBENA;
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wr32(hw, NGBE_PSRCTL, pfdtxgswc);
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hw->mac.set_lben = false;
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}
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}
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/**
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* ngbe_set_mac_type - Sets MAC type
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* @hw: pointer to the HW structure
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@ -802,6 +874,36 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw)
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return err;
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}
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/**
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* ngbe_enable_rx_dma - Enable the Rx DMA unit
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* @hw: pointer to hardware structure
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* @regval: register value to write to RXCTRL
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*
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* Enables the Rx DMA unit
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**/
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s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
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{
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DEBUGFUNC("ngbe_enable_rx_dma");
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/*
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* Workaround silicon errata when enabling the Rx datapath.
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* If traffic is incoming before we enable the Rx unit, it could hang
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* the Rx DMA unit. Therefore, make sure the security engine is
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* completely disabled prior to enabling the Rx unit.
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*/
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hw->mac.disable_sec_rx_path(hw);
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if (regval & NGBE_PBRXCTL_ENA)
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ngbe_enable_rx(hw);
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else
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ngbe_disable_rx(hw);
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hw->mac.enable_sec_rx_path(hw);
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return 0;
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}
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void ngbe_map_device_id(struct ngbe_hw *hw)
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{
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u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
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@ -886,11 +988,14 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
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mac->init_hw = ngbe_init_hw;
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mac->reset_hw = ngbe_reset_hw_em;
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mac->start_hw = ngbe_start_hw;
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mac->enable_rx_dma = ngbe_enable_rx_dma;
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mac->get_mac_addr = ngbe_get_mac_addr;
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mac->stop_hw = ngbe_stop_hw;
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mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
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mac->release_swfw_sync = ngbe_release_swfw_sync;
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mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
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mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
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/* RAR */
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mac->set_rar = ngbe_set_rar;
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mac->clear_rar = ngbe_clear_rar;
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@ -34,6 +34,8 @@ s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
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u32 enable_addr);
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s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index);
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s32 ngbe_init_rx_addrs(struct ngbe_hw *hw);
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s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw);
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s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw);
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s32 ngbe_validate_mac_addr(u8 *mac_addr);
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s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask);
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@ -46,10 +48,12 @@ s32 ngbe_init_uta_tables(struct ngbe_hw *hw);
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s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw);
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s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw);
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void ngbe_disable_rx(struct ngbe_hw *hw);
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void ngbe_enable_rx(struct ngbe_hw *hw);
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s32 ngbe_init_shared_code(struct ngbe_hw *hw);
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s32 ngbe_set_mac_type(struct ngbe_hw *hw);
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s32 ngbe_init_ops_pf(struct ngbe_hw *hw);
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s32 ngbe_init_phy(struct ngbe_hw *hw);
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s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval);
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void ngbe_map_device_id(struct ngbe_hw *hw);
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#endif /* _NGBE_HW_H_ */
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@ -97,6 +97,9 @@ struct ngbe_mac_info {
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s32 (*start_hw)(struct ngbe_hw *hw);
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s32 (*stop_hw)(struct ngbe_hw *hw);
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s32 (*get_mac_addr)(struct ngbe_hw *hw, u8 *mac_addr);
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s32 (*enable_rx_dma)(struct ngbe_hw *hw, u32 regval);
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s32 (*disable_sec_rx_path)(struct ngbe_hw *hw);
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s32 (*enable_sec_rx_path)(struct ngbe_hw *hw);
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s32 (*acquire_swfw_sync)(struct ngbe_hw *hw, u32 mask);
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void (*release_swfw_sync)(struct ngbe_hw *hw, u32 mask);
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@ -190,6 +193,7 @@ struct ngbe_hw {
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u16 nb_rx_queues;
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u16 nb_tx_queues;
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u32 q_rx_regs[8 * 4];
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u32 q_tx_regs[8 * 4];
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bool is_pf;
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};
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@ -569,6 +569,8 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
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dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
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dev_info->min_rx_bufsize = 1024;
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dev_info->max_rx_pktlen = 15872;
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dev_info->default_rxconf = (struct rte_eth_rxconf) {
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.rx_thresh = {
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@ -598,6 +600,7 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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ETH_LINK_SPEED_10M;
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/* Driver-preferred Rx/Tx parameters */
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dev_info->default_rxportconf.burst_size = 32;
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dev_info->default_txportconf.burst_size = 32;
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dev_info->default_rxportconf.nb_queues = 1;
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dev_info->default_txportconf.nb_queues = 1;
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@ -1086,6 +1089,8 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = {
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.dev_start = ngbe_dev_start,
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.dev_stop = ngbe_dev_stop,
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.link_update = ngbe_dev_link_update,
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.rx_queue_start = ngbe_dev_rx_queue_start,
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.rx_queue_stop = ngbe_dev_rx_queue_stop,
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.tx_queue_start = ngbe_dev_tx_queue_start,
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.tx_queue_stop = ngbe_dev_tx_queue_stop,
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.rx_queue_setup = ngbe_dev_rx_queue_setup,
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@ -86,9 +86,15 @@ void ngbe_dev_tx_init(struct rte_eth_dev *dev);
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int ngbe_dev_rxtx_start(struct rte_eth_dev *dev);
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void ngbe_dev_save_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id);
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void ngbe_dev_store_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id);
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void ngbe_dev_save_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id);
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void ngbe_dev_store_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id);
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int ngbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ngbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ngbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int ngbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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@ -511,15 +511,111 @@ ngbe_dev_clear_queues(struct rte_eth_dev *dev)
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}
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}
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static int
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ngbe_alloc_rx_queue_mbufs(struct ngbe_rx_queue *rxq)
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{
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struct ngbe_rx_entry *rxe = rxq->sw_ring;
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uint64_t dma_addr;
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unsigned int i;
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/* Initialize software ring entries */
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for (i = 0; i < rxq->nb_rx_desc; i++) {
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/* the ring can also be modified by hardware */
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volatile struct ngbe_rx_desc *rxd;
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struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
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if (mbuf == NULL) {
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PMD_INIT_LOG(ERR, "Rx mbuf alloc failed queue_id=%u port_id=%u",
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(unsigned int)rxq->queue_id,
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(unsigned int)rxq->port_id);
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return -ENOMEM;
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}
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mbuf->data_off = RTE_PKTMBUF_HEADROOM;
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mbuf->port = rxq->port_id;
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dma_addr =
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rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
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rxd = &rxq->rx_ring[i];
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NGBE_RXD_HDRADDR(rxd, 0);
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NGBE_RXD_PKTADDR(rxd, dma_addr);
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rxe[i].mbuf = mbuf;
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}
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return 0;
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}
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/*
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* Initializes Receive Unit.
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*/
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int
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ngbe_dev_rx_init(struct rte_eth_dev *dev)
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{
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RTE_SET_USED(dev);
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struct ngbe_hw *hw;
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struct ngbe_rx_queue *rxq;
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uint64_t bus_addr;
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uint32_t fctrl;
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uint32_t hlreg0;
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uint32_t srrctl;
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uint16_t buf_size;
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uint16_t i;
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return -EINVAL;
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PMD_INIT_FUNC_TRACE();
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hw = ngbe_dev_hw(dev);
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/*
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* Make sure receives are disabled while setting
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* up the Rx context (registers, descriptor rings, etc.).
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*/
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wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
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wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
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/* Enable receipt of broadcasted frames */
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fctrl = rd32(hw, NGBE_PSRCTL);
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fctrl |= NGBE_PSRCTL_BCA;
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wr32(hw, NGBE_PSRCTL, fctrl);
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hlreg0 = rd32(hw, NGBE_SECRXCTL);
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hlreg0 &= ~NGBE_SECRXCTL_XDSA;
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wr32(hw, NGBE_SECRXCTL, hlreg0);
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wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
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NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
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/* Setup Rx queues */
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for (i = 0; i < dev->data->nb_rx_queues; i++) {
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rxq = dev->data->rx_queues[i];
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/* Setup the Base and Length of the Rx Descriptor Rings */
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bus_addr = rxq->rx_ring_phys_addr;
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wr32(hw, NGBE_RXBAL(rxq->reg_idx),
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(uint32_t)(bus_addr & BIT_MASK32));
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wr32(hw, NGBE_RXBAH(rxq->reg_idx),
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(uint32_t)(bus_addr >> 32));
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wr32(hw, NGBE_RXRP(rxq->reg_idx), 0);
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wr32(hw, NGBE_RXWP(rxq->reg_idx), 0);
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srrctl = NGBE_RXCFG_RNGLEN(rxq->nb_rx_desc);
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/* Set if packets are dropped when no descriptors available */
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if (rxq->drop_en)
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srrctl |= NGBE_RXCFG_DROP;
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/*
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* Configure the Rx buffer size in the PKTLEN field of
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* the RXCFG register of the queue.
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* The value is in 1 KB resolution. Valid values can be from
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* 1 KB to 16 KB.
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*/
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buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
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RTE_PKTMBUF_HEADROOM);
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buf_size = ROUND_DOWN(buf_size, 0x1 << 10);
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srrctl |= NGBE_RXCFG_PKTLEN(buf_size);
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wr32(hw, NGBE_RXCFG(rxq->reg_idx), srrctl);
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}
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return 0;
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}
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/*
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@ -564,7 +660,9 @@ ngbe_dev_rxtx_start(struct rte_eth_dev *dev)
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{
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struct ngbe_hw *hw;
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struct ngbe_tx_queue *txq;
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struct ngbe_rx_queue *rxq;
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uint32_t dmatxctl;
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uint32_t rxctrl;
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uint16_t i;
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int ret = 0;
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@ -594,7 +692,39 @@ ngbe_dev_rxtx_start(struct rte_eth_dev *dev)
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}
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}
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return -EINVAL;
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for (i = 0; i < dev->data->nb_rx_queues; i++) {
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rxq = dev->data->rx_queues[i];
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if (rxq->rx_deferred_start == 0) {
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ret = ngbe_dev_rx_queue_start(dev, i);
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if (ret < 0)
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return ret;
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}
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}
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/* Enable Receive engine */
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rxctrl = rd32(hw, NGBE_PBRXCTL);
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rxctrl |= NGBE_PBRXCTL_ENA;
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hw->mac.enable_rx_dma(hw, rxctrl);
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return 0;
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}
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void
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ngbe_dev_save_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id)
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{
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u32 *reg = &hw->q_rx_regs[rx_queue_id * 8];
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*(reg++) = rd32(hw, NGBE_RXBAL(rx_queue_id));
|
||||
*(reg++) = rd32(hw, NGBE_RXBAH(rx_queue_id));
|
||||
*(reg++) = rd32(hw, NGBE_RXCFG(rx_queue_id));
|
||||
}
|
||||
|
||||
void
|
||||
ngbe_dev_store_rx_queue(struct ngbe_hw *hw, uint16_t rx_queue_id)
|
||||
{
|
||||
u32 *reg = &hw->q_rx_regs[rx_queue_id * 8];
|
||||
wr32(hw, NGBE_RXBAL(rx_queue_id), *(reg++));
|
||||
wr32(hw, NGBE_RXBAH(rx_queue_id), *(reg++));
|
||||
wr32(hw, NGBE_RXCFG(rx_queue_id), *(reg++) & ~NGBE_RXCFG_ENA);
|
||||
}
|
||||
|
||||
void
|
||||
@ -615,6 +745,85 @@ ngbe_dev_store_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id)
|
||||
wr32(hw, NGBE_TXCFG(tx_queue_id), *(reg++) & ~NGBE_TXCFG_ENA);
|
||||
}
|
||||
|
||||
/*
|
||||
* Start Receive Units for specified queue.
|
||||
*/
|
||||
int
|
||||
ngbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
|
||||
{
|
||||
struct ngbe_hw *hw = ngbe_dev_hw(dev);
|
||||
struct ngbe_rx_queue *rxq;
|
||||
uint32_t rxdctl;
|
||||
int poll_ms;
|
||||
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
|
||||
rxq = dev->data->rx_queues[rx_queue_id];
|
||||
|
||||
/* Allocate buffers for descriptor rings */
|
||||
if (ngbe_alloc_rx_queue_mbufs(rxq) != 0) {
|
||||
PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
|
||||
rx_queue_id);
|
||||
return -1;
|
||||
}
|
||||
rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
|
||||
rxdctl |= NGBE_RXCFG_ENA;
|
||||
wr32(hw, NGBE_RXCFG(rxq->reg_idx), rxdctl);
|
||||
|
||||
/* Wait until Rx Enable ready */
|
||||
poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
|
||||
do {
|
||||
rte_delay_ms(1);
|
||||
rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
|
||||
} while (--poll_ms && !(rxdctl & NGBE_RXCFG_ENA));
|
||||
if (poll_ms == 0)
|
||||
PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
|
||||
rte_wmb();
|
||||
wr32(hw, NGBE_RXRP(rxq->reg_idx), 0);
|
||||
wr32(hw, NGBE_RXWP(rxq->reg_idx), rxq->nb_rx_desc - 1);
|
||||
dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop Receive Units for specified queue.
|
||||
*/
|
||||
int
|
||||
ngbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
|
||||
{
|
||||
struct ngbe_hw *hw = ngbe_dev_hw(dev);
|
||||
struct ngbe_adapter *adapter = ngbe_dev_adapter(dev);
|
||||
struct ngbe_rx_queue *rxq;
|
||||
uint32_t rxdctl;
|
||||
int poll_ms;
|
||||
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
|
||||
rxq = dev->data->rx_queues[rx_queue_id];
|
||||
|
||||
ngbe_dev_save_rx_queue(hw, rxq->reg_idx);
|
||||
wr32m(hw, NGBE_RXCFG(rxq->reg_idx), NGBE_RXCFG_ENA, 0);
|
||||
|
||||
/* Wait until Rx Enable bit clear */
|
||||
poll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;
|
||||
do {
|
||||
rte_delay_ms(1);
|
||||
rxdctl = rd32(hw, NGBE_RXCFG(rxq->reg_idx));
|
||||
} while (--poll_ms && (rxdctl & NGBE_RXCFG_ENA));
|
||||
if (poll_ms == 0)
|
||||
PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
|
||||
|
||||
rte_delay_us(RTE_NGBE_WAIT_100_US);
|
||||
ngbe_dev_store_rx_queue(hw, rxq->reg_idx);
|
||||
|
||||
ngbe_rx_queue_release_mbufs(rxq);
|
||||
ngbe_reset_rx_queue(adapter, rxq);
|
||||
dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Start Transmit Units for specified queue.
|
||||
*/
|
||||
|
||||
@ -43,6 +43,14 @@ struct ngbe_rx_desc {
|
||||
} qw1; /* also as r.hdr_addr */
|
||||
};
|
||||
|
||||
/* @ngbe_rx_desc.qw0 */
|
||||
#define NGBE_RXD_PKTADDR(rxd, v) \
|
||||
(((volatile __le64 *)(rxd))[0] = cpu_to_le64(v))
|
||||
|
||||
/* @ngbe_rx_desc.qw1 */
|
||||
#define NGBE_RXD_HDRADDR(rxd, v) \
|
||||
(((volatile __le64 *)(rxd))[1] = cpu_to_le64(v))
|
||||
|
||||
/*****************************************************************************
|
||||
* Transmit Descriptor
|
||||
*****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user