common/cnxk: add CPT hardware definitions
Add CPT hardware definitions. CPT is the hardware block on cnxk family of processors, that can be used to offload cryptographic operations. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit is contained in:
Vidya Sagar Velumuri
Akhil Goyal
parent
71f8bd4e60
commit
64a73ebd87
291
drivers/common/cnxk/hw/cpt.h
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291
drivers/common/cnxk/hw/cpt.h
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@ -0,0 +1,291 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef __CPT_HW_H__
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#define __CPT_HW_H__
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/* Register offsets */
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#define CPT_COMP_NOT_DONE (0x0ull)
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#define CPT_COMP_GOOD (0x1ull)
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#define CPT_COMP_FAULT (0x2ull)
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#define CPT_COMP_SWERR (0x3ull)
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#define CPT_COMP_HWERR (0x4ull)
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#define CPT_COMP_INSTERR (0x5ull)
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#define CPT_COMP_WARN (0x6ull) /* [CN10K, .) */
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#define CPT_LF_INT_VEC_MISC (0x0ull)
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#define CPT_LF_INT_VEC_DONE (0x1ull)
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#define CPT_LF_CTL (0x10ull)
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#define CPT_LF_DONE_WAIT (0x30ull)
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#define CPT_LF_INPROG (0x40ull)
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#define CPT_LF_DONE (0x50ull)
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#define CPT_LF_DONE_ACK (0x60ull)
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#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)
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#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)
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#define CPT_LF_MISC_INT (0xb0ull)
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#define CPT_LF_MISC_INT_W1S (0xc0ull)
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#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)
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#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)
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#define CPT_LF_Q_BASE (0xf0ull)
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#define CPT_LF_Q_SIZE (0x100ull)
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#define CPT_LF_Q_INST_PTR (0x110ull)
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#define CPT_LF_Q_GRP_PTR (0x120ull)
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#define CPT_LF_NQX(a) (0x400ull | (uint64_t)(a) << 3)
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#define CPT_LF_CTX_CTL (0x500ull)
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#define CPT_LF_CTX_FLUSH (0x510ull)
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#define CPT_LF_CTX_ERR (0x520ull)
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#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)
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#define CPT_LF_CTX_ENC_PKT_CNT (0x540ull)
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#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
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#define CPT_LF_CTX_DEC_PKT_CNT (0x560ull)
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#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
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#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
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/* Structures definitions */
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union cpt_lf_ctl {
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uint64_t u;
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struct cpt_lf_ctl_s {
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uint64_t ena : 1;
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uint64_t fc_ena : 1;
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uint64_t fc_up_crossing : 1;
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uint64_t reserved_3_3 : 1;
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uint64_t fc_hyst_bits : 4;
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uint64_t reserved_8_63 : 56;
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} s;
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};
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union cpt_lf_ctx_flush {
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uint64_t u;
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struct {
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uint64_t cptr : 46;
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uint64_t inval : 1;
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uint64_t res : 1;
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uint64_t pf_func : 16;
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} s;
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};
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union cpt_lf_inprog {
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uint64_t u;
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struct cpt_lf_inprog_s {
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uint64_t inflight : 9;
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uint64_t reserved_9_15 : 7;
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uint64_t eena : 1;
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uint64_t grp_drp : 1;
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uint64_t reserved_18_30 : 13;
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uint64_t grb_partial : 1;
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uint64_t grb_cnt : 8;
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uint64_t gwb_cnt : 8;
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uint64_t reserved_48_63 : 16;
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} s;
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};
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union cpt_lf_q_base {
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uint64_t u;
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struct cpt_lf_q_base_s {
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uint64_t fault : 1;
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uint64_t stopped : 1;
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uint64_t reserved_2_6 : 5;
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uint64_t addr : 46;
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uint64_t reserved_53_63 : 11;
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} s;
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};
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union cpt_lf_q_size {
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uint64_t u;
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struct cpt_lf_q_size_s {
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uint64_t size_div40 : 15;
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uint64_t reserved_15_63 : 49;
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} s;
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};
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union cpt_lf_misc_int {
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uint64_t u;
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struct cpt_lf_misc_int_s {
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uint64_t reserved_0_0 : 1;
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uint64_t nqerr : 1;
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uint64_t irde : 1;
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uint64_t nwrp : 1;
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uint64_t reserved_4_4 : 1;
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uint64_t hwerr : 1;
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uint64_t fault : 1;
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uint64_t reserved_7_63 : 57;
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} s;
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};
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union cpt_inst_w4 {
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uint64_t u64;
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struct {
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uint64_t dlen : 16;
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uint64_t param2 : 16;
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uint64_t param1 : 16;
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uint64_t opcode_major : 8;
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uint64_t opcode_minor : 8;
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} s;
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};
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union cpt_inst_w7 {
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uint64_t u64;
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struct {
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uint64_t cptr : 60;
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uint64_t ctx_val : 1;
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uint64_t egrp : 3;
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} s;
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};
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struct cpt_inst_s {
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union cpt_inst_w0 {
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struct {
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uint64_t nixtxl : 3;
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uint64_t doneint : 1;
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uint64_t nixtx_addr : 60;
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} s;
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uint64_t u64;
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} w0;
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uint64_t res_addr;
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union cpt_inst_w2 {
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struct {
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uint64_t tag : 32;
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uint64_t tt : 2;
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uint64_t grp : 10;
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uint64_t reserved_172_175 : 4;
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uint64_t rvu_pf_func : 16;
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} s;
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uint64_t u64;
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} w2;
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union cpt_inst_w3 {
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struct {
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uint64_t qord : 1;
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uint64_t reserved_194_193 : 2;
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uint64_t wqe_ptr : 61;
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} s;
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uint64_t u64;
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} w3;
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union cpt_inst_w4 w4;
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uint64_t dptr;
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uint64_t rptr;
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union cpt_inst_w7 w7;
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};
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union cpt_res_s {
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struct cpt_cn10k_res_s {
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uint64_t compcode : 7;
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uint64_t doneint : 1;
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uint64_t uc_compcode : 8;
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uint64_t rlen : 16;
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uint64_t spi : 32;
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uint64_t esn;
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} cn10k;
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struct cpt_cn9k_res_s {
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uint64_t compcode : 8;
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uint64_t uc_compcode : 8;
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uint64_t doneint : 1;
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uint64_t reserved_17_63 : 47;
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uint64_t reserved_64_127;
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} cn9k;
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};
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/* [CN10K, .) */
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struct cpt_parse_hdr_s {
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/* WORD 0 */
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union {
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uint64_t u64;
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struct {
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uint8_t pad_len : 3;
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uint8_t num_frags : 3;
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uint8_t pkt_out : 2;
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uint8_t err_sum : 1;
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uint8_t reas_sts : 4;
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uint8_t reserved_53 : 1;
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uint8_t et_owr : 1;
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uint8_t pkt_fmt : 1;
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uint16_t match_id : 16;
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uint32_t cookie : 32;
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};
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} w0;
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/* WORD 1 */
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uint64_t wqe_ptr;
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/* WORD 2 */
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union {
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uint64_t u64;
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struct {
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uint8_t fi_pad : 3;
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uint8_t fi_offset : 5;
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uint8_t il3_off;
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uint16_t orig_pf_func;
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uint16_t reserved_145_160;
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uint16_t frag_age;
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};
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} w2;
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/* WORD 3 */
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union {
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uint64_t u64;
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struct {
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uint32_t spi;
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uint16_t reserved_209_224;
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uint8_t uc_ccode;
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uint8_t hw_ccode;
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};
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} w3;
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/* WORD 4 */
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union {
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uint64_t u64;
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uint64_t esn;
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uint64_t frag1_wqe_ptr;
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};
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};
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union cpt_frag_info {
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uint16_t info;
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struct {
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uint16_t f_off : 13;
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uint16_t f_mf : 1;
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uint16_t f_rsv : 2;
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};
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};
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struct cpt_frag_info_s {
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/* WORD 0 */
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union {
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uint64_t u64;
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struct {
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union cpt_frag_info f3;
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union cpt_frag_info f2;
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union cpt_frag_info f1;
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union cpt_frag_info f0;
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};
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} w0;
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/* WORD 1 */
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union {
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uint64_t u64;
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struct {
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uint16_t frag_size3;
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uint16_t frag_size2;
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uint16_t frag_size1;
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uint16_t frag_size0;
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};
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} w1;
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};
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#endif /* __CPT_HW_H__ */
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@ -57,6 +57,11 @@
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#define PCI_DEVID_CN9K_CGX 0xA059
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#define PCI_DEVID_CN10K_RPM 0xA060
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#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD
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#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE
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#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
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#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
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#define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900
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#define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
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@ -67,6 +72,7 @@
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#define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
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/* HW structure definition */
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#include "hw/cpt.h"
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#include "hw/nix.h"
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#include "hw/npa.h"
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#include "hw/npc.h"
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