net/liquidio: add API to send packet to device
Add API to send control and data packets to device. Request list keeps track of host buffers to be freed till it reaches device. Signed-off-by: Shijith Thotton <shijith.thotton@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Venkat Koppula <venkat.koppula@caviumnetworks.com> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com> Signed-off-by: Mallesham Jatharakonda <mjatharakonda@oneconvergence.com>
This commit is contained in:
Shijith Thotton
Ferruh Yigit
parent
9a84a107b0
commit
64af21f803
@ -76,6 +76,8 @@ enum lio_card_type {
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#define LIO_23XX_NAME "23xx"
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#define LIO_DEV_RUNNING 0xc
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#define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
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((cfg)->default_config->num_def_tx_descs)
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@ -93,6 +95,15 @@ enum lio_card_type {
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#define LIO_BASE_MINOR_VERSION 5
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#define LIO_BASE_MICRO_VERSION 1
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/** Tag types used by Octeon cores in its work. */
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enum octeon_tag_type {
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OCTEON_ORDERED_TAG = 0,
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OCTEON_ATOMIC_TAG = 1,
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};
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/* pre-defined host->NIC tag values */
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#define LIO_CONTROL (0x11111110)
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/* Routines for reading and writing CSRs */
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#ifdef RTE_LIBRTE_LIO_DEBUG_REGS
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#define lio_write_csr(lio_dev, reg_off, value) \
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@ -207,6 +207,186 @@ lio_free_instr_queue0(struct lio_device *lio_dev)
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lio_dev->num_iqs--;
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}
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static inline void
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lio_ring_doorbell(struct lio_device *lio_dev,
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struct lio_instr_queue *iq)
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{
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if (rte_atomic64_read(&lio_dev->status) == LIO_DEV_RUNNING) {
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rte_write32(iq->fill_cnt, iq->doorbell_reg);
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/* make sure doorbell write goes through */
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rte_wmb();
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iq->fill_cnt = 0;
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}
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}
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static inline void
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copy_cmd_into_iq(struct lio_instr_queue *iq, uint8_t *cmd)
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{
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uint8_t *iqptr, cmdsize;
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cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
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iqptr = iq->base_addr + (cmdsize * iq->host_write_index);
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rte_memcpy(iqptr, cmd, cmdsize);
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}
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static inline struct lio_iq_post_status
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post_command2(struct lio_instr_queue *iq, uint8_t *cmd)
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{
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struct lio_iq_post_status st;
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st.status = LIO_IQ_SEND_OK;
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/* This ensures that the read index does not wrap around to the same
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* position if queue gets full before Octeon could fetch any instr.
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*/
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if (rte_atomic64_read(&iq->instr_pending) >=
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(int32_t)(iq->max_count - 1)) {
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st.status = LIO_IQ_SEND_FAILED;
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st.index = -1;
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return st;
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}
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if (rte_atomic64_read(&iq->instr_pending) >=
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(int32_t)(iq->max_count - 2))
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st.status = LIO_IQ_SEND_STOP;
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copy_cmd_into_iq(iq, cmd);
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/* "index" is returned, host_write_index is modified. */
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st.index = iq->host_write_index;
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iq->host_write_index = lio_incr_index(iq->host_write_index, 1,
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iq->max_count);
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iq->fill_cnt++;
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/* Flush the command into memory. We need to be sure the data is in
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* memory before indicating that the instruction is pending.
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*/
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rte_wmb();
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rte_atomic64_inc(&iq->instr_pending);
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return st;
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}
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static inline void
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lio_add_to_request_list(struct lio_instr_queue *iq,
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int idx, void *buf, int reqtype)
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{
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iq->request_list[idx].buf = buf;
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iq->request_list[idx].reqtype = reqtype;
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}
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static int
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lio_send_command(struct lio_device *lio_dev, uint32_t iq_no, void *cmd,
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void *buf, uint32_t datasize __rte_unused, uint32_t reqtype)
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{
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struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no];
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struct lio_iq_post_status st;
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rte_spinlock_lock(&iq->post_lock);
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st = post_command2(iq, cmd);
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if (st.status != LIO_IQ_SEND_FAILED) {
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lio_add_to_request_list(iq, st.index, buf, reqtype);
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lio_ring_doorbell(lio_dev, iq);
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}
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rte_spinlock_unlock(&iq->post_lock);
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return st.status;
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}
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void
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lio_prepare_soft_command(struct lio_device *lio_dev,
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struct lio_soft_command *sc, uint8_t opcode,
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uint8_t subcode, uint32_t irh_ossp, uint64_t ossp0,
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uint64_t ossp1)
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{
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struct octeon_instr_pki_ih3 *pki_ih3;
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struct octeon_instr_ih3 *ih3;
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struct octeon_instr_irh *irh;
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struct octeon_instr_rdp *rdp;
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RTE_ASSERT(opcode <= 15);
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RTE_ASSERT(subcode <= 127);
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ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
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ih3->pkind = lio_dev->instr_queue[sc->iq_no]->txpciq.s.pkind;
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pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3;
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pki_ih3->w = 1;
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pki_ih3->raw = 1;
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pki_ih3->utag = 1;
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pki_ih3->uqpg = lio_dev->instr_queue[sc->iq_no]->txpciq.s.use_qpg;
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pki_ih3->utt = 1;
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pki_ih3->tag = LIO_CONTROL;
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pki_ih3->tagtype = OCTEON_ATOMIC_TAG;
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pki_ih3->qpg = lio_dev->instr_queue[sc->iq_no]->txpciq.s.qpg;
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pki_ih3->pm = 0x7;
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pki_ih3->sl = 8;
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if (sc->datasize)
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ih3->dlengsz = sc->datasize;
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irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
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irh->opcode = opcode;
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irh->subcode = subcode;
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/* opcode/subcode specific parameters (ossp) */
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irh->ossp = irh_ossp;
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sc->cmd.cmd3.ossp[0] = ossp0;
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sc->cmd.cmd3.ossp[1] = ossp1;
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if (sc->rdatasize) {
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rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp;
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rdp->pcie_port = lio_dev->pcie_port;
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rdp->rlen = sc->rdatasize;
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irh->rflag = 1;
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/* PKI IH3 */
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ih3->fsz = OCTEON_SOFT_CMD_RESP_IH3;
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} else {
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irh->rflag = 0;
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/* PKI IH3 */
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ih3->fsz = OCTEON_PCI_CMD_O3;
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}
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}
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int
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lio_send_soft_command(struct lio_device *lio_dev,
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struct lio_soft_command *sc)
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{
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struct octeon_instr_ih3 *ih3;
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struct octeon_instr_irh *irh;
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uint32_t len = 0;
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ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
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if (ih3->dlengsz) {
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RTE_ASSERT(sc->dmadptr);
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sc->cmd.cmd3.dptr = sc->dmadptr;
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}
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irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
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if (irh->rflag) {
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RTE_ASSERT(sc->dmarptr);
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RTE_ASSERT(sc->status_word != NULL);
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*sc->status_word = LIO_COMPLETION_WORD_INIT;
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sc->cmd.cmd3.rptr = sc->dmarptr;
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}
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len = (uint32_t)ih3->dlengsz;
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if (sc->wait_time)
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sc->timeout = lio_uptime + sc->wait_time;
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return lio_send_command(lio_dev, sc->iq_no, &sc->cmd, sc, len,
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LIO_REQTYPE_SOFT_COMMAND);
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}
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int
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lio_setup_sc_buffer_pool(struct lio_device *lio_dev)
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{
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@ -50,11 +50,53 @@
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#define lio_uptime \
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(size_t)(rte_get_timer_cycles() / rte_get_timer_hz())
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#define LIO_IQ_SEND_OK 0
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#define LIO_IQ_SEND_STOP 1
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#define LIO_IQ_SEND_FAILED -1
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/* conditions */
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#define LIO_REQTYPE_NONE 0
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#define LIO_REQTYPE_NORESP_NET 1
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#define LIO_REQTYPE_NORESP_NET_SG 2
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#define LIO_REQTYPE_SOFT_COMMAND 3
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struct lio_request_list {
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uint32_t reqtype;
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void *buf;
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};
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/*---------------------- INSTRUCTION FORMAT ----------------------------*/
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struct lio_instr3_64B {
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/** Pointer where the input data is available. */
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uint64_t dptr;
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/** Instruction Header. */
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uint64_t ih3;
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/** Instruction Header. */
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uint64_t pki_ih3;
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/** Input Request Header. */
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uint64_t irh;
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/** opcode/subcode specific parameters */
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uint64_t ossp[2];
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/** Return Data Parameters */
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uint64_t rdp;
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/** Pointer where the response for a RAW mode packet will be written
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* by Octeon.
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*/
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uint64_t rptr;
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};
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union lio_instr_64B {
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struct lio_instr3_64B cmd3;
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};
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/** The size of each buffer in soft command buffer pool */
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#define LIO_SOFT_COMMAND_BUFFER_SIZE 1536
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@ -67,6 +109,9 @@ struct lio_soft_command {
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uint64_t dma_addr;
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uint32_t size;
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/** Command and return status */
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union lio_instr_64B cmd;
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#define LIO_COMPLETION_WORD_INIT 0xffffffffffffffffULL
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uint64_t *status_word;
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@ -93,6 +138,230 @@ struct lio_soft_command {
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struct rte_mbuf *mbuf;
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};
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struct lio_iq_post_status {
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int status;
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int index;
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};
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/* wqe
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* --------------- 0
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* | wqe word0-3 |
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* --------------- 32
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* | PCI IH |
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* --------------- 40
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* | RPTR |
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* --------------- 48
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* | PCI IRH |
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* --------------- 56
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* | OCTEON_CMD |
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* --------------- 64
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* | Addtl 8-BData |
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* | |
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* ---------------
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*/
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union octeon_cmd {
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uint64_t cmd64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t cmd : 5;
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uint64_t more : 6; /* How many udd words follow the command */
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uint64_t reserved : 29;
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uint64_t param1 : 16;
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uint64_t param2 : 8;
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#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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uint64_t param2 : 8;
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uint64_t param1 : 16;
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uint64_t reserved : 29;
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uint64_t more : 6;
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uint64_t cmd : 5;
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#endif
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} s;
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};
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#define OCTEON_CMD_SIZE (sizeof(union octeon_cmd))
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/* Instruction Header */
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struct octeon_instr_ih3 {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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/** Reserved3 */
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uint64_t reserved3 : 1;
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/** Gather indicator 1=gather*/
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uint64_t gather : 1;
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/** Data length OR no. of entries in gather list */
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uint64_t dlengsz : 14;
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/** Front Data size */
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uint64_t fsz : 6;
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/** Reserved2 */
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uint64_t reserved2 : 4;
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/** PKI port kind - PKIND */
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uint64_t pkind : 6;
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/** Reserved1 */
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uint64_t reserved1 : 32;
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#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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/** Reserved1 */
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uint64_t reserved1 : 32;
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/** PKI port kind - PKIND */
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uint64_t pkind : 6;
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/** Reserved2 */
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uint64_t reserved2 : 4;
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/** Front Data size */
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uint64_t fsz : 6;
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/** Data length OR no. of entries in gather list */
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uint64_t dlengsz : 14;
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/** Gather indicator 1=gather*/
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uint64_t gather : 1;
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/** Reserved3 */
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uint64_t reserved3 : 1;
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#endif
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};
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/* PKI Instruction Header(PKI IH) */
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struct octeon_instr_pki_ih3 {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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/** Wider bit */
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uint64_t w : 1;
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/** Raw mode indicator 1 = RAW */
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uint64_t raw : 1;
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/** Use Tag */
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uint64_t utag : 1;
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/** Use QPG */
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uint64_t uqpg : 1;
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/** Reserved2 */
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uint64_t reserved2 : 1;
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/** Parse Mode */
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uint64_t pm : 3;
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/** Skip Length */
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uint64_t sl : 8;
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/** Use Tag Type */
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uint64_t utt : 1;
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/** Tag type */
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uint64_t tagtype : 2;
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/** Reserved1 */
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uint64_t reserved1 : 2;
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/** QPG Value */
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uint64_t qpg : 11;
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/** Tag Value */
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uint64_t tag : 32;
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#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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/** Tag Value */
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uint64_t tag : 32;
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/** QPG Value */
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uint64_t qpg : 11;
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/** Reserved1 */
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uint64_t reserved1 : 2;
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/** Tag type */
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uint64_t tagtype : 2;
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/** Use Tag Type */
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uint64_t utt : 1;
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/** Skip Length */
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uint64_t sl : 8;
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/** Parse Mode */
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uint64_t pm : 3;
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/** Reserved2 */
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uint64_t reserved2 : 1;
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/** Use QPG */
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uint64_t uqpg : 1;
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/** Use Tag */
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uint64_t utag : 1;
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/** Raw mode indicator 1 = RAW */
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uint64_t raw : 1;
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/** Wider bit */
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uint64_t w : 1;
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#endif
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};
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/** Input Request Header */
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struct octeon_instr_irh {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t opcode : 4;
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uint64_t rflag : 1;
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uint64_t subcode : 7;
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uint64_t vlan : 12;
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uint64_t priority : 3;
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uint64_t reserved : 5;
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uint64_t ossp : 32; /* opcode/subcode specific parameters */
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#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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uint64_t ossp : 32; /* opcode/subcode specific parameters */
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uint64_t reserved : 5;
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uint64_t priority : 3;
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uint64_t vlan : 12;
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uint64_t subcode : 7;
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uint64_t rflag : 1;
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uint64_t opcode : 4;
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#endif
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};
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/* pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
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#define OCTEON_SOFT_CMD_RESP_IH3 (40 + 8)
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/* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */
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#define OCTEON_PCI_CMD_O3 (24 + 8)
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/** Return Data Parameters */
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struct octeon_instr_rdp {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t reserved : 49;
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uint64_t pcie_port : 3;
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uint64_t rlen : 12;
|
||||
#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
|
||||
uint64_t rlen : 12;
|
||||
uint64_t pcie_port : 3;
|
||||
uint64_t reserved : 49;
|
||||
#endif
|
||||
};
|
||||
|
||||
int lio_setup_sc_buffer_pool(struct lio_device *lio_dev);
|
||||
void lio_free_sc_buffer_pool(struct lio_device *lio_dev);
|
||||
|
||||
@ -100,6 +369,13 @@ struct lio_soft_command *
|
||||
lio_alloc_soft_command(struct lio_device *lio_dev,
|
||||
uint32_t datasize, uint32_t rdatasize,
|
||||
uint32_t ctxsize);
|
||||
void lio_prepare_soft_command(struct lio_device *lio_dev,
|
||||
struct lio_soft_command *sc,
|
||||
uint8_t opcode, uint8_t subcode,
|
||||
uint32_t irh_ossp, uint64_t ossp0,
|
||||
uint64_t ossp1);
|
||||
int lio_send_soft_command(struct lio_device *lio_dev,
|
||||
struct lio_soft_command *sc);
|
||||
void lio_free_soft_command(struct lio_soft_command *sc);
|
||||
|
||||
/** Maximum ordered requests to process in every invocation of
|
||||
@ -167,6 +443,21 @@ lio_swap_8B_data(uint64_t *data, uint32_t blocks)
|
||||
}
|
||||
}
|
||||
|
||||
/* Macro to increment index.
|
||||
* Index is incremented by count; if the sum exceeds
|
||||
* max, index is wrapped-around to the start.
|
||||
*/
|
||||
static inline uint32_t
|
||||
lio_incr_index(uint32_t index, uint32_t count, uint32_t max)
|
||||
{
|
||||
if ((index + count) >= max)
|
||||
index = index + count - max;
|
||||
else
|
||||
index += count;
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
/** Setup instruction queue zero for the device
|
||||
* @param lio_dev which lio device to setup
|
||||
*
|
||||
|
||||
@ -288,6 +288,12 @@ struct lio_device {
|
||||
uint16_t pf_num;
|
||||
uint16_t vf_num;
|
||||
|
||||
/** This device's PCIe port used for traffic. */
|
||||
uint16_t pcie_port;
|
||||
|
||||
/** The state of this device */
|
||||
rte_atomic64_t status;
|
||||
|
||||
uint8_t *hw_addr;
|
||||
|
||||
struct lio_fn_list fn_list;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user