raw/ntb: fix write memory barrier
All buffers and ring info should be written before tail register update.
This patch relocates the write memory barrier before updating tail register
to avoid potential issues.
Fixes: 11b5c7daf0
("raw/ntb: add enqueue and dequeue functions")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
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@ -683,8 +683,8 @@ ntb_enqueue_bufs(struct rte_rawdev *dev,
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sizeof(struct ntb_used) * nb1);
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rte_memcpy(txq->tx_used_ring, tx_used + nb1,
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sizeof(struct ntb_used) * nb2);
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*txq->used_cnt = txq->last_used;
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rte_wmb();
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*txq->used_cnt = txq->last_used;
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/* update queue stats */
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hw->ntb_xstats[NTB_TX_BYTES_ID + off] += bytes;
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@ -789,8 +789,8 @@ ntb_dequeue_bufs(struct rte_rawdev *dev,
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sizeof(struct ntb_desc) * nb1);
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rte_memcpy(rxq->rx_desc_ring, rx_desc + nb1,
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sizeof(struct ntb_desc) * nb2);
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*rxq->avail_cnt = rxq->last_avail;
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rte_wmb();
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*rxq->avail_cnt = rxq->last_avail;
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/* update queue stats */
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off = NTB_XSTATS_NUM * ((size_t)context + 1);
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