raw/ntb: fix write memory barrier

All buffers and ring info should be written before tail register update.
This patch relocates the write memory barrier before updating tail register
to avoid potential issues.

Fixes: 11b5c7daf0 ("raw/ntb: add enqueue and dequeue functions")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Xiaoyun Li 2019-12-04 23:19:16 +08:00 committed by Thomas Monjalon
parent aebdf3cadc
commit 657cd1370d

View File

@ -683,8 +683,8 @@ ntb_enqueue_bufs(struct rte_rawdev *dev,
sizeof(struct ntb_used) * nb1);
rte_memcpy(txq->tx_used_ring, tx_used + nb1,
sizeof(struct ntb_used) * nb2);
*txq->used_cnt = txq->last_used;
rte_wmb();
*txq->used_cnt = txq->last_used;
/* update queue stats */
hw->ntb_xstats[NTB_TX_BYTES_ID + off] += bytes;
@ -789,8 +789,8 @@ ntb_dequeue_bufs(struct rte_rawdev *dev,
sizeof(struct ntb_desc) * nb1);
rte_memcpy(rxq->rx_desc_ring, rx_desc + nb1,
sizeof(struct ntb_desc) * nb2);
*rxq->avail_cnt = rxq->last_avail;
rte_wmb();
*rxq->avail_cnt = rxq->last_avail;
/* update queue stats */
off = NTB_XSTATS_NUM * ((size_t)context + 1);