event/cnxk: fix packet Tx overflow
The transmit loop incorrectly assumes that nb_mbufs is always
a multiple of 4 when transmitting an event vector. The max
size of the vector might not be reached and pushed out early
due to timeout.
Fixes: 761a321acf91 ("event/cnxk: support vectorized Tx event fast path")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This commit is contained in:
Pavan Nikhilesh
Jerin Jacob
parent
bd64a963d2
commit
671971c917
@ -7,10 +7,10 @@
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#include <rte_vect.h>
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#include "cn10k_cryptodev_ops.h"
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#include "cnxk_ethdev.h"
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#include "cnxk_eventdev.h"
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#include "cnxk_worker.h"
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#include "cn10k_cryptodev_ops.h"
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#include "cn10k_ethdev.h"
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#include "cn10k_rx.h"
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@ -237,18 +237,16 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
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cq_w1 = *(uint64_t *)(gw.u64[1] + 8);
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sa_base = cnxk_nix_sa_base_get(port,
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lookup_mem);
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sa_base =
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cnxk_nix_sa_base_get(port, lookup_mem);
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sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
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mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(cq_w1,
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sa_base, (uintptr_t)&iova,
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&loff, (struct rte_mbuf *)mbuf,
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d_off);
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mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(
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cq_w1, sa_base, (uintptr_t)&iova, &loff,
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(struct rte_mbuf *)mbuf, d_off);
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if (loff)
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roc_npa_aura_op_free(m->pool->pool_id,
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0, iova);
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}
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gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
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@ -396,6 +394,56 @@ cn10k_sso_hws_xtract_meta(struct rte_mbuf *m,
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txq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];
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}
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static __rte_always_inline void
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cn10k_sso_tx_one(struct rte_mbuf *m, uint64_t *cmd, uint16_t lmt_id,
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uintptr_t lmt_addr, uint8_t sched_type, uintptr_t base,
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const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
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const uint32_t flags)
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{
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uint8_t lnum = 0, loff = 0, shft = 0;
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struct cn10k_eth_txq *txq;
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uintptr_t laddr;
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uint16_t segdw;
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uintptr_t pa;
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bool sec;
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txq = cn10k_sso_hws_xtract_meta(m, txq_data);
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cn10k_nix_tx_skeleton(txq, cmd, flags);
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/* Perform header writes before barrier
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* for TSO
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*/
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if (flags & NIX_TX_OFFLOAD_TSO_F)
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cn10k_nix_xmit_prepare_tso(m, flags);
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cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
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laddr = lmt_addr;
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/* Prepare CPT instruction and get nixtx addr if
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* it is for CPT on same lmtline.
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*/
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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cn10k_nix_prep_sec(m, cmd, &laddr, lmt_addr, &lnum, &loff,
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&shft, txq->sa_base, flags);
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/* Move NIX desc to LMT/NIXTX area */
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cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
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if (flags & NIX_TX_MULTI_SEG_F)
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segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)laddr, flags);
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else
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segdw = cn10k_nix_tx_ext_subs(flags) + 2;
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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pa = txq->cpt_io_addr | 3 << 4;
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else
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pa = txq->io_addr | ((segdw - 1) << 4);
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if (!sched_type)
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roc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);
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roc_lmt_submit_steorl(lmt_id, pa);
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}
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static __rte_always_inline void
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cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
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uint64_t *cmd, uint16_t lmt_id, uintptr_t lmt_addr,
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@ -404,11 +452,13 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
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const uint32_t flags)
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{
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uint16_t port[4], queue[4];
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uint16_t i, j, pkts, scalar;
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struct cn10k_eth_txq *txq;
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uint16_t i, j;
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uintptr_t pa;
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for (i = 0; i < nb_mbufs; i += 4) {
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scalar = nb_mbufs & (NIX_DESCS_PER_LOOP - 1);
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pkts = RTE_ALIGN_FLOOR(nb_mbufs, NIX_DESCS_PER_LOOP);
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for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
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port[0] = mbufs[i]->port;
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port[1] = mbufs[i + 1]->port;
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port[2] = mbufs[i + 2]->port;
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@ -421,66 +471,25 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
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if (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||
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((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
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for (j = 0; j < 4; j++) {
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uint8_t lnum = 0, loff = 0, shft = 0;
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struct rte_mbuf *m = mbufs[i + j];
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uintptr_t laddr;
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uint16_t segdw;
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bool sec;
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txq = (struct cn10k_eth_txq *)
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txq_data[port[j]][queue[j]];
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cn10k_nix_tx_skeleton(txq, cmd, flags);
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/* Perform header writes before barrier
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* for TSO
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*/
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if (flags & NIX_TX_OFFLOAD_TSO_F)
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cn10k_nix_xmit_prepare_tso(m, flags);
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cn10k_nix_xmit_prepare(m, cmd, flags,
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txq->lso_tun_fmt, &sec);
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laddr = lmt_addr;
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/* Prepare CPT instruction and get nixtx addr if
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* it is for CPT on same lmtline.
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*/
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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cn10k_nix_prep_sec(m, cmd, &laddr,
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lmt_addr, &lnum,
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&loff, &shft,
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txq->sa_base, flags);
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/* Move NIX desc to LMT/NIXTX area */
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cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
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if (flags & NIX_TX_MULTI_SEG_F) {
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segdw = cn10k_nix_prepare_mseg(m,
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(uint64_t *)laddr, flags);
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} else {
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segdw = cn10k_nix_tx_ext_subs(flags) +
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2;
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}
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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pa = txq->cpt_io_addr | 3 << 4;
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else
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pa = txq->io_addr | ((segdw - 1) << 4);
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if (!sched_type)
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roc_sso_hws_head_wait(base +
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SSOW_LF_GWS_TAG);
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roc_lmt_submit_steorl(lmt_id, pa);
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}
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for (j = 0; j < 4; j++)
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cn10k_sso_tx_one(mbufs[i + j], cmd, lmt_id,
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lmt_addr, sched_type, base,
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txq_data, flags);
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} else {
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txq = (struct cn10k_eth_txq *)
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txq_data[port[0]][queue[0]];
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cn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd, base
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+ SSOW_LF_GWS_TAG,
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cn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd,
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base + SSOW_LF_GWS_TAG,
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flags | NIX_TX_VWQE_F);
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}
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}
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mbufs += i;
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for (i = 0; i < scalar; i++) {
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cn10k_sso_tx_one(mbufs[i], cmd, lmt_id, lmt_addr, sched_type,
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base, txq_data, flags);
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}
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}
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static __rte_always_inline uint16_t
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@ -489,19 +498,14 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
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const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
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const uint32_t flags)
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{
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uint8_t lnum = 0, loff = 0, shft = 0;
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struct cn10k_eth_txq *txq;
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uint16_t ref_cnt, segdw;
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struct rte_mbuf *m;
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uintptr_t lmt_addr;
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uintptr_t c_laddr;
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uint16_t ref_cnt;
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uint16_t lmt_id;
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uintptr_t pa;
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bool sec;
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lmt_addr = ws->lmt_base;
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ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
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c_laddr = lmt_addr;
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if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
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struct rte_mbuf **mbufs = ev->vec->mbufs;
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@ -526,38 +530,8 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
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m = ev->mbuf;
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ref_cnt = m->refcnt;
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txq = cn10k_sso_hws_xtract_meta(m, txq_data);
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cn10k_nix_tx_skeleton(txq, cmd, flags);
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/* Perform header writes before barrier for TSO */
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if (flags & NIX_TX_OFFLOAD_TSO_F)
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cn10k_nix_xmit_prepare_tso(m, flags);
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cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
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/* Prepare CPT instruction and get nixtx addr if
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* it is for CPT on same lmtline.
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*/
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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cn10k_nix_prep_sec(m, cmd, &lmt_addr, c_laddr, &lnum, &loff,
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&shft, txq->sa_base, flags);
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/* Move NIX desc to LMT/NIXTX area */
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cn10k_nix_xmit_mv_lmt_base(lmt_addr, cmd, flags);
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if (flags & NIX_TX_MULTI_SEG_F) {
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segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)lmt_addr, flags);
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} else {
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segdw = cn10k_nix_tx_ext_subs(flags) + 2;
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}
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if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
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pa = txq->cpt_io_addr | 3 << 4;
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else
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pa = txq->io_addr | ((segdw - 1) << 4);
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if (!ev->sched_type)
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roc_sso_hws_head_wait(ws->tx_base + SSOW_LF_GWS_TAG);
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roc_lmt_submit_steorl(lmt_id, pa);
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cn10k_sso_tx_one(m, cmd, lmt_id, lmt_addr, ev->sched_type, ws->tx_base,
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txq_data, flags);
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if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
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if (ref_cnt > 1)
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