event/octeontx2: add port config functions
Add default config, setup and release functions for event ports i.e. SSO GWS. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This commit is contained in:
Pavan Nikhilesh
Jerin Jacob
parent
55e778ca46
commit
67b5f46864
@ -144,6 +144,12 @@ sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
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return 0;
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}
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static void
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otx2_sso_port_release(void *port)
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{
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rte_free(port);
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}
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static void
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otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
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{
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@ -151,13 +157,24 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
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RTE_SET_USED(queue_id);
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}
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static void
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sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
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{
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ws->tag_op = base + SSOW_LF_GWS_TAG;
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ws->wqp_op = base + SSOW_LF_GWS_WQP;
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ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
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ws->swtp_op = base + SSOW_LF_GWS_SWTP;
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ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
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ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
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}
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static int
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sso_configure_ports(const struct rte_eventdev *event_dev)
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{
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struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
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struct otx2_mbox *mbox = dev->mbox;
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uint8_t nb_lf;
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int rc;
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int i, rc;
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otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
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@ -175,6 +192,40 @@ sso_configure_ports(const struct rte_eventdev *event_dev)
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return -ENODEV;
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}
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for (i = 0; i < nb_lf; i++) {
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struct otx2_ssogws *ws;
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uintptr_t base;
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/* Free memory prior to re-allocation if needed */
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if (event_dev->data->ports[i] != NULL) {
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ws = event_dev->data->ports[i];
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rte_free(ws);
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ws = NULL;
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}
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/* Allocate event port memory */
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ws = rte_zmalloc_socket("otx2_sso_ws",
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sizeof(struct otx2_ssogws),
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RTE_CACHE_LINE_SIZE,
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event_dev->data->socket_id);
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if (ws == NULL) {
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otx2_err("Failed to alloc memory for port=%d", i);
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rc = -ENOMEM;
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break;
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}
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ws->port = i;
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base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
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sso_set_port_ops(ws, base);
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event_dev->data->ports[i] = ws;
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}
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if (rc < 0) {
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sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
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sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
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}
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return rc;
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}
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@ -459,6 +510,60 @@ otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
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return 0;
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}
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static void
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otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
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struct rte_event_port_conf *port_conf)
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{
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struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
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RTE_SET_USED(port_id);
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port_conf->new_event_threshold = dev->max_num_events;
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port_conf->dequeue_depth = 1;
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port_conf->enqueue_depth = 1;
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}
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static int
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otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
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const struct rte_event_port_conf *port_conf)
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{
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struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
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uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
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uint64_t val;
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uint16_t q;
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sso_func_trace("Port=%d", port_id);
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RTE_SET_USED(port_conf);
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if (event_dev->data->ports[port_id] == NULL) {
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otx2_err("Invalid port Id %d", port_id);
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return -EINVAL;
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}
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for (q = 0; q < dev->nb_event_queues; q++) {
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grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
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if (grps_base[q] == 0) {
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otx2_err("Failed to get grp[%d] base addr", q);
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return -EINVAL;
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}
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}
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/* Set get_work timeout for HWS */
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val = NSEC2USEC(dev->deq_tmo_ns) - 1;
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struct otx2_ssogws *ws = event_dev->data->ports[port_id];
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uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
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rte_memcpy(ws->grps_base, grps_base,
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sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
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ws->fc_mem = dev->fc_mem;
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ws->xaq_lmt = dev->xaq_lmt;
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otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
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otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
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return 0;
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}
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/* Initialize and register event driver with DPDK Application */
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static struct rte_eventdev_ops otx2_sso_ops = {
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.dev_infos_get = otx2_sso_info_get,
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@ -466,6 +571,9 @@ static struct rte_eventdev_ops otx2_sso_ops = {
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.queue_def_conf = otx2_sso_queue_def_conf,
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.queue_setup = otx2_sso_queue_setup,
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.queue_release = otx2_sso_queue_release,
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.port_def_conf = otx2_sso_port_def_conf,
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.port_setup = otx2_sso_port_setup,
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.port_release = otx2_sso_port_release,
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};
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#define OTX2_SSO_XAE_CNT "xae_cnt"
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@ -38,6 +38,42 @@
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#define SSO_LF_GGRP_AQ_THR (0x1e0ull)
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#define SSO_LF_GGRP_MISC_CNT (0x200ull)
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/* SSOW LF register offsets (BAR2) */
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#define SSOW_LF_GWS_LINKS (0x10ull)
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#define SSOW_LF_GWS_PENDWQP (0x40ull)
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#define SSOW_LF_GWS_PENDSTATE (0x50ull)
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#define SSOW_LF_GWS_NW_TIM (0x70ull)
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#define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)
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#define SSOW_LF_GWS_INT (0x100ull)
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#define SSOW_LF_GWS_INT_W1S (0x108ull)
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#define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)
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#define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)
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#define SSOW_LF_GWS_TAG (0x200ull)
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#define SSOW_LF_GWS_WQP (0x210ull)
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#define SSOW_LF_GWS_SWTP (0x220ull)
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#define SSOW_LF_GWS_PENDTAG (0x230ull)
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#define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)
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#define SSOW_LF_GWS_OP_GET_WORK (0x600ull)
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#define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)
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#define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)
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#define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)
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#define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)
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#define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)
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#define SSOW_LF_GWS_OP_DESCHED (0x880ull)
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#define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)
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#define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)
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#define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)
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#define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)
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#define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)
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#define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)
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#define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)
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#define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)
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#define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)
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#define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)
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#define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)
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#define NSEC2USEC(__ns) ((__ns) / 1E3)
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#define USEC2NSEC(__us) ((__us) * 1E3)
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enum otx2_sso_lf_type {
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@ -70,6 +106,29 @@ struct otx2_sso_evdev {
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uint32_t iue;
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} __rte_cache_aligned;
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#define OTX2_SSOGWS_OPS \
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/* WS ops */ \
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uintptr_t getwrk_op; \
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uintptr_t tag_op; \
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uintptr_t wqp_op; \
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uintptr_t swtp_op; \
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uintptr_t swtag_norm_op; \
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uintptr_t swtag_desched_op; \
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uint8_t cur_tt; \
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uint8_t cur_grp
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/* Event port aka GWS */
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struct otx2_ssogws {
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/* Get Work Fastpath data */
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OTX2_SSOGWS_OPS;
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uint8_t swtag_req;
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uint8_t port;
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/* Add Work Fastpath data */
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uint64_t xaq_lmt __rte_cache_aligned;
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uint64_t *fc_mem;
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uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
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} __rte_cache_aligned;
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static inline struct otx2_sso_evdev *
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sso_pmd_priv(const struct rte_eventdev *event_dev)
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{
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