eal: introduce I/O device memory read/write operations
This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device memory read/write operations along with the relaxed versions. The weakly-ordered machine like ARM needs additional I/O barrier for device memory read/write access over PCI bus. By introducing the eal abstraction for I/O device memory read/write access, The drivers can access I/O device memory in architecture agnostic manner. The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit is contained in:
Jerin Jacob
Thomas Monjalon
parent
2cf953cfd8
commit
69736db1d8
@ -70,7 +70,8 @@ There are many libraries, so their headers may be grouped by topics:
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[cache prefetch] (@ref rte_prefetch.h),
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[SIMD] (@ref rte_vect.h),
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[byte order] (@ref rte_byteorder.h),
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[CPU flags] (@ref rte_cpuflags.h)
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[CPU flags] (@ref rte_cpuflags.h),
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[I/O access] (@ref rte_io.h)
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- **CPU multicore**:
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[interrupts] (@ref rte_interrupts.h),
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@ -44,7 +44,8 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h
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GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h
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GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h
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GENERIC_INC += rte_vect.h
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GENERIC_INC += rte_vect.h rte_io.h
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# defined in mk/arch/$(RTE_ARCH)/rte.vars.mk
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ARCH_DIR ?= $(RTE_ARCH)
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ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))
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263
lib/librte_eal/common/include/generic/rte_io.h
Normal file
263
lib/librte_eal/common/include/generic/rte_io.h
Normal file
@ -0,0 +1,263 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2016 Cavium networks. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium networks nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTE_IO_H_
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#define _RTE_IO_H_
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/**
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* @file
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* I/O device memory operations
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*
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* This file defines the generic API for I/O device memory read/write operations
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*/
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#include <stdint.h>
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#include <rte_common.h>
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#include <rte_atomic.h>
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#ifdef __DOXYGEN__
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/**
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* Read a 8-bit value from I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint8_t
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rte_read8_relaxed(const volatile void *addr);
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/**
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* Read a 16-bit value from I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint16_t
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rte_read16_relaxed(const volatile void *addr);
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/**
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* Read a 32-bit value from I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint32_t
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rte_read32_relaxed(const volatile void *addr);
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/**
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* Read a 64-bit value from I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint64_t
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rte_read64_relaxed(const volatile void *addr);
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/**
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* Write a 8-bit value to I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write8_relaxed(uint8_t value, volatile void *addr);
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/**
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* Write a 16-bit value to I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write16_relaxed(uint16_t value, volatile void *addr);
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/**
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* Write a 32-bit value to I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write32_relaxed(uint32_t value, volatile void *addr);
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/**
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* Write a 64-bit value to I/O device memory address *addr*.
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*
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* The relaxed version does not have additional I/O memory barrier, useful in
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* accessing the device registers of integrated controllers which implicitly
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* strongly ordered with respect to memory access.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write64_relaxed(uint64_t value, volatile void *addr);
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/**
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* Read a 8-bit value from I/O device memory address *addr*.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint8_t
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rte_read8(const volatile void *addr);
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/**
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* Read a 16-bit value from I/O device memory address *addr*.
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*
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint16_t
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rte_read16(const volatile void *addr);
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/**
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* Read a 32-bit value from I/O device memory address *addr*.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint32_t
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rte_read32(const volatile void *addr);
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/**
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* Read a 64-bit value from I/O device memory address *addr*.
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*
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* @param addr
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* I/O memory address to read the value from
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* @return
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* read value
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*/
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static inline uint64_t
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rte_read64(const volatile void *addr);
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/**
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* Write a 8-bit value to I/O device memory address *addr*.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write8(uint8_t value, volatile void *addr);
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/**
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* Write a 16-bit value to I/O device memory address *addr*.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write16(uint16_t value, volatile void *addr);
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/**
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* Write a 32-bit value to I/O device memory address *addr*.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write32(uint32_t value, volatile void *addr);
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/**
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* Write a 64-bit value to I/O device memory address *addr*.
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*
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* @param value
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* Value to write
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* @param addr
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* I/O memory address to write the value to
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*/
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static inline void
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rte_write64(uint64_t value, volatile void *addr);
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#endif /* __DOXYGEN__ */
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#endif /* _RTE_IO_H_ */
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