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net/ice/base: remove redundant empty lines

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Remove redundant empty lines

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
This commit is contained in:
Qi Zhang 2019-09-23 15:44:19 +08:00 committed by Ferruh Yigit
parent 0ecc27f28d
commit 6b1172d4dc
17 changed files with 0 additions and 197 deletions
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111
drivers/net/ice/base/ice_adminq_cmd.h
View File

@ -9,12 +9,10 @@
* descriptor format. It is shared between Firmware and Software.
*/
#define ICE_MAX_VSI 768
#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
struct ice_aqc_generic {
__le32 param0;
__le32 param1;
@ -22,7 +20,6 @@ struct ice_aqc_generic {
__le32 addr_low;
};
/* Get version (direct 0x0001) */
struct ice_aqc_get_ver {
__le32 rom_ver;
@ -37,7 +34,6 @@ struct ice_aqc_get_ver {
u8 api_patch;
};
/* Send driver version (indirect 0x0002) */
struct ice_aqc_driver_ver {
u8 major_ver;
@ -49,7 +45,6 @@ struct ice_aqc_driver_ver {
__le32 addr_low;
};
/* Queue Shutdown (direct 0x0003) */
struct ice_aqc_q_shutdown {
u8 driver_unloading;
@ -57,9 +52,6 @@ struct ice_aqc_q_shutdown {
u8 reserved[15];
};
/* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009)
*/
@ -92,7 +84,6 @@ struct ice_aqc_req_res {
u8 reserved[2];
};
/* Get function capabilities (indirect 0x000A)
* Get device capabilities (indirect 0x000B)
*/
@ -105,7 +96,6 @@ struct ice_aqc_list_caps {
__le32 addr_low;
};
/* Device/Function buffer entry, repeated per reported capability */
struct ice_aqc_list_caps_elem {
__le16 cap;
@ -132,7 +122,6 @@ struct ice_aqc_list_caps_elem {
__le64 rsvd2;
};
/* Manage MAC address, read command - indirect (0x0107)
* This struct is also used for the response
*/
@ -153,7 +142,6 @@ struct ice_aqc_manage_mac_read {
__le32 addr_low;
};
/* Response buffer format for manage MAC read command */
struct ice_aqc_manage_mac_read_resp {
u8 lport_num;
@ -163,7 +151,6 @@ struct ice_aqc_manage_mac_read_resp {
u8 mac_addr[ETH_ALEN];
};
/* Manage MAC address, write command - direct (0x0108) */
struct ice_aqc_manage_mac_write {
u8 rsvd;
@ -182,7 +169,6 @@ struct ice_aqc_manage_mac_write {
__le32 addr_low;
};
/* Clear PXE Command and response (direct 0x0110) */
struct ice_aqc_clear_pxe {
u8 rx_cnt;
@ -190,7 +176,6 @@ struct ice_aqc_clear_pxe {
u8 reserved[15];
};
/* Configure No-Drop Policy Command (direct 0x0112) */
struct ice_aqc_config_no_drop_policy {
u8 opts;
@ -215,7 +200,6 @@ struct ice_aqc_get_sw_cfg {
__le32 addr_low;
};
/* Each entry in the response buffer is of the following type: */
struct ice_aqc_get_sw_cfg_resp_elem {
/* VSI/Port Number */
@ -242,7 +226,6 @@ struct ice_aqc_get_sw_cfg_resp_elem {
#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
};
/* The response buffer is as follows. Note that the length of the
* elements array varies with the length of the command response.
*/
@ -250,8 +233,6 @@ struct ice_aqc_get_sw_cfg_resp {
struct ice_aqc_get_sw_cfg_resp_elem elements[1];
};
/* These resource type defines are used for all switch resource
* commands where a resource type is required, such as:
* Get Resource Allocation command (indirect 0x0204)
@ -324,7 +305,6 @@ struct ice_aqc_get_res_resp {
struct ice_aqc_get_res_resp_elem elem[1];
};
/* Allocate Resources command (indirect 0x0208)
* Free Resources command (indirect 0x0209)
*/
@ -335,7 +315,6 @@ struct ice_aqc_alloc_free_res_cmd {
__le32 addr_low;
};
/* Resource descriptor */
struct ice_aqc_res_elem {
union {
@ -344,7 +323,6 @@ struct ice_aqc_res_elem {
} e;
};
/* Buffer for Allocate/Free Resources commands */
struct ice_aqc_alloc_free_res_elem {
__le16 res_type; /* Types defined above cmd 0x0204 */
@ -355,7 +333,6 @@ struct ice_aqc_alloc_free_res_elem {
struct ice_aqc_res_elem elem[1];
};
/* Get Allocated Resource Descriptors Command (indirect 0x020A) */
struct ice_aqc_get_allocd_res_desc {
union {
@ -379,7 +356,6 @@ struct ice_aqc_get_allocd_res_desc_resp {
struct ice_aqc_res_elem elem[1];
};
/* Add VSI (indirect 0x0210)
* Update VSI (indirect 0x0211)
* Get VSI (indirect 0x0212)
@ -405,7 +381,6 @@ struct ice_aqc_add_get_update_free_vsi {
__le32 addr_low;
};
/* Response descriptor for:
* Add VSI (indirect 0x0210)
* Update VSI (indirect 0x0211)
@ -420,7 +395,6 @@ struct ice_aqc_add_update_free_vsi_resp {
__le32 addr_low;
};
struct ice_aqc_get_vsi_resp {
__le16 vsi_num;
u8 vf_id;
@ -434,7 +408,6 @@ struct ice_aqc_get_vsi_resp {
__le32 addr_low;
};
struct ice_aqc_vsi_props {
__le16 valid_sections;
#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
@ -589,7 +562,6 @@ struct ice_aqc_vsi_props {
u8 reserved[24];
};
/* Add/update mirror rule - direct (0x0260) */
#define ICE_AQC_RULE_ID_VALID_S 7
#define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
@ -694,7 +666,6 @@ struct ice_aqc_storm_cfg {
__le32 reserved;
};
#define ICE_MAX_NUM_RECIPES 64
/* Add/Get Recipe (indirect 0x0290/0x0292)*/
@ -779,7 +750,6 @@ struct ice_aqc_sw_rules {
__le32 addr_low;
};
#pragma pack(1)
/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
* This structures describes the lookup rules and associated actions. "index"
@ -867,7 +837,6 @@ struct ice_sw_rule_lkup_rx_tx {
};
#pragma pack()
/* Add/Update/Remove large action command/response entry
* "index" is returned as part of a response to a successful Add command, and
* can be used to identify the action for Update/Get/Remove commands.
@ -928,7 +897,6 @@ struct ice_sw_rule_lg_act {
#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
};
/* Add/Update/Remove VSI list command/response entry
* "index" is returned as part of a response to a successful Add command, and
* can be used to identify the VSI list for Update/Get/Remove commands.
@ -939,7 +907,6 @@ struct ice_sw_rule_vsi_list {
__le16 vsi[1]; /* Array of number_vsi VSI numbers */
};
#pragma pack(1)
/* Query VSI list command/response entry */
struct ice_sw_rule_vsi_list_query {
@ -948,7 +915,6 @@ struct ice_sw_rule_vsi_list_query {
};
#pragma pack()
#pragma pack(1)
/* Add switch rule response:
* Content of return buffer is same as the input buffer. The status field and
@ -974,7 +940,6 @@ struct ice_aqc_sw_rules_elem {
#pragma pack()
/* PFC Ignore (direct 0x0301)
* The command and response use the same descriptor structure
*/
@ -1009,7 +974,6 @@ struct ice_aqc_set_dcb_params {
u8 rsvd[14];
};
/* Get Default Topology (indirect 0x0400) */
struct ice_aqc_get_topo {
u8 port_num;
@ -1020,7 +984,6 @@ struct ice_aqc_get_topo {
__le32 addr_low;
};
/* Update TSE (indirect 0x0403)
* Get TSE (indirect 0x0404)
* Add TSE (indirect 0x0401)
@ -1037,7 +1000,6 @@ struct ice_aqc_sched_elem_cmd {
__le32 addr_low;
};
/* This is the buffer for:
* Suspend Nodes (indirect 0x0409)
* Resume Nodes (indirect 0x040A)
@ -1046,7 +1008,6 @@ struct ice_aqc_suspend_resume_elem {
__le32 teid[1];
};
struct ice_aqc_txsched_move_grp_info_hdr {
__le32 src_parent_teid;
__le32 dest_parent_teid;
@ -1054,19 +1015,16 @@ struct ice_aqc_txsched_move_grp_info_hdr {
__le16 reserved;
};
struct ice_aqc_move_elem {
struct ice_aqc_txsched_move_grp_info_hdr hdr;
__le32 teid[1];
};
struct ice_aqc_elem_info_bw {
__le16 bw_profile_idx;
__le16 bw_alloc;
};
struct ice_aqc_txsched_elem {
u8 elem_type; /* Special field, reserved for some aq calls */
#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
@ -1098,50 +1056,42 @@ struct ice_aqc_txsched_elem {
__le16 reserved2;
};
struct ice_aqc_txsched_elem_data {
__le32 parent_teid;
__le32 node_teid;
struct ice_aqc_txsched_elem data;
};
struct ice_aqc_txsched_topo_grp_info_hdr {
__le32 parent_teid;
__le16 num_elems;
__le16 reserved2;
};
struct ice_aqc_add_elem {
struct ice_aqc_txsched_topo_grp_info_hdr hdr;
struct ice_aqc_txsched_elem_data generic[1];
};
struct ice_aqc_conf_elem {
struct ice_aqc_txsched_elem_data generic[1];
};
struct ice_aqc_get_elem {
struct ice_aqc_txsched_elem_data generic[1];
};
struct ice_aqc_get_topo_elem {
struct ice_aqc_txsched_topo_grp_info_hdr hdr;
struct ice_aqc_txsched_elem_data
generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
};
struct ice_aqc_delete_elem {
struct ice_aqc_txsched_topo_grp_info_hdr hdr;
__le32 teid[1];
};
/* Query Port ETS (indirect 0x040E)
*
* This indirect command is used to query port TC node configuration.
@ -1168,7 +1118,6 @@ struct ice_aqc_port_ets_elem {
__le32 tc_node_teid[8]; /* Used for response, reserved in command */
};
/* Rate limiting profile for
* Add RL profile (indirect 0x0410)
* Query RL profile (indirect 0x0411)
@ -1184,7 +1133,6 @@ struct ice_aqc_rl_profile {
__le32 addr_low;
};
struct ice_aqc_rl_profile_elem {
u8 level;
u8 flags;
@ -1204,13 +1152,10 @@ struct ice_aqc_rl_profile_elem {
__le16 rl_encode;
};
struct ice_aqc_rl_profile_generic_elem {
struct ice_aqc_rl_profile_elem generic[1];
};
/* Configure L2 Node CGD (indirect 0x0414)
* This indirect command allows configuring a congestion domain for given L2
* node TEIDs in the scheduler topology.
@ -1222,19 +1167,16 @@ struct ice_aqc_cfg_l2_node_cgd {
__le32 addr_low;
};
struct ice_aqc_cfg_l2_node_cgd_elem {
__le32 node_teid;
u8 cgd;
u8 reserved[3];
};
struct ice_aqc_cfg_l2_node_cgd_data {
struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
};
/* Query Scheduler Resource Allocation (indirect 0x0412)
* This indirect command retrieves the scheduler resources allocated by
* EMP Firmware to the given PF.
@ -1245,7 +1187,6 @@ struct ice_aqc_query_txsched_res {
__le32 addr_low;
};
struct ice_aqc_generic_sched_props {
__le16 phys_levels;
__le16 logical_levels;
@ -1257,7 +1198,6 @@ struct ice_aqc_generic_sched_props {
u8 rsvd1[22];
};
struct ice_aqc_layer_props {
u8 logical_layer;
u8 chunk_size;
@ -1271,13 +1211,11 @@ struct ice_aqc_layer_props {
u8 rsvd1[14];
};
struct ice_aqc_query_txsched_res_resp {
struct ice_aqc_generic_sched_props sched_props;
struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
};
/* Query Node to Root Topology (indirect 0x0413)
* This command uses ice_aqc_get_elem as its data buffer.
*/
@ -1288,7 +1226,6 @@ struct ice_aqc_query_node_to_root {
__le32 addr_low;
};
/* Get PHY capabilities (indirect 0x0600) */
struct ice_aqc_get_phy_caps {
u8 lport_num;
@ -1311,7 +1248,6 @@ struct ice_aqc_get_phy_caps {
__le32 addr_low;
};
/* This is #define of PHY type (Extended):
* The first set of defines is for phy_type_low.
*/
@ -1453,7 +1389,6 @@ struct ice_aqc_get_phy_caps_data {
} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
};
/* Set PHY capabilities (direct 0x0601)
* NOTE: This command must be followed by setup link and restart auto-neg
*/
@ -1464,7 +1399,6 @@ struct ice_aqc_set_phy_cfg {
__le32 addr_low;
};
/* Set PHY config command data structure */
struct ice_aqc_set_phy_cfg_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
@ -1485,7 +1419,6 @@ struct ice_aqc_set_phy_cfg_data {
u8 rsvd1;
};
/* Set MAC Config command data structure (direct 0x0603) */
struct ice_aqc_set_mac_cfg {
__le16 max_frame_size;
@ -1505,7 +1438,6 @@ struct ice_aqc_set_mac_cfg {
u8 reserved[7];
};
/* Restart AN command data structure (direct 0x0605)
* Also used for response, with only the lport_num field present.
*/
@ -1518,7 +1450,6 @@ struct ice_aqc_restart_an {
u8 reserved2[13];
};
/* Get link status (indirect 0x0607), also used for Link Status Event */
struct ice_aqc_get_link_status {
u8 lport_num;
@ -1535,7 +1466,6 @@ struct ice_aqc_get_link_status {
__le32 addr_low;
};
/* Get link status response data structure, also used for Link Status Event */
struct ice_aqc_get_link_status_data {
u8 topo_media_conflict;
@ -1621,7 +1551,6 @@ struct ice_aqc_get_link_status_data {
__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
};
/* Set event mask command (direct 0x0613) */
struct ice_aqc_set_event_mask {
u8 lport_num;
@ -1641,8 +1570,6 @@ struct ice_aqc_set_event_mask {
u8 reserved1[6];
};
/* Set MAC Loopback command (direct 0x0620) */
struct ice_aqc_set_mac_lb {
u8 lb_mode;
@ -1651,9 +1578,6 @@ struct ice_aqc_set_mac_lb {
u8 reserved[15];
};
struct ice_aqc_link_topo_addr {
u8 lport_num;
u8 lport_num_valid;
@ -1716,8 +1640,6 @@ struct ice_aqc_set_port_id_led {
u8 rsvd[13];
};
/* Read/Write SFF EEPROM command (indirect 0x06EE) */
struct ice_aqc_sff_eeprom {
u8 lport_num;
@ -1797,7 +1719,6 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {
u8 cmd_flags;
@ -1812,14 +1733,12 @@ struct ice_aqc_nvm_cfg {
__le32 addr_low;
};
struct ice_aqc_nvm_cfg_data {
__le16 field_id;
__le16 field_options;
__le16 field_value;
};
/* NVM Checksum Command (direct, 0x0706) */
struct ice_aqc_nvm_checksum {
u8 flags;
@ -1831,9 +1750,6 @@ struct ice_aqc_nvm_checksum {
u8 rsvd2[12];
};
/* Get LLDP MIB (indirect 0x0A00)
* Note: This is also used by the LLDP MIB Change Event (0x0A01)
* as the format is the same.
@ -1985,7 +1901,6 @@ struct ice_aqc_lldp_stop_start_specific_agent {
u8 reserved[15];
};
/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
struct ice_aqc_get_set_rss_key {
#define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
@ -1997,7 +1912,6 @@ struct ice_aqc_get_set_rss_key {
__le32 addr_low;
};
#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
@ -2019,7 +1933,6 @@ struct ice_aqc_get_set_rss_keys {
u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
};
/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
struct ice_aqc_get_set_rss_lut {
#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
@ -2055,7 +1968,6 @@ struct ice_aqc_get_set_rss_lut {
__le32 addr_low;
};
/* Clear FD Table Command (direct, 0x0B06) */
struct ice_aqc_clear_fd_table {
u8 clear_type;
@ -2066,9 +1978,6 @@ struct ice_aqc_clear_fd_table {
u8 reserved[12];
};
/* Add Tx LAN Queues (indirect 0x0C30) */
struct ice_aqc_add_txqs {
u8 num_qgrps;
@ -2078,7 +1987,6 @@ struct ice_aqc_add_txqs {
__le32 addr_low;
};
/* This is the descriptor of each queue entry for the Add Tx LAN Queues
* command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
*/
@ -2091,7 +1999,6 @@ struct ice_aqc_add_txqs_perq {
struct ice_aqc_txsched_elem info;
};
/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
* is an array of the following structs. Please note that the length of
* each struct ice_aqc_add_tx_qgrp is variable due
@ -2104,7 +2011,6 @@ struct ice_aqc_add_tx_qgrp {
struct ice_aqc_add_txqs_perq txqs[1];
};
/* Disable Tx LAN Queues (indirect 0x0C31) */
struct ice_aqc_dis_txqs {
u8 cmd_type;
@ -2127,7 +2033,6 @@ struct ice_aqc_dis_txqs {
__le32 addr_low;
};
/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
* contains the following structures, arrayed one after the
* other.
@ -2150,12 +2055,10 @@ struct ice_aqc_dis_txq_item {
(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
};
struct ice_aqc_dis_txq {
struct ice_aqc_dis_txq_item qgrps[1];
};
/* Tx LAN Queues Cleanup Event (0x0C31) */
struct ice_aqc_txqs_cleanup {
__le16 caller_opc;
@ -2163,7 +2066,6 @@ struct ice_aqc_txqs_cleanup {
u8 reserved[12];
};
/* Move / Reconfigure Tx Queues (indirect 0x0C32) */
struct ice_aqc_move_txqs {
u8 cmd_type;
@ -2184,7 +2086,6 @@ struct ice_aqc_move_txqs {
__le32 addr_low;
};
/* This is the descriptor of each queue entry for the move Tx LAN Queues
* command (0x0C32).
*/
@ -2195,15 +2096,12 @@ struct ice_aqc_move_txqs_elem {
__le32 q_teid;
};
struct ice_aqc_move_txqs_data {
__le32 src_teid;
__le32 dest_teid;
struct ice_aqc_move_txqs_elem txqs[1];
};
/* Download Package (indirect 0x0C40) */
/* Also used for Update Package (indirect 0x0C42) */
struct ice_aqc_download_pkg {
@ -2255,9 +2153,6 @@ struct ice_aqc_get_pkg_info_resp {
struct ice_aqc_get_pkg_info pkg_info[1];
};
/* Lan Queue Overflow Event (direct, 0x1001) */
struct ice_aqc_event_lan_overflow {
__le32 prtdcb_ruptq;
@ -2265,9 +2160,6 @@ struct ice_aqc_event_lan_overflow {
u8 reserved[8];
};
/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor
* @flags: ICE_AQ_FLAG_* flags
@ -2361,7 +2253,6 @@ struct ice_aq_desc {
} params;
};
/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
#define ICE_AQ_LG_BUF 512
@ -2572,8 +2463,6 @@ enum ice_adminq_opc {
ice_aqc_opc_update_pkg = 0x0C42,
ice_aqc_opc_get_pkg_info_list = 0x0C43,
/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow = 0x1001,
};

2
drivers/net/ice/base/ice_bitops.h
View File

@ -8,7 +8,6 @@
/* Define the size of the bitmap chunk */
typedef u32 ice_bitmap_t;
/* Number of bits per bitmap chunk */
#define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t))
/* Determine which chunk a bit belongs in */
@ -372,5 +371,4 @@ ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size)
return true;
}
#endif /* _ICE_BITOPS_H_ */

25
drivers/net/ice/base/ice_common.c
View File

@ -11,7 +11,6 @@
#define ICE_PF_RESET_WAIT_COUNT 200
/**
* ice_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
@ -41,7 +40,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
return status;
}
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
@ -113,7 +111,6 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
ETH_ALEN, ICE_DMA_TO_NONDMA);
break;
}
return ICE_SUCCESS;
}
@ -533,7 +530,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
ice_free(hw, sw);
}
/**
* ice_get_itr_intrl_gran
* @hw: pointer to the HW struct
@ -598,7 +594,6 @@ void ice_print_rollback_msg(struct ice_hw *hw)
&ver_lo);
SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
ice_warn(hw,
"Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
@ -617,7 +612,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
/* Set MAC type based on DeviceID */
status = ice_set_mac_type(hw);
if (status)
@ -627,14 +621,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
PF_FUNC_RID_FUNCTION_NUMBER_M) >>
PF_FUNC_RID_FUNCTION_NUMBER_S;
status = ice_reset(hw, ICE_RESET_PFR);
if (status)
return status;
ice_get_itr_intrl_gran(hw);
status = ice_create_all_ctrlq(hw);
if (status)
goto err_unroll_cqinit;
@ -686,7 +678,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
goto err_unroll_alloc;
}
/* Initialize port_info struct with scheduler data */
status = ice_sched_init_port(hw->port_info);
if (status)
@ -725,7 +716,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_sched;
/* Get MAC information */
/* A single port can report up to two (LAN and WoL) addresses */
mac_buf = ice_calloc(hw, 2,
@ -926,7 +916,6 @@ enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
wr32(hw, GLGEN_RTRIG, val);
ice_flush(hw);
/* wait for the FW to be ready */
return ice_check_reset(hw);
}
@ -997,8 +986,6 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
return ICE_ERR_DOES_NOT_EXIST;
}
/**
* ice_copy_rxq_ctx_to_hw
* @hw: pointer to the hardware structure
@ -1321,7 +1308,6 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
}
#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
/* FW Admin Queue command wrappers */
/**
@ -2142,7 +2128,6 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
cmd->flags = flags;
/* Prep values for flags, sah, sal */
cmd->sah = HTONS(*((const u16 *)mac_addr));
cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
@ -2179,7 +2164,6 @@ void ice_clear_pxe_mode(struct ice_hw *hw)
ice_aq_clear_pxe_mode(hw);
}
/**
* ice_get_link_speed_based_on_phy_type - returns link speed
* @phy_type_low: lower part of phy_type
@ -2848,7 +2832,6 @@ ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/**
* ice_aq_set_port_id_led
* @pi: pointer to the port information
@ -2869,7 +2852,6 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
if (is_orig_mode)
cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
else
@ -3357,7 +3339,6 @@ ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
return status;
}
/* End of FW Admin Queue command wrappers */
/**
@ -3581,9 +3562,6 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
return ICE_SUCCESS;
}
/**
* ice_read_byte - read context byte into struct
* @src_ctx: the context structure to read from
@ -4047,8 +4025,6 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
ICE_SCHED_NODE_OWNER_LAN);
}
/**
* ice_replay_pre_init - replay pre initialization
* @hw: pointer to the HW struct
@ -4246,7 +4222,6 @@ ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
cur_stats->rx_errors += error_cnt;
}
/**
* ice_sched_query_elem - query element information from HW
* @hw: pointer to the HW struct

2
drivers/net/ice/base/ice_common.h
View File

@ -169,7 +169,6 @@ ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
enum ice_status
ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
enum ice_status
ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
struct ice_sq_cd *cd);
@ -178,7 +177,6 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
bool write, struct ice_sq_cd *cd);
enum ice_status
ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
enum ice_status

9
drivers/net/ice/base/ice_controlq.c
View File

@ -4,7 +4,6 @@
#include "ice_common.h"
#define ICE_CQ_INIT_REGS(qinfo, prefix) \
do { \
(qinfo)->sq.head = prefix##_ATQH; \
@ -53,7 +52,6 @@ static void ice_mailbox_init_regs(struct ice_hw *hw)
ICE_CQ_INIT_REGS(cq, PF_MBX);
}
/**
* ice_check_sq_alive
* @hw: pointer to the HW struct
@ -521,7 +519,6 @@ shutdown_rq_out:
return ret_code;
}
/**
* ice_init_check_adminq - Check version for Admin Queue to know if its alive
* @hw: pointer to the hardware structure
@ -533,12 +530,10 @@ static enum ice_status ice_init_check_adminq(struct ice_hw *hw)
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
status = ice_aq_get_fw_ver(hw, NULL);
if (status)
goto init_ctrlq_free_rq;
if (!ice_aq_ver_check(hw)) {
status = ICE_ERR_FW_API_VER;
goto init_ctrlq_free_rq;
@ -633,7 +628,6 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
/* Init FW admin queue */
ret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);
if (ret_code)
@ -972,7 +966,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
(cq->sq.next_to_use)++;
if (cq->sq.next_to_use == cq->sq.count)
cq->sq.next_to_use = 0;
@ -1025,7 +1018,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
ice_debug_cq(hw, (void *)desc, buf, buf_size);
/* save writeback AQ if requested */
if (details->wb_desc)
ice_memcpy(details->wb_desc, desc_on_ring,
@ -1158,7 +1150,6 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
ice_debug_cq(hw, (void *)desc, e->msg_buf,
cq->rq_buf_size);
/* Restore the original datalen and buffer address in the desc,
* FW updates datalen to indicate the event message size
*/

1
drivers/net/ice/base/ice_controlq.h
View File

@ -7,7 +7,6 @@
#include "ice_adminq_cmd.h"
/* Maximum buffer lengths for all control queue types */
#define ICE_AQ_MAX_BUF_LEN 4096
#define ICE_MBXQ_MAX_BUF_LEN 4096

1
drivers/net/ice/base/ice_devids.h
View File

@ -5,7 +5,6 @@
#ifndef _ICE_DEVIDS_H_
#define _ICE_DEVIDS_H_
/* Device IDs */
/* Intel(R) Ethernet Controller E810-C for backplane */
#define ICE_DEV_ID_E810C_BACKPLANE 0x1591

5
drivers/net/ice/base/ice_flex_pipe.c
View File

@ -808,7 +808,6 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,
return status;
}
/**
* ice_aq_update_pkg
* @hw: pointer to the hardware structure
@ -1180,7 +1179,6 @@ init_pkg_free_alloc:
return status;
}
/**
* ice_verify_pkg - verify package
* @pkg: pointer to the package buffer
@ -2084,7 +2082,6 @@ ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,
/* PTG Management */
/**
* ice_ptg_find_ptype - Search for packet type group using packet type (ptype)
* @hw: pointer to the hardware structure
@ -2121,7 +2118,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg)
hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;
}
/**
* ice_ptg_remove_ptype - Removes ptype from a particular packet type group
* @hw: pointer to the hardware structure
@ -2315,7 +2311,6 @@ ice_match_prop_lst(struct LIST_HEAD_TYPE *list1, struct LIST_HEAD_TYPE *list2)
/* VSIG Management */
/**
* ice_vsig_find_vsi - find a VSIG that contains a specified VSI
* @hw: pointer to the hardware structure

1
drivers/net/ice/base/ice_flex_pipe.h
View File

@ -46,7 +46,6 @@ bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index);
bool
ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type);
/* XLT2/VSI group functions */
enum ice_status
ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);

2
drivers/net/ice/base/ice_hw_autogen.h
View File

@ -6,8 +6,6 @@
#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_
#define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
#define GL_RDPU_CNTRL_RX_PAD_EN_S 0
#define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)

9
drivers/net/ice/base/ice_lan_tx_rx.h
View File

@ -173,7 +173,6 @@ struct ice_fltr_desc {
(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
#define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL
enum ice_rx_desc_status_bits {
/* Note: These are predefined bit offsets */
ICE_RX_DESC_STATUS_DD_S = 0,
@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits {
#define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S
#define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
enum ice_rx_desc_fltstat_values {
ICE_RX_DESC_FLTSTAT_NO_DATA = 0,
ICE_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values {
ICE_RX_DESC_FLTSTAT_RSS_HASH = 3,
};
#define ICE_RXD_QW1_ERROR_S 19
#define ICE_RXD_QW1_ERROR_M (0xFFUL << ICE_RXD_QW1_ERROR_S)
@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer {
ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
};
#define ICE_RXD_QW1_LEN_PBUF_S 38
#define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)
@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer {
#define ICE_RXD_QW1_LEN_SPH_S 63
#define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
enum ice_rx_desc_ext_status_bits {
/* Note: These are predefined bit offsets */
ICE_RX_DESC_EXT_STATUS_L2TAG2P_S = 0,
@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits {
ICE_RX_DESC_EXT_STATUS_PELONGB_S = 11,
};
enum ice_rx_desc_pe_status_bits {
/* Note: These are predefined bit offsets */
ICE_RX_DESC_PE_STATUS_QPID_S = 0, /* 18 BITS */
@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits {
#define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M \
(0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)
#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S 19
#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M \
(0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)
@ -840,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits {
ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
};
#define ICE_RXQ_CTX_SIZE_DWORDS 8
#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
@ -1056,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload {
#define ICE_TXD_CTX_QW0_L4T_CS_S 23
#define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
#define ICE_LAN_TXQ_MAX_QGRPS 127
#define ICE_LAN_TXQ_MAX_QDIS 1023

4
drivers/net/ice/base/ice_nvm.c
View File

@ -4,7 +4,6 @@
#include "ice_common.h"
/**
* ice_aq_read_nvm
* @hw: pointer to the HW struct
@ -138,7 +137,6 @@ ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
return status;
}
/**
* ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
* @hw: pointer to the HW structure
@ -354,7 +352,6 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return ICE_SUCCESS;
}
/**
* ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
* @hw: pointer to the HW structure
@ -380,7 +377,6 @@ ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
return status;
}
/**
* ice_nvm_validate_checksum
* @hw: pointer to the HW struct

2
drivers/net/ice/base/ice_protocol_type.h
View File

@ -114,7 +114,6 @@ enum ice_prot_id {
#define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */
#define ICE_MAC_OFOS_HW 1
#define ICE_MAC_IL_HW 4
#define ICE_ETYPE_OL_HW 9
@ -148,7 +147,6 @@ struct ice_protocol_entry {
u8 protocol_id;
};
struct ice_ether_hdr {
u8 dst_addr[ETH_ALEN];
u8 src_addr[ETH_ALEN];

4
drivers/net/ice/base/ice_sched.c
View File

@ -4,7 +4,6 @@
#include "ice_sched.h"
/**
* ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB
* @pi: port information structure
@ -876,7 +875,6 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes,
return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
}
/**
* ice_sched_add_elems - add nodes to HW and SW DB
* @pi: port information structure
@ -1366,7 +1364,6 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)
goto sched_query_out;
}
sched_query_out:
ice_free(hw, buf);
return status;
@ -2021,7 +2018,6 @@ enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)
return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN);
}
/**
* ice_sched_is_tree_balanced - Check tree nodes are identical or not
* @hw: pointer to the HW struct

8
drivers/net/ice/base/ice_switch.c
View File

@ -6,7 +6,6 @@
#include "ice_flex_type.h"
#include "ice_flow.h"
#define ICE_ETH_DA_OFFSET 0
#define ICE_ETH_ETHTYPE_OFFSET 12
#define ICE_ETH_VLAN_TCI_OFFSET 14
@ -743,7 +742,6 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp *buf,
return status;
}
/**
* ice_alloc_sw - allocate resources specific to switch
* @hw: pointer to the HW struct
@ -1787,13 +1785,11 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)
}
} while (req_desc && !status);
out:
ice_free(hw, (void *)rbuf);
return status;
}
/**
* ice_fill_sw_info - Helper function to populate lb_en and lan_en
* @hw: pointer to the hardware structure
@ -3424,7 +3420,6 @@ ice_remove_eth_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list)
return ICE_SUCCESS;
}
/**
* ice_rem_sw_rule_info
* @hw: pointer to the hardware structure
@ -3823,7 +3818,6 @@ ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,
return status;
}
/**
* ice_determine_promisc_mask
* @fi: filter info to parse
@ -4811,8 +4805,6 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,
return ret_val;
}
/**
* ice_create_first_fit_recp_def - Create a recipe grouping
* @hw: pointer to the hardware structure

2
drivers/net/ice/base/ice_switch.h
View File

@ -15,7 +15,6 @@
#define ICE_FLTR_TX BIT(1)
#define ICE_FLTR_TX_RX (ICE_FLTR_RX | ICE_FLTR_TX)
/* Worst case buffer length for ice_aqc_opc_get_res_alloc */
#define ICE_MAX_RES_TYPES 0x80
#define ICE_AQ_GET_RES_ALLOC_BUF_LEN \
@ -391,7 +390,6 @@ enum ice_status
ice_add_mac_with_counter(struct ice_hw *hw, struct ice_fltr_info *f_info);
void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle);
/* Promisc/defport setup for VSIs */
enum ice_status
ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,

9
drivers/net/ice/base/ice_type.h
View File

@ -134,10 +134,6 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
#define __ALWAYS_UNUSED
#endif
#define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
(((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
@ -384,7 +380,6 @@ struct ice_hw_common_caps {
u8 proxy_support;
};
/* Function specific capabilities */
struct ice_hw_func_caps {
struct ice_hw_common_caps common_cap;
@ -401,7 +396,6 @@ struct ice_hw_dev_caps {
u32 num_funcs;
};
/* Information about MAC such as address, etc... */
struct ice_mac_info {
u8 lan_addr[ETH_ALEN];
@ -567,7 +561,6 @@ enum ice_rl_type {
#define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
#define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
/* The following tree example shows the naming conventions followed under
* ice_port_info struct for default scheduler tree topology.
*
@ -729,7 +722,6 @@ struct ice_switch_info {
struct ice_sw_recipe *recp_list;
};
/* Port hardware description */
struct ice_hw {
u8 *hw_addr;
@ -787,7 +779,6 @@ struct ice_hw {
u8 fw_patch; /* firmware patch version */
u32 fw_build; /* firmware build number */
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
* register. Used for determining the ITR/INTRL granularity during
* initialization.