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net/cxgbe: support to match on ingress physical port

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Add support to match packets based on ingress physical port.

Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
This commit is contained in:
Shagun Agrawal 2018-06-29 23:42:23 +05:30 committed by Ferruh Yigit
parent a4279771c6
commit 6b805d23a5
2 changed files with 45 additions and 1 deletions
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16
drivers/net/cxgbe/cxgbe_filter.c
View File

@ -65,11 +65,19 @@ int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
#define U(_mask, _field) \
(!(fconf & (_mask)) && S(_field))
if (U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto))
if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto))
return -EOPNOTSUPP;
#undef S
#undef U
/*
* Don't allow various trivially obvious bogus out-of-range
* values ...
*/
if (fs->val.iport >= adapter->params.nports)
return -ERANGE;
return 0;
}
@ -228,6 +236,9 @@ static u64 hash_filter_ntuple(const struct filter_entry *f)
u64 ntuple = 0;
u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
if (tp->port_shift >= 0)
ntuple |= (u64)f->fs.mask.iport << tp->port_shift;
if (tp->protocol_shift >= 0) {
if (!f->fs.val.proto)
ntuple |= (u64)tcp_proto << tp->protocol_shift;
@ -664,6 +675,9 @@ int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
));
fwr->maci_to_matchtypem =
cpu_to_be32(V_FW_FILTER_WR_PORT(f->fs.val.iport) |
V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
fwr->ptcl = f->fs.val.proto;
fwr->ptclm = f->fs.mask.proto;
rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));

30
drivers/net/cxgbe/cxgbe_flow.c
View File

@ -93,6 +93,8 @@ cxgbe_fill_filter_region(struct adapter *adap,
ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift;
if (tp->ethertype_shift >= 0)
ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift;
if (tp->port_shift >= 0)
ntuple_mask |= (u64)fs->mask.iport << tp->port_shift;
if (ntuple_mask != hash_filter_mask)
return;
@ -100,6 +102,27 @@ cxgbe_fill_filter_region(struct adapter *adap,
fs->cap = 1; /* use hash region */
}
static int
ch_rte_parsetype_port(const void *dmask, const struct rte_flow_item *item,
struct ch_filter_specification *fs,
struct rte_flow_error *e)
{
const struct rte_flow_item_phy_port *val = item->spec;
const struct rte_flow_item_phy_port *umask = item->mask;
const struct rte_flow_item_phy_port *mask;
mask = umask ? umask : (const struct rte_flow_item_phy_port *)dmask;
if (val->index > 0x7)
return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
item,
"port index upto 0x7 is supported");
CXGBE_FILL_FS(val->index, mask->index, iport);
return 0;
}
static int
ch_rte_parsetype_udp(const void *dmask, const struct rte_flow_item *item,
struct ch_filter_specification *fs,
@ -357,6 +380,13 @@ cxgbe_rtef_parse_actions(struct rte_flow *flow,
}
struct chrte_fparse parseitem[] = {
[RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
.fptr = ch_rte_parsetype_port,
.dmask = &(const struct rte_flow_item_phy_port){
.index = 0x7,
}
},
[RTE_FLOW_ITEM_TYPE_IPV4] = {
.fptr = ch_rte_parsetype_ipv4,
.dmask = &rte_flow_item_ipv4_mask,