event/octeontx: add mailbox support
ssovf VF device has mailbox mechanism to communicate with PF device. This patch adds support for a mbox API to send the mailbox request to PF device. The ssovf VF device will be used as the communication channel to talk to PF devices of all the network accelerated co-processors in Octeontx. Exposing as shared function to use it from pool, crypto, network devices. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
This commit is contained in:
Jerin Jacob
parent
a5d4742d15
commit
6da9d24574
@ -47,6 +47,7 @@ LIBABIVER := 1
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# all source are stored in SRCS-y
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#
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SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_probe.c
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SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_mbox.c
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# install this header file
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SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)-include := rte_pmd_octeontx_ssovf.h
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@ -46,8 +46,16 @@ enum octeontx_ssovf_type {
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OCTEONTX_SSO_HWS, /* SSO hardware workslot vf */
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};
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struct octeontx_mbox_hdr {
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uint16_t vfid; /* VF index or pf resource index local to the domain */
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uint8_t coproc; /* Coprocessor id */
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uint8_t msg; /* Message id */
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uint8_t res_code; /* Functional layer response code */
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};
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int octeontx_ssovf_info(struct octeontx_ssovf_info *info);
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void *octeontx_ssovf_bar(enum octeontx_ssovf_type, uint8_t id, uint8_t bar);
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int octeontx_ssovf_mbox_send(struct octeontx_mbox_hdr *hdr,
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void *txdata, uint16_t txlen, void *rxdata, uint16_t rxlen);
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#endif /* __RTE_PMD_OCTEONTX_SSOVF_H__ */
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@ -3,6 +3,7 @@ DPDK_17.05 {
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octeontx_ssovf_info;
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octeontx_ssovf_bar;
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octeontx_ssovf_mbox_send;
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local: *;
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};
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232
drivers/event/octeontx/ssovf_mbox.c
Normal file
232
drivers/event/octeontx/ssovf_mbox.c
Normal file
@ -0,0 +1,232 @@
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/*
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* BSD LICENSE
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*
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* Copyright (C) Cavium networks Ltd. 2017.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium networks nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <rte_atomic.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_io.h>
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#include <rte_spinlock.h>
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#include "ssovf_evdev.h"
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/* Mbox operation timeout in seconds */
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#define MBOX_WAIT_TIME_SEC 3
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#define MAX_RAM_MBOX_LEN ((SSOW_BAR4_LEN >> 1) - 8 /* Mbox header */)
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/* Mbox channel state */
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enum {
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MBOX_CHAN_STATE_REQ = 1,
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MBOX_CHAN_STATE_RES = 0,
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};
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/* Response messages */
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enum {
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MBOX_RET_SUCCESS,
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MBOX_RET_INVALID,
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MBOX_RET_INTERNAL_ERR,
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};
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struct mbox {
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int init_once;
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uint8_t *ram_mbox_base; /* Base address of mbox message stored in ram */
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uint8_t *reg; /* Store to this register triggers PF mbox interrupt */
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uint16_t tag_own; /* Last tag which was written to own channel */
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rte_spinlock_t lock;
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};
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static struct mbox octeontx_mbox;
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/*
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* Structure used for mbox synchronization
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* This structure sits at the begin of Mbox RAM and used as main
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* synchronization point for channel communication
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*/
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struct mbox_ram_hdr {
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union {
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uint64_t u64;
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struct {
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uint8_t chan_state : 1;
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uint8_t coproc : 7;
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uint8_t msg;
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uint8_t vfid;
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uint8_t res_code;
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uint16_t tag;
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uint16_t len;
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};
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};
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};
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static inline void
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mbox_send_request(struct mbox *m, struct octeontx_mbox_hdr *hdr,
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const void *txmsg, uint16_t txsize)
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{
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struct mbox_ram_hdr old_hdr;
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struct mbox_ram_hdr new_hdr = {.u64 = 0};
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uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
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uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
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/*
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* Initialize the channel with the tag left by last send.
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* On success full mbox send complete, PF increments the tag by one.
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* The sender can validate integrity of PF message with this scheme
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*/
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old_hdr.u64 = rte_read64(ram_mbox_hdr);
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m->tag_own = (old_hdr.tag + 2) & (~0x1ul); /* next even number */
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/* Copy msg body */
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if (txmsg)
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memcpy(ram_mbox_msg, txmsg, txsize);
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/* Prepare new hdr */
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new_hdr.chan_state = MBOX_CHAN_STATE_REQ;
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new_hdr.coproc = hdr->coproc;
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new_hdr.msg = hdr->msg;
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new_hdr.vfid = hdr->vfid;
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new_hdr.tag = m->tag_own;
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new_hdr.len = txsize;
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/* Write the msg header */
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rte_write64(new_hdr.u64, ram_mbox_hdr);
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rte_io_wmb();
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/* Notify PF about the new msg - write to MBOX reg generates PF IRQ */
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rte_write64(0, m->reg);
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}
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static inline int
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mbox_wait_response(struct mbox *m, struct octeontx_mbox_hdr *hdr,
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void *rxmsg, uint16_t rxsize)
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{
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int res = 0, wait;
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uint16_t len;
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struct mbox_ram_hdr rx_hdr;
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uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
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uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
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/* Wait for response */
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wait = MBOX_WAIT_TIME_SEC * 1000 * 10;
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while (wait > 0) {
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rte_delay_us(100);
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rx_hdr.u64 = rte_read64(ram_mbox_hdr);
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if (rx_hdr.chan_state == MBOX_CHAN_STATE_RES)
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break;
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--wait;
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}
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hdr->res_code = rx_hdr.res_code;
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m->tag_own++;
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/* Timeout */
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if (wait <= 0) {
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res = -ETIMEDOUT;
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goto error;
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}
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/* Tag mismatch */
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if (m->tag_own != rx_hdr.tag) {
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res = -EINVAL;
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goto error;
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}
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/* PF nacked the msg */
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if (rx_hdr.res_code != MBOX_RET_SUCCESS) {
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res = -EBADMSG;
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goto error;
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}
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len = RTE_MIN(rx_hdr.len, rxsize);
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if (rxmsg)
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memcpy(rxmsg, ram_mbox_msg, len);
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return len;
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error:
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ssovf_log_err("Failed to send mbox(%d/%d) coproc=%d msg=%d ret=(%d,%d)",
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m->tag_own, rx_hdr.tag, hdr->msg, hdr->coproc, res,
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hdr->res_code);
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return res;
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}
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static inline int
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mbox_send(struct mbox *m, struct octeontx_mbox_hdr *hdr, const void *txmsg,
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uint16_t txsize, void *rxmsg, uint16_t rxsize)
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{
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int res = -EINVAL;
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if (m->init_once == 0 || hdr == NULL ||
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txsize > MAX_RAM_MBOX_LEN || rxsize > MAX_RAM_MBOX_LEN) {
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ssovf_log_err("Invalid init_once=%d hdr=%p txsz=%d rxsz=%d",
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m->init_once, hdr, txsize, rxsize);
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return res;
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}
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rte_spinlock_lock(&m->lock);
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mbox_send_request(m, hdr, txmsg, txsize);
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res = mbox_wait_response(m, hdr, rxmsg, rxsize);
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rte_spinlock_unlock(&m->lock);
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return res;
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}
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static inline int
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mbox_setup(struct mbox *m)
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{
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if (unlikely(m->init_once == 0)) {
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rte_spinlock_init(&m->lock);
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m->ram_mbox_base = octeontx_ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
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m->reg = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
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m->reg += SSO_VHGRP_PF_MBOX(1);
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if (m->ram_mbox_base == NULL || m->reg == NULL) {
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ssovf_log_err("Invalid ram_mbox_base=%p or reg=%p",
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m->ram_mbox_base, m->reg);
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return -EINVAL;
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}
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m->init_once = 1;
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}
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return 0;
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}
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int
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octeontx_ssovf_mbox_send(struct octeontx_mbox_hdr *hdr, void *txdata,
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uint16_t txlen, void *rxdata, uint16_t rxlen)
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{
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struct mbox *m = &octeontx_mbox;
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RTE_BUILD_BUG_ON(sizeof(struct mbox_ram_hdr) != 8);
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if (rte_eal_process_type() != RTE_PROC_PRIMARY || mbox_setup(m))
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return -EINVAL;
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return mbox_send(m, hdr, txdata, txlen, rxdata, rxlen);
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}
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