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config: clean cache line size selection scheme

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by default, all the targets will be configured with the 64-byte cache line
size, targets which have different cache line size can be overridden
through target specific config file.

Selected ThunderX and power8 as CONFIG_RTE_CACHE_LINE_SIZE=128 targets
based on existing configuration.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
This commit is contained in:
Jerin Jacob 2015-12-07 19:52:50 +05:30 committed by Thomas Monjalon
parent 94e4b3a607
commit 6e757e6942
11 changed files with 17 additions and 15 deletions
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5
config/common_bsdapp
View File

@ -83,6 +83,11 @@ CONFIG_RTE_BUILD_COMBINE_LIBS=n
#
CONFIG_RTE_NEXT_ABI=y
#
# Machine's cache line size
#
CONFIG_RTE_CACHE_LINE_SIZE=64
#
# Compile Environment Abstraction Layer
#

6
config/common_linuxapp
View File

@ -83,6 +83,11 @@ CONFIG_RTE_BUILD_COMBINE_LIBS=n
#
CONFIG_RTE_NEXT_ABI=y
#
# Machine's cache line size
#
CONFIG_RTE_CACHE_LINE_SIZE=64
#
# Compile Environment Abstraction Layer
#
@ -100,7 +105,6 @@ CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n
CONFIG_RTE_EAL_IGB_UIO=y
CONFIG_RTE_EAL_VFIO=y
CONFIG_RTE_MALLOC_DEBUG=n
# Default driver path (or "" to disable)
CONFIG_RTE_EAL_PMD_PATH=""

2
config/defconfig_arm64-armv8a-linuxapp-gcc
View File

@ -43,8 +43,6 @@ CONFIG_RTE_FORCE_INTRINSICS=y
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y
CONFIG_RTE_CACHE_LINE_SIZE=64
CONFIG_RTE_IXGBE_INC_VECTOR=n
CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
CONFIG_RTE_LIBRTE_IVSHMEM=n

2
config/defconfig_ppc_64-power8-linuxapp-gcc
View File

@ -36,6 +36,8 @@ CONFIG_RTE_ARCH="ppc_64"
CONFIG_RTE_ARCH_PPC_64=y
CONFIG_RTE_ARCH_64=y
CONFIG_RTE_CACHE_LINE_SIZE=128
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y

3
lib/librte_eal/common/include/rte_memory.h
View File

@ -68,9 +68,6 @@ enum rte_page_sizes {
};
#define SOCKET_ID_ANY -1 /**< Any NUMA socket. */
#ifndef RTE_CACHE_LINE_SIZE
#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */
#endif
#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */
#define RTE_CACHE_LINE_ROUNDUP(size) \

4
lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h
View File

@ -68,10 +68,6 @@
*/
#define RTE_KNI_NAMESIZE 32
#ifndef RTE_CACHE_LINE_SIZE
#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */
#endif
/*
* Request id.
*/

2
mk/arch/arm/rte.vars.mk
View File

@ -32,7 +32,7 @@
ARCH ?= arm
CROSS ?=
CPU_CFLAGS ?= -marm -DRTE_CACHE_LINE_SIZE=64 -munaligned-access
CPU_CFLAGS ?= -marm -munaligned-access
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf

2
mk/arch/ppc_64/rte.vars.mk
View File

@ -32,7 +32,7 @@
ARCH ?= powerpc
CROSS ?=
CPU_CFLAGS ?= -m64 -DRTE_CACHE_LINE_SIZE=128
CPU_CFLAGS ?= -m64
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf64

2
mk/machine/armv8a/rte.vars.mk
View File

@ -55,4 +55,4 @@
# CPU_LDFLAGS =
# CPU_ASFLAGS =
MACHINE_CFLAGS += -march=armv8-a+crc -DRTE_CACHE_LINE_SIZE=64
MACHINE_CFLAGS += -march=armv8-a+crc

2
mk/machine/thunderx/rte.vars.mk
View File

@ -55,4 +55,4 @@ CROSS ?= aarch64-thunderx-linux-gnu-
# CPU_LDFLAGS =
# CPU_ASFLAGS =
MACHINE_CFLAGS += -march=armv8-a+crc -mcpu=thunderx -DRTE_CACHE_LINE_SIZE=128
MACHINE_CFLAGS += -march=armv8-a+crc -mcpu=thunderx

2
mk/machine/xgene1/rte.vars.mk
View File

@ -55,4 +55,4 @@
# CPU_LDFLAGS =
# CPU_ASFLAGS =
MACHINE_CFLAGS += -march=armv8-a -DRTE_CACHE_LINE_SIZE=64
MACHINE_CFLAGS += -march=armv8-a