e1000/base: fix K1 configuration
This patch is for the following updates to the K1 configurations: Tx idle period for entering K1 should be 128 ns. Minimum Tx idle period in K1 should be 256 ns. Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
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@ -1503,10 +1503,14 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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}
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/* Clear link partner's EEE ability */
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hw->dev_spec.ich8lan.eee_lp_ability = 0;
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/* Configure K0s minimum time */
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if (hw->mac.type == e1000_pch_lpt) {
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e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
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}
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if (!link)
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return E1000_SUCCESS; /* No link detected */
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@ -5309,3 +5313,44 @@ STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
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}
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}
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/**
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* e1000_configure_k0s_lpt - Configure K0s power state
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* @hw: pointer to the HW structure
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* @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
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* 0 corresponds to 128ns, each value over 0 doubles the duration.
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* @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
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* 0 corresponds to 128ns, each value over 0 doubles the duration.
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*
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* Configure the K1 power state based on the provided parameter.
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* Assumes semaphore already acquired.
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*
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* Success returns 0, Failure returns:
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* -E1000_ERR_PHY (-2) in case of access error
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* -E1000_ERR_PARAM (-4) in case of parameters error
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**/
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s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
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{
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s32 ret_val;
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u16 kmrn_reg = 0;
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DEBUGFUNC("e1000_configure_k0s_lpt");
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if (entry_latency > 3 || min_time > 4)
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return -E1000_ERR_PARAM;
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ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
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&kmrn_reg);
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if (ret_val)
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return ret_val;
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/* for now don't touch the latency */
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kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
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kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
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ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
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kmrn_reg);
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if (ret_val)
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return ret_val;
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return E1000_SUCCESS;
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}
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@ -114,7 +114,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
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#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
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#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
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#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
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#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
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#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
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@ -179,6 +179,8 @@ POSSIBILITY OF SUCH DAMAGE.
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#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
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#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
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#define K1_ENTRY_LATENCY 0
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#define K1_MIN_TIME 1
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/* SMBus Control Phy Register */
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#define CV_SMB_CTRL PHY_REG(769, 23)
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@ -301,6 +303,7 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
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void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
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u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
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s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
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s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
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void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
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s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
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s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
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@ -274,6 +274,13 @@ bool e1000_is_mphy_ready(struct e1000_hw *hw);
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#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
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#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
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#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
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#define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
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#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
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#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
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#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
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(3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
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#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
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(7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
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#define E1000_KMRNCTRLSTA_OP_MODES 0x1F /* Kumeran Modes of Operation */
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#define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC 0x0002 /* change LSC to CSC */
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@ -66,6 +66,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
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#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
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#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
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#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
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#define E1000_FCT 0x00030 /* Flow Control Type - RW */
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#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
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#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
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