bus/fslmc: adding cpu support in stashing config

Stashing can also be configured by other drivers (for instance
event driver) passing cpu_id as an argument. This change
facilitates the same.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
This commit is contained in:
Nipun Gupta 2017-06-30 14:24:24 +05:30 committed by Jerin Jacob
parent 15be42b688
commit 71e50d4069
3 changed files with 12 additions and 8 deletions

View File

@ -172,10 +172,9 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
}
static int
dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
{
int sdest;
int cpu_id, ret;
int sdest, ret;
static int first_time;
/* find the SoC type for the first time */
@ -194,7 +193,6 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
}
/* Set the Stashing Destination */
cpu_id = rte_lcore_id();
if (cpu_id < 0) {
cpu_id = rte_get_master_lcore();
if (cpu_id < 0) {
@ -220,7 +218,7 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
return 0;
}
static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
{
struct dpaa2_dpio_dev *dpio_dev = NULL;
int ret;
@ -236,7 +234,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
dpio_dev, dpio_dev->index, syscall(SYS_gettid));
ret = dpaa2_configure_stashing(dpio_dev);
ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
if (ret)
PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
@ -276,7 +274,7 @@ dpaa2_affine_qbman_swp(void)
}
/* Populate the dpaa2_io_portal structure */
dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();
dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
if (dpaa2_io_portal[lcore_id].dpio_dev) {
RTE_PER_LCORE(_dpaa2_io).dpio_dev
@ -322,7 +320,7 @@ dpaa2_affine_qbman_swp_sec(void)
}
/* Populate the dpaa2_io_portal structure */
dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp();
dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev

View File

@ -53,6 +53,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal
extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id);
/* Affine a DPIO portal to current processing thread */
int dpaa2_affine_qbman_swp(void);

View File

@ -53,6 +53,8 @@ DPDK_17.05 {
DPDK_17.08 {
global:
dpaa2_io_portal;
dpaa2_get_qbman_swp;
dpci_set_rx_queue;
dpcon_open;
dpcon_get_attributes;