bus/fslmc: adding cpu support in stashing config
Stashing can also be configured by other drivers (for instance event driver) passing cpu_id as an argument. This change facilitates the same. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
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15be42b688
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@ -172,10 +172,9 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
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}
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static int
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dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
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dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
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{
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int sdest;
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int cpu_id, ret;
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int sdest, ret;
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static int first_time;
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/* find the SoC type for the first time */
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@ -194,7 +193,6 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
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}
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/* Set the Stashing Destination */
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cpu_id = rte_lcore_id();
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if (cpu_id < 0) {
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cpu_id = rte_get_master_lcore();
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if (cpu_id < 0) {
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@ -220,7 +218,7 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
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return 0;
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}
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static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
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struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
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{
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struct dpaa2_dpio_dev *dpio_dev = NULL;
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int ret;
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@ -236,7 +234,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
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PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
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dpio_dev, dpio_dev->index, syscall(SYS_gettid));
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ret = dpaa2_configure_stashing(dpio_dev);
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ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
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if (ret)
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PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
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@ -276,7 +274,7 @@ dpaa2_affine_qbman_swp(void)
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}
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/* Populate the dpaa2_io_portal structure */
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dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();
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dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
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if (dpaa2_io_portal[lcore_id].dpio_dev) {
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RTE_PER_LCORE(_dpaa2_io).dpio_dev
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@ -322,7 +320,7 @@ dpaa2_affine_qbman_swp_sec(void)
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}
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/* Populate the dpaa2_io_portal structure */
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dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp();
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dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
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if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
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RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
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@ -53,6 +53,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
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#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
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#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal
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extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
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struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id);
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/* Affine a DPIO portal to current processing thread */
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int dpaa2_affine_qbman_swp(void);
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@ -53,6 +53,8 @@ DPDK_17.05 {
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DPDK_17.08 {
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global:
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dpaa2_io_portal;
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dpaa2_get_qbman_swp;
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dpci_set_rx_queue;
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dpcon_open;
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dpcon_get_attributes;
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