ethdev: add support for device offload capabilities
1) Make device RX and TX offload capabilities to be returned in the rte_eth_dev_info data structure by the function rte_eth_dev_info_get The following initial set of RX offload capabilities are defined: - VLAN header stripping - IPv4 header checksum check - UDP checksum check - TCP checksum check - TCP large receive offload (LRO) The following initial set of TX offload capabilities are defined: - VLAN header insertion - IPv4 header checksum computation - UDP checksum computation - TCP checksum computation - SCTP checksum computation - TCP segmentation offload (Transmit Segmentation Offload) - UDP segmentation offload 2) Update the eth_dev_infos_get() function of the igb and ixgbe PMDs to return the offload capabilities which are supported by the device and that are effectively managed by the driver. Signed-off-by: Ivan Boule <ivan.boule@6wind.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
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@ -1034,6 +1034,9 @@ rte_eth_dev_info_get(uint8_t port_id, struct rte_eth_dev_info *dev_info)
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}
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}
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dev = &rte_eth_devices[port_id];
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dev = &rte_eth_devices[port_id];
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/* Default device offload capabilities to zero */
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dev_info->rx_offload_capa = 0;
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dev_info->tx_offload_capa = 0;
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FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get);
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FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get);
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(*dev->dev_ops->dev_infos_get)(dev, dev_info);
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(*dev->dev_ops->dev_infos_get)(dev, dev_info);
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dev_info->pci_dev = dev->pci_dev;
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dev_info->pci_dev = dev->pci_dev;
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@ -759,6 +759,27 @@ struct rte_eth_conf {
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* an Ethernet device, such as the controlling driver of the device,
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* an Ethernet device, such as the controlling driver of the device,
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* its PCI context, etc...
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* its PCI context, etc...
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*/
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*/
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/**
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* RX offload capabilities of a device.
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*/
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#define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001
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#define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002
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#define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004
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#define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008
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#define DEV_RX_OFFLOAD_TCP_LRO 0x00000010
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/**
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* TX offload capabilities of a device.
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*/
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#define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001
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#define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002
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#define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004
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#define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008
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#define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010
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#define DEV_TX_OFFLOAD_TCP_TSO 0x00000020
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#define DEV_TX_OFFLOAD_UDP_TSO 0x00000040
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struct rte_eth_dev_info {
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struct rte_eth_dev_info {
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struct rte_pci_device *pci_dev; /**< Device PCI information. */
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struct rte_pci_device *pci_dev; /**< Device PCI information. */
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const char *driver_name; /**< Device Driver name. */
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const char *driver_name; /**< Device Driver name. */
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@ -771,6 +792,8 @@ struct rte_eth_dev_info {
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/** Maximum number of hash MAC addresses for MTA and UTA. */
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/** Maximum number of hash MAC addresses for MTA and UTA. */
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uint16_t max_vfs; /**< Maximum number of VFs. */
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uint16_t max_vfs; /**< Maximum number of VFs. */
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uint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */
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uint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */
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uint32_t rx_offload_capa; /**< Device RX offload capabilities. */
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uint32_t tx_offload_capa; /**< Device TX offload capabilities. */
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};
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};
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struct rte_eth_dev;
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struct rte_eth_dev;
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@ -1125,6 +1125,17 @@ eth_igb_infos_get(struct rte_eth_dev *dev,
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dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
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dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
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dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
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dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
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dev_info->max_mac_addrs = hw->mac.rar_entry_count;
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dev_info->max_mac_addrs = hw->mac.rar_entry_count;
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dev_info->rx_offload_capa =
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DEV_RX_OFFLOAD_VLAN_STRIP |
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DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM |
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DEV_RX_OFFLOAD_TCP_CKSUM;
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dev_info->tx_offload_capa =
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DEV_TX_OFFLOAD_VLAN_INSERT |
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DEV_TX_OFFLOAD_IPV4_CKSUM |
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DEV_TX_OFFLOAD_UDP_CKSUM |
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DEV_TX_OFFLOAD_TCP_CKSUM |
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DEV_TX_OFFLOAD_SCTP_CKSUM;
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switch (hw->mac.type) {
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switch (hw->mac.type) {
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case e1000_82575:
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case e1000_82575:
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@ -1699,6 +1699,17 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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dev_info->max_vmdq_pools = ETH_16_POOLS;
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dev_info->max_vmdq_pools = ETH_16_POOLS;
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else
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else
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dev_info->max_vmdq_pools = ETH_64_POOLS;
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dev_info->max_vmdq_pools = ETH_64_POOLS;
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dev_info->rx_offload_capa =
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DEV_RX_OFFLOAD_VLAN_STRIP |
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DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM |
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DEV_RX_OFFLOAD_TCP_CKSUM;
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dev_info->tx_offload_capa =
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DEV_TX_OFFLOAD_VLAN_INSERT |
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DEV_TX_OFFLOAD_IPV4_CKSUM |
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DEV_TX_OFFLOAD_UDP_CKSUM |
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DEV_TX_OFFLOAD_TCP_CKSUM |
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DEV_TX_OFFLOAD_SCTP_CKSUM;
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}
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}
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/* return 0 means link status changed, -1 means not changed */
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/* return 0 means link status changed, -1 means not changed */
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