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net/bnxt: add VLAN tag count in computed field list

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Added number of vlan tags in the computed field list so conditional
table execution could be done based on number of vlan tags in the
flow create.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2020-07-06 13:54:54 +05:30 committed by Ferruh Yigit
parent 272a652be0
commit 72ee725b27
2 changed files with 43 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
View File

@ -88,6 +88,10 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_FLOW_DIR_BITMASK_EGR);
/* Set the computed flags for no vlan tags before parsing */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 1);
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
/* get the header information from the flow_hdr_info table */
@ -480,6 +484,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
outer_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 0);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
@ -490,6 +496,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_TWO_VTAGS, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OI_VLAN);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
@ -499,6 +506,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
inner_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 0);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
@ -509,6 +518,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_TWO_VTAGS, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_II_VLAN);
} else {

60
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
View File

@ -96,33 +96,39 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_NOT_USED = 0,
BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1,
BNXT_ULP_CF_IDX_O_VTAG_NUM = 2,
BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
BNXT_ULP_CF_IDX_I_TWO_VTAGS = 5,
BNXT_ULP_CF_IDX_INCOMING_IF = 6,
BNXT_ULP_CF_IDX_DIRECTION = 7,
BNXT_ULP_CF_IDX_SVIF_FLAG = 8,
BNXT_ULP_CF_IDX_O_L3 = 9,
BNXT_ULP_CF_IDX_I_L3 = 10,
BNXT_ULP_CF_IDX_O_L4 = 11,
BNXT_ULP_CF_IDX_I_L4 = 12,
BNXT_ULP_CF_IDX_DEV_PORT_ID = 13,
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 14,
BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 15,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 16,
BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 17,
BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 18,
BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 19,
BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 20,
BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 21,
BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 22,
BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 23,
BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 24,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 25,
BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 26,
BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 27,
BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 28,
BNXT_ULP_CF_IDX_LAST = 29
BNXT_ULP_CF_IDX_O_NO_VTAG = 3,
BNXT_ULP_CF_IDX_O_ONE_VTAG = 4,
BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5,
BNXT_ULP_CF_IDX_I_VTAG_NUM = 6,
BNXT_ULP_CF_IDX_I_NO_VTAG = 7,
BNXT_ULP_CF_IDX_I_ONE_VTAG = 8,
BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9,
BNXT_ULP_CF_IDX_INCOMING_IF = 10,
BNXT_ULP_CF_IDX_DIRECTION = 11,
BNXT_ULP_CF_IDX_SVIF_FLAG = 12,
BNXT_ULP_CF_IDX_O_L3 = 13,
BNXT_ULP_CF_IDX_I_L3 = 14,
BNXT_ULP_CF_IDX_O_L4 = 15,
BNXT_ULP_CF_IDX_I_L4 = 16,
BNXT_ULP_CF_IDX_DEV_PORT_ID = 17,
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 18,
BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 19,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 20,
BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 21,
BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 22,
BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 23,
BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 24,
BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 25,
BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 26,
BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 27,
BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 28,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 29,
BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 30,
BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 31,
BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 32,
BNXT_ULP_CF_IDX_ACT_DEC_TTL = 33,
BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 34,
BNXT_ULP_CF_IDX_LAST = 35
};
enum bnxt_ulp_cond_opcode {