net/mlx5: add hardware steering item translation
This provides shared item tranlsation code for hardware steering root table flows as they still work under FW steering mode. Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
This commit is contained in:
Suanming Mou
Raslan Darawsheh
parent
cd4ab74206
commit
75a00812b1
@ -63,10 +63,6 @@ tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev,
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uint32_t group, uint32_t *table,
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struct rte_flow_error *error);
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static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void);
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static void mlx5_flow_pop_thread_workspace(void);
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/** Device flow drivers. */
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extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops;
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@ -7108,7 +7104,7 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)
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struct rte_flow_item_port_id port_spec = {
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.id = MLX5_PORT_ESW_MGR,
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};
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struct mlx5_rte_flow_item_tx_queue txq_spec = {
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struct mlx5_rte_flow_item_sq txq_spec = {
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.queue = txq,
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};
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struct rte_flow_item pattern[] = {
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@ -7118,7 +7114,7 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)
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},
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{
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.type = (enum rte_flow_item_type)
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MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
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MLX5_RTE_FLOW_ITEM_TYPE_SQ,
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.spec = &txq_spec,
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},
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{
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@ -7404,7 +7400,7 @@ flow_alloc_thread_workspace(void)
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*
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* @return pointer to thread specific flow workspace data, NULL on error.
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*/
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static struct mlx5_flow_workspace*
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struct mlx5_flow_workspace*
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mlx5_flow_push_thread_workspace(void)
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{
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struct mlx5_flow_workspace *curr;
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@ -7441,7 +7437,7 @@ mlx5_flow_push_thread_workspace(void)
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*
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* @return pointer to thread specific flow workspace data, NULL on error.
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*/
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static void
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void
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mlx5_flow_pop_thread_workspace(void)
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{
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struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace();
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@ -7504,16 +7500,16 @@ mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev,
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.egress = 1,
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.priority = 0,
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};
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struct mlx5_rte_flow_item_tx_queue queue_spec = {
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struct mlx5_rte_flow_item_sq queue_spec = {
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.queue = queue,
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};
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struct mlx5_rte_flow_item_tx_queue queue_mask = {
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struct mlx5_rte_flow_item_sq queue_mask = {
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.queue = UINT32_MAX,
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};
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struct rte_flow_item items[] = {
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{
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.type = (enum rte_flow_item_type)
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MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
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MLX5_RTE_FLOW_ITEM_TYPE_SQ,
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.spec = &queue_spec,
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.last = NULL,
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.mask = &queue_mask,
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@ -28,7 +28,7 @@
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enum mlx5_rte_flow_item_type {
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MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
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MLX5_RTE_FLOW_ITEM_TYPE_TAG,
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MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
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MLX5_RTE_FLOW_ITEM_TYPE_SQ,
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MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
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MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
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};
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@ -95,7 +95,7 @@ struct mlx5_flow_action_copy_mreg {
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};
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/* Matches on source queue. */
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struct mlx5_rte_flow_item_tx_queue {
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struct mlx5_rte_flow_item_sq {
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uint32_t queue;
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};
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@ -159,7 +159,7 @@ enum mlx5_feature_name {
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#define MLX5_FLOW_LAYER_GENEVE (1u << 26)
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/* Queue items. */
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#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
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#define MLX5_FLOW_ITEM_SQ (1u << 27)
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/* Pattern tunnel Layer bits (continued). */
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#define MLX5_FLOW_LAYER_GTP (1u << 28)
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@ -196,6 +196,9 @@ enum mlx5_feature_name {
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#define MLX5_FLOW_ITEM_PORT_REPRESENTOR (UINT64_C(1) << 41)
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#define MLX5_FLOW_ITEM_REPRESENTED_PORT (UINT64_C(1) << 42)
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/* Meter color item */
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#define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44)
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/* Outer Masks. */
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#define MLX5_FLOW_LAYER_OUTER_L3 \
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(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
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@ -1009,6 +1012,18 @@ flow_items_to_tunnel(const struct rte_flow_item items[])
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return items[0].spec;
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}
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/* HW steering flow attributes. */
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struct mlx5_flow_attr {
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uint32_t port_id; /* Port index. */
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uint32_t group; /* Flow group. */
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uint32_t priority; /* Original Priority. */
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/* rss level, used by priority adjustment. */
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uint32_t rss_level;
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/* Action flags, used by priority adjustment. */
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uint32_t act_flags;
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uint32_t tbl_type; /* Flow table type. */
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};
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/* Flow structure. */
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struct rte_flow {
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uint32_t dev_handles;
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@ -1601,6 +1616,8 @@ struct mlx5_flow_driver_ops {
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/* mlx5_flow.c */
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struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void);
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void mlx5_flow_pop_thread_workspace(void);
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struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
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__extension__
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struct flow_grp_info {
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@ -1769,6 +1786,32 @@ mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
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int flow_hw_q_flow_flush(struct rte_eth_dev *dev,
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struct rte_flow_error *error);
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/*
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* Convert rte_mtr_color to mlx5 color.
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*
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* @param[in] rcol
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* rte_mtr_color.
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*
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* @return
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* mlx5 color.
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*/
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static inline int
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rte_col_2_mlx5_col(enum rte_color rcol)
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{
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switch (rcol) {
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case RTE_COLOR_GREEN:
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return MLX5_FLOW_COLOR_GREEN;
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case RTE_COLOR_YELLOW:
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return MLX5_FLOW_COLOR_YELLOW;
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case RTE_COLOR_RED:
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return MLX5_FLOW_COLOR_RED;
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default:
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break;
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}
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return MLX5_FLOW_COLOR_UNDEFINED;
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}
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int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
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const struct mlx5_flow_tunnel *tunnel,
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uint32_t group, uint32_t *table,
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@ -2128,4 +2171,9 @@ int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev,
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bool *all_ports,
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struct rte_flow_error *error);
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int flow_dv_translate_items_hws(const struct rte_flow_item *items,
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struct mlx5_flow_attr *attr, void *key,
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uint32_t key_type, uint64_t *item_flags,
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uint8_t *match_criteria,
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struct rte_flow_error *error);
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#endif /* RTE_PMD_MLX5_FLOW_H_ */
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@ -212,31 +212,6 @@ flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
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attr->valid = 1;
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}
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/*
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* Convert rte_mtr_color to mlx5 color.
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*
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* @param[in] rcol
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* rte_mtr_color.
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*
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* @return
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* mlx5 color.
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*/
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static inline int
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rte_col_2_mlx5_col(enum rte_color rcol)
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{
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switch (rcol) {
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case RTE_COLOR_GREEN:
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return MLX5_FLOW_COLOR_GREEN;
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case RTE_COLOR_YELLOW:
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return MLX5_FLOW_COLOR_YELLOW;
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case RTE_COLOR_RED:
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return MLX5_FLOW_COLOR_RED;
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default:
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break;
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}
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return MLX5_FLOW_COLOR_UNDEFINED;
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}
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struct field_modify_info {
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uint32_t size; /* Size of field in protocol header, in bytes. */
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uint32_t offset; /* Offset of field in protocol header, in bytes. */
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@ -7338,8 +7313,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
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return ret;
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last_item = MLX5_FLOW_ITEM_TAG;
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break;
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case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
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last_item = MLX5_FLOW_ITEM_TX_QUEUE;
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case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
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last_item = MLX5_FLOW_ITEM_SQ;
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break;
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case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
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break;
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@ -8225,7 +8200,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
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* work due to metadata regC0 mismatch.
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*/
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if ((!attr->transfer && attr->egress) && priv->representor &&
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!(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))
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!(item_flags & MLX5_FLOW_ITEM_SQ))
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return rte_flow_error_set(error, EINVAL,
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RTE_FLOW_ERROR_TYPE_ITEM,
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NULL,
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@ -11244,9 +11219,9 @@ flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
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const struct rte_flow_item *item,
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uint32_t key_type)
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{
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const struct mlx5_rte_flow_item_tx_queue *queue_m;
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const struct mlx5_rte_flow_item_tx_queue *queue_v;
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const struct mlx5_rte_flow_item_tx_queue queue_mask = {
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const struct mlx5_rte_flow_item_sq *queue_m;
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const struct mlx5_rte_flow_item_sq *queue_v;
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const struct mlx5_rte_flow_item_sq queue_mask = {
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.queue = UINT32_MAX,
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};
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void *misc_v =
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@ -13231,9 +13206,9 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
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flow_dv_translate_mlx5_item_tag(dev, key, items, key_type);
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last_item = MLX5_FLOW_ITEM_TAG;
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break;
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case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
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case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
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flow_dv_translate_item_tx_queue(dev, key, items, key_type);
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last_item = MLX5_FLOW_ITEM_TX_QUEUE;
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last_item = MLX5_FLOW_ITEM_SQ;
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break;
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case RTE_FLOW_ITEM_TYPE_GTP:
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flow_dv_translate_item_gtp(key, items, tunnel, key_type);
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@ -13273,6 +13248,105 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
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return 0;
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}
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/**
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* Fill the HW steering flow with DV spec.
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*
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* @param[in] items
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* Pointer to the list of items.
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* @param[in] attr
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* Pointer to the flow attributes.
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* @param[in] key
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* Pointer to the flow matcher key.
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* @param[in] key_type
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* Key type.
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* @param[in, out] item_flags
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* Pointer to the flow item flags.
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* @param[out] error
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* Pointer to the error structure.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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int
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flow_dv_translate_items_hws(const struct rte_flow_item *items,
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struct mlx5_flow_attr *attr, void *key,
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uint32_t key_type, uint64_t *item_flags,
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uint8_t *match_criteria,
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struct rte_flow_error *error)
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{
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struct mlx5_flow_workspace *flow_wks = mlx5_flow_push_thread_workspace();
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struct mlx5_flow_rss_desc rss_desc = { .level = attr->rss_level };
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struct rte_flow_attr rattr = {
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.group = attr->group,
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.priority = attr->priority,
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.ingress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_RX),
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.egress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_TX),
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.transfer = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_FDB),
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};
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struct mlx5_dv_matcher_workspace wks = {
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.action_flags = attr->act_flags,
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.item_flags = item_flags ? *item_flags : 0,
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.external = 0,
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.next_protocol = 0xff,
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.attr = &rattr,
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.rss_desc = &rss_desc,
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};
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int ret = 0;
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RTE_SET_USED(flow_wks);
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for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
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if (!mlx5_flow_os_item_supported(items->type)) {
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ret = rte_flow_error_set(error, ENOTSUP,
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RTE_FLOW_ERROR_TYPE_ITEM,
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NULL, "item not supported");
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goto exit;
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}
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ret = flow_dv_translate_items(&rte_eth_devices[attr->port_id],
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items, &wks, key, key_type, NULL);
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if (ret)
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goto exit;
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}
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if (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) {
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flow_dv_translate_item_vxlan_gpe(key,
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wks.tunnel_item,
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wks.item_flags,
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key_type);
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} else if (wks.item_flags & MLX5_FLOW_LAYER_GENEVE) {
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flow_dv_translate_item_geneve(key,
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wks.tunnel_item,
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wks.item_flags,
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key_type);
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} else if (wks.item_flags & MLX5_FLOW_LAYER_GRE) {
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if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE) {
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flow_dv_translate_item_gre(key,
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wks.tunnel_item,
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wks.item_flags,
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key_type);
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} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) {
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flow_dv_translate_item_gre_option(key,
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wks.tunnel_item,
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wks.gre_item,
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wks.item_flags,
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key_type);
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} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) {
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flow_dv_translate_item_nvgre(key,
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wks.tunnel_item,
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wks.item_flags,
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key_type);
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} else {
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MLX5_ASSERT(false);
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}
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}
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if (match_criteria)
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*match_criteria = flow_dv_matcher_enable(key);
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if (item_flags)
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*item_flags = wks.item_flags;
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exit:
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mlx5_flow_pop_thread_workspace();
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return ret;
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}
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/**
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* Fill the SW steering flow with DV spec.
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*
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