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net/e1000/base: add workaround for possible stalled packet

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This works around a possible stalled packet issue, which may occur due to
clock recovery from the PCH being too slow, when the LAN is transitioning
from K1 at 1G link speed.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Wenzhuo Lu 2016-11-23 12:22:56 -05:00 committed by Ferruh Yigit
parent a3358d942f
commit 75a202f022
2 changed files with 11 additions and 1 deletions
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10
drivers/net/e1000/base/e1000_ich8lan.c
View File

@ -1584,6 +1584,16 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
hw->phy.ops.write_reg_locked(hw,
I217_PLL_CLOCK_GATE_REG,
phy_reg);
if (speed == SPEED_1000) {
hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
&phy_reg);
phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
phy_reg);
}
}
hw->phy.ops.release(hw);

2
drivers/net/e1000/base/e1000_ich8lan.h
View File

@ -250,7 +250,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* PHY Power Management Control */
#define HV_PM_CTRL PHY_REG(770, 17)
#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
#define HV_PM_CTRL_K1_CLK_REQ 0x200
#define HV_PM_CTRL_K1_ENABLE 0x4000
#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)