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crypto/qat: support SM3 hash algorithm

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Added support for ShangMi 3 (SM3) hash algorithm.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
This commit is contained in:
Arek Kusztal 2022-09-30 10:41:08 +01:00 committed by Akhil Goyal
parent 92522c84e4
commit 75fd4bbc94
4 changed files with 26 additions and 5 deletions
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1
doc/guides/cryptodevs/features/qat.ini
View File

@ -65,6 +65,7 @@ KASUMI F9 = Y
AES XCBC MAC = Y
ZUC EIA3 = Y
AES CMAC (128) = Y
SM3 = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.

1
doc/guides/rel_notes/release_22_11.rst
View File

@ -94,6 +94,7 @@ New Features
* **Updated Intel QuickAssist Technology (QAT) symmetric crypto driver.**
* Added support for SM3 hash algorithm.
* Added support for SM4 encryption algorithm in ECB, CBC and CTR modes.
* **Updated Marvell cnxk crypto driver.**

4
drivers/common/qat/qat_adf/icp_qat_hw.h
View File

@ -46,7 +46,7 @@ enum icp_qat_hw_auth_algo {
ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
ICP_QAT_HW_AUTH_RESERVED_1 = 15,
ICP_QAT_HW_AUTH_ALGO_SM3 = 15,
ICP_QAT_HW_AUTH_RESERVED_2 = 16,
ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
ICP_QAT_HW_AUTH_RESERVED_3 = 18,
@ -134,6 +134,7 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SM3_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
@ -153,6 +154,7 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SM3_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0

25
drivers/crypto/qat/qat_sym_session.c
View File

@ -102,6 +102,13 @@ static const uint8_t sha512InitialState[] = {
0x2b, 0x3e, 0x6c, 0x1f, 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd,
0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79};
static uint8_t sm3InitialState[] = {
0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9,
0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00,
0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa,
0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e
};
static int
qat_sym_cd_cipher_set(struct qat_sym_session *cd,
const uint8_t *enckey,
@ -708,6 +715,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->digest_length = auth_xform->digest_length;
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SM3:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;
session->auth_mode = ICP_QAT_HW_AUTH_MODE2;
break;
case RTE_CRYPTO_AUTH_SHA1:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
@ -1051,6 +1062,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_SM3:
return QAT_HW_ROUND_UP(ICP_QAT_HW_SM3_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_NULL:
return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
@ -2069,11 +2083,14 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
}
cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_auth_setup);
/*
* cd_cur_ptr now points at the state1 information.
*/
switch (cdesc->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SM3:
rte_memcpy(cdesc->cd_cur_ptr, sm3InitialState,
sizeof(sm3InitialState));
state1_size = qat_hash_get_state1_size(
cdesc->qat_hash_alg);
state2_size = ICP_QAT_HW_SM3_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA1:
if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {
/* Plain SHA-1 */