ixgbe/base: new X557 phy
Add new phy ID: X557_PHY_ID, and implement its internal setup function and external init function. Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com>
This commit is contained in:
Ouyang Changchun
Thomas Monjalon
parent
3b3a1423b1
commit
76d5b807ff
@ -536,6 +536,20 @@ s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
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IXGBE_NOT_IMPLEMENTED);
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}
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/**
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* ixgbe_setup_internal_phy - Configure integrated PHY
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* @hw: pointer to hardware structure
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*
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* Reconfigure the integrated PHY in order to enable talk to the external PHY.
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* Returns success if not implemented, since nothing needs to be done in this
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* case.
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*/
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s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
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{
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return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
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IXGBE_SUCCESS);
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}
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/**
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* ixgbe_check_phy_link - Determine link and speed status
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* @hw: pointer to hardware structure
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@ -70,6 +70,7 @@ s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 phy_data);
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s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
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s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);
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s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *link_up);
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@ -435,6 +435,9 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
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case ATH_PHY_ID:
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phy_type = ixgbe_phy_nl;
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break;
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case X557_PHY_ID:
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phy_type = ixgbe_phy_x550em_ext_t;
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break;
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default:
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phy_type = ixgbe_phy_unknown;
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break;
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@ -1374,6 +1374,7 @@ struct ixgbe_dmac_config {
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#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
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#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
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#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */
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@ -1394,10 +1395,17 @@ struct ixgbe_dmac_config {
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#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
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#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
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#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
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#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */
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#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
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#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
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#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
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#define IXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */
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#define IXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */
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@ -1408,6 +1416,21 @@ struct ixgbe_dmac_config {
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/* MII clause 22/28 definitions */
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#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
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#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register*/
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#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
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#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
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#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
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#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
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#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
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@ -1432,6 +1455,7 @@ struct ixgbe_dmac_config {
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#define TNX_FW_REV 0xB
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#define X540_PHY_ID 0x01540200
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#define X550_PHY_ID 0x01540220
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#define X557_PHY_ID 0x01540240
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#define AQ_FW_REV 0x20
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#define QT2022_PHY_ID 0x0043A400
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#define ATH_PHY_ID 0x03429050
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@ -3186,6 +3210,7 @@ enum ixgbe_phy_type {
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ixgbe_phy_aq,
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ixgbe_phy_x550em_kr,
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ixgbe_phy_x550em_kx4,
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ixgbe_phy_x550em_ext_t,
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ixgbe_phy_cu_unknown,
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ixgbe_phy_qt,
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ixgbe_phy_xaui,
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@ -3536,6 +3561,7 @@ struct ixgbe_phy_operations {
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s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
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s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
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s32 (*setup_link)(struct ixgbe_hw *);
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s32 (*setup_internal_link)(struct ixgbe_hw *);
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s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
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s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
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s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
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@ -185,8 +185,6 @@ s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
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ixgbe_get_supported_physical_layer_X550em;
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/* PHY */
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phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
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phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
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phy->ops.init = ixgbe_init_phy_ops_X550em;
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phy->ops.identify = ixgbe_identify_phy_x550em;
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if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
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@ -944,6 +942,11 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
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switch (hw->phy.type) {
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case ixgbe_phy_x550em_kr:
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phy->ops.setup_link = ixgbe_setup_kr_x550em;
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phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
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phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
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break;
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case ixgbe_phy_x550em_ext_t:
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phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
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break;
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default:
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break;
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@ -985,6 +988,13 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
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if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
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return status;
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/* start the external PHY */
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if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
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status = ixgbe_init_ext_t_x550em(hw);
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if (status)
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return status;
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}
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/* Setup SFP module if there is one present. */
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if (hw->phy.sfp_setup_needed) {
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status = hw->mac.ops.setup_sfp(hw);
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@ -1049,6 +1059,97 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
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hw->mac.num_rar_entries = 128;
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hw->mac.ops.init_rx_addrs(hw);
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return status;
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}
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/**
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* ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
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* @hw: pointer to hardware structure
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*/
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s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
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{
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u32 status;
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u16 reg;
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u32 retries = 1;
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/* TODO: The number of attempts and delay between attempts is undefined */
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do {
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/* decrement retries counter and exit if we hit 0 */
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if (retries < 1) {
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ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
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"External PHY not yet finished resetting.");
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return IXGBE_ERR_PHY;
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}
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retries--;
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usec_delay(0);
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status = hw->phy.ops.read_reg(hw,
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IXGBE_MDIO_TX_VENDOR_ALARMS_3,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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®);
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if (status != IXGBE_SUCCESS)
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return status;
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/* Verify PHY FW reset has completed */
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} while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
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/* Set port to low power mode */
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status = hw->phy.ops.read_reg(hw,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
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®);
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if (status != IXGBE_SUCCESS)
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return status;
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reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
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status = hw->phy.ops.write_reg(hw,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
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reg);
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if (status != IXGBE_SUCCESS)
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return status;
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/* Enable the transmitter */
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status = hw->phy.ops.read_reg(hw,
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IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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®);
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if (status != IXGBE_SUCCESS)
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return status;
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reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
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status = hw->phy.ops.write_reg(hw,
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IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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reg);
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if (status != IXGBE_SUCCESS)
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return status;
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/* Un-stall the PHY FW */
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status = hw->phy.ops.read_reg(hw,
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IXGBE_MDIO_GLOBAL_RES_PR_10,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
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®);
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if (status != IXGBE_SUCCESS)
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return status;
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reg &= ~IXGBE_MDIO_POWER_UP_STALL;
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status = hw->phy.ops.write_reg(hw,
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IXGBE_MDIO_GLOBAL_RES_PR_10,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
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reg);
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return status;
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}
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@ -1095,10 +1196,12 @@ s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
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/**
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* ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
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* @hw: pointer to hardware structure
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* @speed: the link speed to force
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*
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* Configures the integrated KR PHY to use iXFI mode.
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* Configures the integrated KR PHY to use iXFI mode. Used to connect an
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* internal and external PHY at a specific speed, without autonegotiation.
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**/
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s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
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STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
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{
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s32 status;
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u32 reg_val;
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@ -1112,7 +1215,20 @@ s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
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reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
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reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
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reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
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/* Select forced link speed for internal PHY. */
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switch (*speed) {
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case IXGBE_LINK_SPEED_10GB_FULL:
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reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
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break;
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case IXGBE_LINK_SPEED_1GB_FULL:
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reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
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break;
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default:
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/* Other link speeds are not supported by internal KR PHY. */
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return IXGBE_ERR_LINK_SETUP;
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}
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status = ixgbe_write_iosf_sb_reg_x550(hw,
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IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
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IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
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@ -1190,6 +1306,74 @@ s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
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return status;
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}
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/**
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* ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
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* @hw: point to hardware structure
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*
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* Configures the integrated KR PHY to talk to the external PHY. The base
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* driver will call this function when it gets notification via interrupt from
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* the external PHY. This function forces the internal PHY into iXFI mode at
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* the correct speed.
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*
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* A return of a non-zero value indicates an error, and the base driver should
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* not report link up.
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*/
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s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
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{
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u32 status;
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u16 lasi, autoneg_status, speed;
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ixgbe_link_speed force_speed;
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/* Verify that the external link status has changed */
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&lasi);
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if (status != IXGBE_SUCCESS)
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return status;
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/* If there was no change in link status, we can just exit */
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if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
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return IXGBE_SUCCESS;
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/* we read this twice back to back to indicate current status */
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_status);
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if (status != IXGBE_SUCCESS)
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return status;
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_status);
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if (status != IXGBE_SUCCESS)
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return status;
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/* If link is not up return an error indicating treat link as down */
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if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
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return IXGBE_ERR_INVALID_LINK_SETTINGS;
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&speed);
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/* clear everything but the speed and duplex bits */
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speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
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switch (speed) {
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case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
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force_speed = IXGBE_LINK_SPEED_10GB_FULL;
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break;
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case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
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force_speed = IXGBE_LINK_SPEED_1GB_FULL;
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break;
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default:
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/* Internal PHY does not support anything else */
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return IXGBE_ERR_INVALID_LINK_SETTINGS;
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}
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return ixgbe_setup_ixfi_x550em(hw, &force_speed);
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}
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/**
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* ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
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* @hw: pointer to hardware structure
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@ -1748,6 +1932,7 @@ s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
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u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
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{
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u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
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u16 ext_ability = 0;
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DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
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@ -1762,6 +1947,15 @@ u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
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physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
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IXGBE_PHYSICAL_LAYER_1000BASE_KX;
|
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break;
|
||||
case ixgbe_phy_x550em_ext_t:
|
||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
|
||||
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
|
||||
&ext_ability);
|
||||
if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
|
||||
physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
|
||||
if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
|
||||
physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
@ -80,7 +80,9 @@ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw);
|
||||
u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);
|
||||
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user