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net/qede: add PCI ids for new chip variant

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Add PCI IDs for new asic type (defined as CHIP_NUM_AH_xxx).
It supports 50G, 40G, 25G and 10G speeds.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody 2017-01-04 23:04:02 -08:00 committed by Ferruh Yigit
parent 0b46a4e6ae
commit 77f7222124
3 changed files with 55 additions and 24 deletions
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7
drivers/net/qede/base/ecore_dev.c
View File

@ -2365,7 +2365,12 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
#endif #endif
for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc); /* @@@TMP for AH:
* Force the driver's default resource allocation in case there
* is a diff with the MFW allocation value.
*/
rc = ecore_hw_set_resc_info(p_hwfn, res_id,
b_ah || drv_resc_alloc);
if (rc != ECORE_SUCCESS) if (rc != ECORE_SUCCESS)
return rc; return rc;
} }

29
drivers/net/qede/qede_ethdev.c
View File

@ -2267,10 +2267,13 @@ static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
static struct rte_pci_id pci_id_qedevf_map[] = { static struct rte_pci_id pci_id_qedevf_map[] = {
#define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
{ {
QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF) QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
}, },
{ {
QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV) QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
},
{
QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
}, },
{.vendor_id = 0,} {.vendor_id = 0,}
}; };
@ -2278,19 +2281,31 @@ static struct rte_pci_id pci_id_qedevf_map[] = {
static struct rte_pci_id pci_id_qede_map[] = { static struct rte_pci_id pci_id_qede_map[] = {
#define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
{ {
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E) QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
}, },
{ {
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S) QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
}, },
{ {
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40) QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
}, },
{ {
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25) QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
}, },
{ {
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100) QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
},
{
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
},
{
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
},
{
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
},
{
QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
}, },
{.vendor_id = 0,} {.vendor_id = 0,}
}; };

43
drivers/net/qede/qede_ethdev.h
View File

@ -92,24 +92,35 @@
struct ecore_dev *edev = &qdev->edev; \ struct ecore_dev *edev = &qdev->edev; \
} }
/************* QLogic 25G/40G/100G vendor/devices ids *************/ /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
#define PCI_VENDOR_ID_QLOGIC 0x1077 #define PCI_VENDOR_ID_QLOGIC 0x1077
#define CHIP_NUM_57980E 0x1634 #define CHIP_NUM_57980E 0x1634
#define CHIP_NUM_57980S 0x1629 #define CHIP_NUM_57980S 0x1629
#define CHIP_NUM_VF 0x1630 #define CHIP_NUM_VF 0x1630
#define CHIP_NUM_57980S_40 0x1634 #define CHIP_NUM_57980S_40 0x1634
#define CHIP_NUM_57980S_25 0x1656 #define CHIP_NUM_57980S_25 0x1656
#define CHIP_NUM_57980S_IOV 0x1664 #define CHIP_NUM_57980S_IOV 0x1664
#define CHIP_NUM_57980S_100 0x1644 #define CHIP_NUM_57980S_100 0x1644
#define CHIP_NUM_AH_50G 0x8070
#define CHIP_NUM_AH_10G 0x8071
#define CHIP_NUM_AH_40G 0x8072
#define CHIP_NUM_AH_25G 0x8073
#define CHIP_NUM_AH_IOV 0x8090
#define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
#define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
#define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
#define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
#define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
#define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
#define PCI_DEVICE_ID_NX2_57980E CHIP_NUM_57980E
#define PCI_DEVICE_ID_NX2_57980S CHIP_NUM_57980S
#define PCI_DEVICE_ID_NX2_VF CHIP_NUM_VF
#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
#define QEDE_VXLAN_DEF_PORT 8472 #define QEDE_VXLAN_DEF_PORT 8472