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common/mlx5: remove doorbell allocation functions

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The mlx5_devx_dbr_page structure was used to allocate and release the
umem of the doorbells.
Since doorbell and buffer have used same umem, this structure is
useless.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Michael Baum 2021-01-06 08:19:41 +00:00 committed by Ferruh Yigit
parent 6e0a3637d8
commit 7819b8fb9a
4 changed files with 0 additions and 151 deletions
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122
drivers/common/mlx5/mlx5_common.c
View File

@ -8,12 +8,10 @@
#include <rte_errno.h>
#include <rte_mempool.h>
#include <rte_malloc.h>
#include "mlx5_common.h"
#include "mlx5_common_os.h"
#include "mlx5_common_utils.h"
#include "mlx5_malloc.h"
#include "mlx5_common_pci.h"
int mlx5_common_logtype;
@ -125,126 +123,6 @@ RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
haswell_broadwell_cpu = 0;
}
/**
* Allocate page of door-bells and register it using DevX API.
*
* @param [in] ctx
* Pointer to the device context.
*
* @return
* Pointer to new page on success, NULL otherwise.
*/
static struct mlx5_devx_dbr_page *
mlx5_alloc_dbr_page(void *ctx)
{
struct mlx5_devx_dbr_page *page;
/* Allocate space for door-bell page and management data. */
page = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
sizeof(struct mlx5_devx_dbr_page),
RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
if (!page) {
DRV_LOG(ERR, "cannot allocate dbr page");
return NULL;
}
/* Register allocated memory. */
page->umem = mlx5_os_umem_reg(ctx, page->dbrs,
MLX5_DBR_PAGE_SIZE, 0);
if (!page->umem) {
DRV_LOG(ERR, "cannot umem reg dbr page");
mlx5_free(page);
return NULL;
}
return page;
}
/**
* Find the next available door-bell, allocate new page if needed.
*
* @param [in] ctx
* Pointer to device context.
* @param [in] head
* Pointer to the head of dbr pages list.
* @param [out] dbr_page
* Door-bell page containing the page data.
*
* @return
* Door-bell address offset on success, a negative error value otherwise.
*/
int64_t
mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,
struct mlx5_devx_dbr_page **dbr_page)
{
struct mlx5_devx_dbr_page *page = NULL;
uint32_t i, j;
LIST_FOREACH(page, head, next)
if (page->dbr_count < MLX5_DBR_PER_PAGE)
break;
if (!page) { /* No page with free door-bell exists. */
page = mlx5_alloc_dbr_page(ctx);
if (!page) /* Failed to allocate new page. */
return (-1);
LIST_INSERT_HEAD(head, page, next);
}
/* Loop to find bitmap part with clear bit. */
for (i = 0;
i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
i++)
; /* Empty. */
/* Find the first clear bit. */
MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
j = rte_bsf64(~page->dbr_bitmap[i]);
page->dbr_bitmap[i] |= (UINT64_C(1) << j);
page->dbr_count++;
*dbr_page = page;
return (i * CHAR_BIT * sizeof(uint64_t) + j) * MLX5_DBR_SIZE;
}
/**
* Release a door-bell record.
*
* @param [in] head
* Pointer to the head of dbr pages list.
* @param [in] umem_id
* UMEM ID of page containing the door-bell record to release.
* @param [in] offset
* Offset of door-bell record in page.
*
* @return
* 0 on success, a negative error value otherwise.
*/
int32_t
mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,
uint64_t offset)
{
struct mlx5_devx_dbr_page *page = NULL;
int ret = 0;
LIST_FOREACH(page, head, next)
/* Find the page this address belongs to. */
if (mlx5_os_get_umem_id(page->umem) == umem_id)
break;
if (!page)
return -EINVAL;
page->dbr_count--;
if (!page->dbr_count) {
/* Page not used, free it and remove from list. */
LIST_REMOVE(page, next);
if (page->umem)
ret = -mlx5_os_umem_dereg(page->umem);
mlx5_free(page);
} else {
/* Mark in bitmap that this door-bell is not in use. */
offset /= MLX5_DBR_SIZE;
int i = offset / 64;
int j = offset % 64;
page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
}
return ret;
}
/**
* Allocate the User Access Region with DevX on specified device.
*

23
drivers/common/mlx5/mlx5_common.h
View File

@ -220,21 +220,6 @@ enum mlx5_class {
};
#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
#define MLX5_DBR_PER_PAGE 64
/* Must be >= CHAR_BIT * sizeof(uint64_t) */
#define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE)
/* Page size must be >= 512. */
#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t)))
struct mlx5_devx_dbr_page {
/* Door-bell records, must be first member in structure. */
uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
void *umem;
uint32_t dbr_count; /* Number of door-bell records in use. */
/* 1 bit marks matching door-bell is in use. */
uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
};
/* devX creation object */
struct mlx5_devx_obj {
@ -249,19 +234,11 @@ struct mlx5_klm {
uint64_t address;
};
LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page);
__rte_internal
void mlx5_translate_port_name(const char *port_name_in,
struct mlx5_switch_info *port_info_out);
void mlx5_glue_constructor(void);
__rte_internal
int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,
struct mlx5_devx_dbr_page **dbr_page);
__rte_internal
int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,
uint64_t offset);
__rte_internal
void *mlx5_devx_alloc_uar(void *ctx, int mapping);
extern uint8_t haswell_broadwell_cpu;

3
drivers/common/mlx5/rte_common_mlx5_exports.def
View File

@ -42,7 +42,6 @@ EXPORTS
mlx5_devx_sq_create
mlx5_devx_sq_destroy
mlx5_get_dbr
mlx5_glue
mlx5_malloc_mem_select
@ -63,8 +62,6 @@ EXPORTS
mlx5_pci_driver_register
mlx5_release_dbr
mlx5_malloc
mlx5_realloc
mlx5_free

3
drivers/common/mlx5/version.map
View File

@ -51,7 +51,6 @@ INTERNAL {
mlx5_devx_sq_destroy;
mlx5_get_ifname_sysfs;
mlx5_get_dbr;
mlx5_mp_init_primary;
mlx5_mp_uninit_primary;
@ -93,8 +92,6 @@ INTERNAL {
mlx5_nl_vlan_vmwa_create;
mlx5_nl_vlan_vmwa_delete;
mlx5_release_dbr;
mlx5_translate_port_name;
mlx5_malloc_mem_select;