i40e: add hash configuration
Hash filter control has been implemented for i40e. It includes getting/setting, - global hash configurations (hash function type, and symmetric hash enable per flow type) - symmetric hash enable per port Signed-off-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This commit is contained in:
Helin Zhang
Thomas Monjalon
parent
a98ff8a3c3
commit
782c8c92f1
@ -93,6 +93,18 @@
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I40E_PFINT_ICR0_ENA_VFLR_MASK | \
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I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
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#define I40E_FLOW_TYPES ( \
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(1UL << RTE_ETH_FLOW_TYPE_UDPV4) | \
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(1UL << RTE_ETH_FLOW_TYPE_TCPV4) | \
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(1UL << RTE_ETH_FLOW_TYPE_SCTPV4) | \
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(1UL << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
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(1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
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(1UL << RTE_ETH_FLOW_TYPE_UDPV6) | \
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(1UL << RTE_ETH_FLOW_TYPE_TCPV6) | \
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(1UL << RTE_ETH_FLOW_TYPE_SCTPV6) | \
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(1UL << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
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(1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
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static int eth_i40e_dev_init(\
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__attribute__((unused)) struct eth_driver *eth_drv,
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struct rte_eth_dev *eth_dev);
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@ -199,6 +211,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
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enum rte_filter_op filter_op,
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void *arg);
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static void i40e_configure_registers(struct i40e_hw *hw);
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static void i40e_hw_init(struct i40e_hw *hw);
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static struct rte_pci_id pci_id_i40e_map[] = {
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#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
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@ -398,6 +411,9 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
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/* Make sure all is clean before doing PF reset */
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i40e_clear_hw(hw);
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/* Initialize the hardware */
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i40e_hw_init(hw);
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/* Reset here to make sure all is clean for each PF */
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ret = i40e_pf_reset(hw);
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if (ret) {
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@ -5136,6 +5152,260 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)
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return ret;
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}
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/* Get the symmetric hash enable configurations per port */
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static void
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i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
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{
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uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
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*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
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}
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/* Set the symmetric hash enable configurations per port */
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static void
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i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
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{
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uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
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if (enable > 0) {
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if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
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PMD_DRV_LOG(INFO, "Symmetric hash has already "
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"been enabled");
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return;
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}
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reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
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} else {
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if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
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PMD_DRV_LOG(INFO, "Symmetric hash has already "
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"been disabled");
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return;
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}
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reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
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}
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I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
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I40E_WRITE_FLUSH(hw);
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}
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/*
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* Get global configurations of hash function type and symmetric hash enable
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* per flow type (pctype). Note that global configuration means it affects all
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* the ports on the same NIC.
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*/
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static int
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i40e_get_hash_filter_global_config(struct i40e_hw *hw,
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struct rte_eth_hash_global_conf *g_cfg)
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{
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uint32_t reg, mask = I40E_FLOW_TYPES;
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uint32_t i;
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enum i40e_filter_pctype pctype;
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memset(g_cfg, 0, sizeof(*g_cfg));
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reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
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if (reg & I40E_GLQF_CTL_HTOEP_MASK)
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g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
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else
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g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
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PMD_DRV_LOG(DEBUG, "Hash function is %s",
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(reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
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for (i = 0; mask && i < RTE_ETH_FLOW_TYPE_MAX; i++) {
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if (!(mask & (1UL << i)))
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continue;
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mask &= ~(1UL << i);
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/* Bit set indicats the coresponding flow type is supported */
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g_cfg->valid_bit_mask[0] |= (1UL << i);
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pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
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reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
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if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
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g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
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}
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return 0;
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}
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static int
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i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
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{
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uint32_t i;
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uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
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if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
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g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
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g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
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PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
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g_cfg->hash_func);
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return -EINVAL;
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}
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/*
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* As i40e supports less than 32 flow types, only first 32 bits need to
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* be checked.
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*/
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mask0 = g_cfg->valid_bit_mask[0];
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for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
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if (i == 0) {
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/* Check if any unsupported flow type configured */
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if ((mask0 | i40e_mask) ^ i40e_mask)
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goto mask_err;
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} else {
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if (g_cfg->valid_bit_mask[i])
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goto mask_err;
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}
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}
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return 0;
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mask_err:
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PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
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return -EINVAL;
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}
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/*
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* Set global configurations of hash function type and symmetric hash enable
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* per flow type (pctype). Note any modifying global configuration will affect
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* all the ports on the same NIC.
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*/
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static int
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i40e_set_hash_filter_global_config(struct i40e_hw *hw,
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struct rte_eth_hash_global_conf *g_cfg)
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{
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int ret;
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uint32_t i, reg;
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uint32_t mask0 = g_cfg->valid_bit_mask[0];
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enum i40e_filter_pctype pctype;
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/* Check the input parameters */
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ret = i40e_hash_global_config_check(g_cfg);
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if (ret < 0)
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return ret;
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for (i = 0; mask0 && i < UINT32_BIT; i++) {
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if (!(mask0 & (1UL << i)))
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continue;
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mask0 &= ~(1UL << i);
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pctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);
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reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
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I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
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I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
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}
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reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
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if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
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/* Toeplitz */
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if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
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PMD_DRV_LOG(DEBUG, "Hash function already set to "
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"Toeplitz");
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goto out;
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}
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reg |= I40E_GLQF_CTL_HTOEP_MASK;
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} else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
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/* Simple XOR */
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if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
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PMD_DRV_LOG(DEBUG, "Hash function already set to "
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"Simple XOR");
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goto out;
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}
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reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
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} else
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/* Use the default, and keep it as it is */
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goto out;
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I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
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out:
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I40E_WRITE_FLUSH(hw);
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return 0;
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}
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static int
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i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
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{
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int ret = 0;
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if (!hw || !info) {
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PMD_DRV_LOG(ERR, "Invalid pointer");
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return -EFAULT;
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}
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switch (info->info_type) {
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case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
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i40e_get_symmetric_hash_enable_per_port(hw,
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&(info->info.enable));
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break;
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case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
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ret = i40e_get_hash_filter_global_config(hw,
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&(info->info.global_conf));
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break;
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default:
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PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
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info->info_type);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int
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i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
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{
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int ret = 0;
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if (!hw || !info) {
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PMD_DRV_LOG(ERR, "Invalid pointer");
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return -EFAULT;
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}
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switch (info->info_type) {
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case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
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i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
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break;
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case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
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ret = i40e_set_hash_filter_global_config(hw,
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&(info->info.global_conf));
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break;
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default:
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PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
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info->info_type);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/* Operations for hash function */
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static int
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i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
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enum rte_filter_op filter_op,
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void *arg)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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int ret = 0;
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switch (filter_op) {
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case RTE_ETH_FILTER_NOP:
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break;
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case RTE_ETH_FILTER_GET:
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ret = i40e_hash_filter_get(hw,
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(struct rte_eth_hash_filter_info *)arg);
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break;
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case RTE_ETH_FILTER_SET:
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ret = i40e_hash_filter_set(hw,
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(struct rte_eth_hash_filter_info *)arg);
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break;
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default:
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PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
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filter_op);
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ret = -ENOTSUP;
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break;
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}
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return ret;
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}
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/*
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* Configure ethertype filter, which can director packet by filtering
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* with mac address and ether_type or only ether_type
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@ -5238,6 +5508,9 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
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return -EINVAL;
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switch (filter_type) {
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case RTE_ETH_FILTER_HASH:
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ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
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break;
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case RTE_ETH_FILTER_MACVLAN:
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ret = i40e_mac_filter_handle(dev, filter_op, arg);
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break;
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@ -5260,10 +5533,26 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
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return ret;
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}
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/*
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* As some registers wouldn't be reset unless a global hardware reset,
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* hardware initialization is needed to put those registers into an
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* expected initial state.
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*/
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static void
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i40e_hw_init(struct i40e_hw *hw)
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{
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/* clear the PF Queue Filter control register */
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I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
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/* Disable symmetric hash per port */
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i40e_set_symmetric_hash_enable_per_port(hw, 0);
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}
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enum i40e_filter_pctype
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i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
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{
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static const enum i40e_filter_pctype pctype_table[] = {
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static const enum i40e_filter_pctype
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pctype_table[RTE_ETH_FLOW_TYPE_MAX] = {
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[RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
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[RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
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[RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
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@ -5286,7 +5575,8 @@ i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)
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enum rte_eth_flow_type
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i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
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{
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static const enum rte_eth_flow_type flowtype_table[] = {
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static const enum rte_eth_flow_type
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flowtype_table[RTE_ETH_FLOW_TYPE_MAX] = {
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[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,
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[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,
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[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,
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