net/ice: support low Rx latency
This patch adds a devarg parameter to enable/disable low Rx latency. Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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@ -227,6 +227,18 @@ Runtime Config Options
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-a af:00.0,pps_out='[pin:0]'
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- ``Low Rx latency`` (default ``0``)
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vRAN workloads require low latency DPDK interface for the front haul
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interface connection to Radio. By specifying ``1`` for parameter
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``rx_low_latency``, each completed Rx descriptor can be written immediately
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to host memory and the Rx interrupt latency can be reduced to 2us::
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-a 0000:88:00.0,rx_low_latency=1
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As a trade-off, this configuration may cause the packet processing performance
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degradation due to the PCI bandwidth limitation.
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Driver compilation and testing
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------------------------------
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@ -30,6 +30,7 @@
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#define ICE_PROTO_XTR_ARG "proto_xtr"
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#define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask"
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#define ICE_ONE_PPS_OUT_ARG "pps_out"
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#define ICE_RX_LOW_LATENCY_ARG "rx_low_latency"
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static const char * const ice_valid_args[] = {
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ICE_SAFE_MODE_SUPPORT_ARG,
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@ -37,6 +38,7 @@ static const char * const ice_valid_args[] = {
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ICE_PROTO_XTR_ARG,
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ICE_HW_DEBUG_MASK_ARG,
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ICE_ONE_PPS_OUT_ARG,
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ICE_RX_LOW_LATENCY_ARG,
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NULL
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};
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@ -1956,6 +1958,9 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
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if (ret)
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goto bail;
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ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG,
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&parse_bool, &ad->devargs.rx_low_latency);
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bail:
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rte_kvargs_free(kvlist);
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return ret;
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@ -3272,8 +3277,9 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
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{
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struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
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uint32_t val, val_tx;
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int i;
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int rx_low_latency, i;
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rx_low_latency = vsi->adapter->devargs.rx_low_latency;
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for (i = 0; i < nb_queue; i++) {
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/*do actual bind*/
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val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
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@ -3283,8 +3289,21 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
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PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
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base_queue + i, msix_vect);
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/* set ITR0 value */
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ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
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if (rx_low_latency) {
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/**
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* Empirical configuration for optimal real time
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* latency reduced interrupt throttling to 2us
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*/
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ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
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ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),
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QRX_ITR_NO_EXPR_M);
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} else {
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ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
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ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);
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}
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ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
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ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
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}
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@ -5497,7 +5516,8 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ice,
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ICE_HW_DEBUG_MASK_ARG "=0xXXX"
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ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
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ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
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ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
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ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
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ICE_RX_LOW_LATENCY_ARG "=<0|1>");
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RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
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RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
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@ -476,6 +476,7 @@ struct ice_pf {
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* Cache devargs parse result.
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*/
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struct ice_devargs {
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int rx_low_latency;
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int safe_mode_support;
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uint8_t proto_xtr_dflt;
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int pipe_mode_support;
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