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net/qede/base: semantic changes

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Make APIs static and other semantic changes.
A step toward cleaning 'make C=1' with GCC 4.8.3.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody 2017-03-29 13:36:58 -07:00 committed by Ferruh Yigit
parent 39f0eb3bbb
commit 7a5dfdc1f3
6 changed files with 66 additions and 75 deletions
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5
drivers/net/qede/base/ecore_cxt.c
View File

@ -327,7 +327,8 @@ static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
}
}
void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
struct ecore_qm_iids *iids)
{
struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct ecore_tid_seg *segs;
@ -1945,7 +1946,7 @@ enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
{
struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;

11
drivers/net/qede/base/ecore_cxt.h
View File

@ -35,17 +35,6 @@ u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
enum protocol_type type);
u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn);
#ifndef LINUX_REMOVE
/**
* @brief ecore_cxt_qm_iids - fills the cid/tid counts for the QM configuration
*
* @param p_hwfn
* @param iids [out], a structure holding all the counters
*/
void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
struct ecore_qm_iids *iids);
#endif
/**
* @brief ecore_cxt_set_pf_params - Set the PF params for cxt init
*

2
drivers/net/qede/base/ecore_dcbx.c
View File

@ -114,7 +114,7 @@ ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,
}
}
void
static void
ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
struct ecore_hwfn *p_hwfn,
bool enable, u8 prio, u8 tc,

109
drivers/net/qede/base/ecore_dev.c
View File

@ -759,8 +759,8 @@ enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
enum _ecore_status_t rc;
bool b_rc;
enum _ecore_status_t rc;
/* initialize ecore's qm data structure */
ecore_init_qm_info(p_hwfn);
@ -1507,54 +1507,6 @@ static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
}
#endif
static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
int hw_mode)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
hw_mode);
if (rc != ECORE_SUCCESS)
return rc;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
return ECORE_SUCCESS;
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
if (ECORE_IS_AH(p_hwfn->p_dev))
return ECORE_SUCCESS;
else if (ECORE_IS_BB(p_hwfn->p_dev))
ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
} else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
if (p_hwfn->p_dev->num_hwfns > 1) {
/* Activate OPTE in CMT */
u32 val;
val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
val |= 0x10;
ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
0x55555555);
}
ecore_emul_link_init(p_hwfn, p_ptt);
} else {
DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
}
#endif
return rc;
}
static enum _ecore_status_t
ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
@ -1623,7 +1575,7 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
u32 db_bar_size, n_cpus;
u32 roce_edpm_mode;
u32 pf_dems_shift;
int rc = ECORE_SUCCESS;
enum _ecore_status_t rc = ECORE_SUCCESS;
u8 cond;
db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
@ -1678,8 +1630,9 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
}
cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
(roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
cond = ((rc != ECORE_SUCCESS) &&
(roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
(roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
if (cond || p_hwfn->dcbx_no_edpm) {
/* Either EDPM is disabled from user configuration, or it is
* disabled via DCBx, or it is not mandatory and we failed to
@ -1703,7 +1656,7 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
"disabled" : "enabled");
/* Check return codes from above calls */
if (rc) {
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn,
"Failed to allocate enough DPIs\n");
return ECORE_NORESOURCES;
@ -1721,6 +1674,54 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
int hw_mode)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
hw_mode);
if (rc != ECORE_SUCCESS)
return rc;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
return ECORE_SUCCESS;
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
if (ECORE_IS_AH(p_hwfn->p_dev))
return ECORE_SUCCESS;
else if (ECORE_IS_BB(p_hwfn->p_dev))
ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
} else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
if (p_hwfn->p_dev->num_hwfns > 1) {
/* Activate OPTE in CMT */
u32 val;
val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
val |= 0x10;
ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
0x55555555);
}
ecore_emul_link_init(p_hwfn, p_ptt);
} else {
DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
}
#endif
return rc;
}
static enum _ecore_status_t
ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
@ -1922,8 +1923,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
{
struct ecore_load_req_params load_req_params;
u32 load_code, param, drv_mb_param;
struct ecore_hwfn *p_hwfn;
bool b_default_mtu = true;
struct ecore_hwfn *p_hwfn;
enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
int i;

12
drivers/net/qede/base/ecore_l2.c
View File

@ -946,17 +946,17 @@ ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn,
dma_addr_t bd_chain_phys_addr,
dma_addr_t cqe_pbl_addr,
u16 cqe_pbl_size,
void OSAL_IOMEM * *pp_producer)
void OSAL_IOMEM * *pp_prod)
{
u32 init_prod_val = 0;
*pp_producer = (u8 OSAL_IOMEM *)
p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
*pp_prod = (u8 OSAL_IOMEM *)
p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
__internal_ram_wr(p_hwfn, *pp_producer, sizeof(u32),
__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
(u32 *)(&init_prod_val));
return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid,

2
drivers/net/qede/base/ecore_vf.c
View File

@ -1285,8 +1285,8 @@ enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn)
struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
struct pfvf_def_resp_tlv *resp;
struct vfpf_first_tlv *req;
enum _ecore_status_t rc;
u32 size;
enum _ecore_status_t rc;
/* clear mailbox and prep first tlv */
req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));