net/i40e: support flow director on AVX Rx
This commit adds FDIR ID support to the AVX2 based receive path routine. Support for both 16B and 32B descriptors is implemented. Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Tested-by: Mesut Ali Ergin <mesut.a.ergin@intel.com>
This commit is contained in:
Harry van Haaren
Ferruh Yigit
parent
cc46d3d368
commit
7d087a0a8b
@ -137,9 +137,90 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq)
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I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
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}
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#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
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/* Handles 32B descriptor FDIR ID processing:
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* rxdp: receive descriptor ring, required to load 2nd 16B half of each desc
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* rx_pkts: required to store metadata back to mbufs
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* pkt_idx: offset into the burst, increments in vector widths
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* desc_idx: required to select the correct shift at compile time
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*/
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static inline __m256i
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desc_fdir_processing_32b(volatile union i40e_rx_desc *rxdp,
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struct rte_mbuf **rx_pkts,
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const uint32_t pkt_idx,
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const uint32_t desc_idx)
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{
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/* 32B desc path: load rxdp.wb.qword2 for EXT_STATUS and FLEXBH_STAT */
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__m128i *rxdp_desc_0 = (void *)(&rxdp[desc_idx + 0].wb.qword2);
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__m128i *rxdp_desc_1 = (void *)(&rxdp[desc_idx + 1].wb.qword2);
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const __m128i desc_qw2_0 = _mm_load_si128(rxdp_desc_0);
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const __m128i desc_qw2_1 = _mm_load_si128(rxdp_desc_1);
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/* Mask for FLEXBH_STAT, and the FDIR_ID value to compare against. The
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* remaining data is set to all 1's to pass through data.
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*/
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const __m256i flexbh_mask = _mm256_set_epi32(-1, -1, -1, 3 << 4,
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-1, -1, -1, 3 << 4);
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const __m256i flexbh_id = _mm256_set_epi32(-1, -1, -1, 1 << 4,
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-1, -1, -1, 1 << 4);
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/* Load descriptor, check for FLEXBH bits, generate a mask for both
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* packets in the register.
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*/
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__m256i desc_qw2_0_1 =
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_mm256_inserti128_si256(_mm256_castsi128_si256(desc_qw2_0),
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desc_qw2_1, 1);
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__m256i desc_tmp_msk = _mm256_and_si256(flexbh_mask, desc_qw2_0_1);
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__m256i fdir_mask = _mm256_cmpeq_epi32(flexbh_id, desc_tmp_msk);
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__m256i fdir_data = _mm256_alignr_epi8(desc_qw2_0_1, desc_qw2_0_1, 12);
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__m256i desc_fdir_data = _mm256_and_si256(fdir_mask, fdir_data);
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/* Write data out to the mbuf. There is no store to this area of the
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* mbuf today, so we cannot combine it with another store.
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*/
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const uint32_t idx_0 = pkt_idx + desc_idx;
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const uint32_t idx_1 = pkt_idx + desc_idx + 1;
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rx_pkts[idx_0]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 0);
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rx_pkts[idx_1]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 4);
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/* Create mbuf flags as required for mbuf_flags layout
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* (That's high lane [1,3,5,7, 0,2,4,6] as u32 lanes).
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* Approach:
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* - Mask away bits not required from the fdir_mask
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* - Leave the PKT_FDIR_ID bit (1 << 13)
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* - Position that bit correctly based on packet number
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* - OR in the resulting bit to mbuf_flags
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*/
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RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
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__m256i mbuf_flag_mask = _mm256_set_epi32(0, 0, 0, 1 << 13,
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0, 0, 0, 1 << 13);
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__m256i desc_flag_bit = _mm256_and_si256(mbuf_flag_mask, fdir_mask);
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/* For static-inline function, this will be stripped out
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* as the desc_idx is a hard-coded constant.
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*/
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switch (desc_idx) {
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case 0:
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return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 4);
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case 2:
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return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 8);
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case 4:
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return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 12);
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case 6:
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return desc_flag_bit;
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default:
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break;
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}
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/* NOT REACHED, see above switch returns */
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return _mm256_setzero_si256();
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}
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#endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
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#define PKTLEN_SHIFT 10
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static inline uint16_t
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/* Force inline as some compilers will not inline by default. */
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static __rte_always_inline uint16_t
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_recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts, uint8_t *split_packet)
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{
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@ -419,8 +500,10 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
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/* set vlan and rss flags */
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const __m256i vlan_flags = _mm256_shuffle_epi8(
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vlan_flags_shuf, flag_bits);
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const __m256i rss_flags = _mm256_shuffle_epi8(
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rss_flags_shuf, _mm256_srli_epi32(flag_bits, 11));
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const __m256i rss_fdir_bits = _mm256_srli_epi32(flag_bits, 11);
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const __m256i rss_flags = _mm256_shuffle_epi8(rss_flags_shuf,
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rss_fdir_bits);
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/*
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* l3_l4_error flags, shuffle, then shift to correct adjustment
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* of flags in flags_shuf, and finally mask out extra bits
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@ -431,8 +514,110 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
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l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
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/* merge flags */
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const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
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__m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
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_mm256_or_si256(rss_flags, vlan_flags));
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/* If the rxq has FDIR enabled, read and process the FDIR info
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* from the descriptor. This can cause more loads/stores, so is
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* not always performed. Branch over the code when not enabled.
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*/
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if (rxq->fdir_enabled) {
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#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
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/* 16B descriptor code path:
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* RSS and FDIR ID use the same offset in the desc, so
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* only one can be present at a time. The code below
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* identifies an FDIR ID match, and zeros the RSS value
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* in the mbuf on FDIR match to keep mbuf data clean.
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*/
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/* Flags:
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* - Take flags, shift bits to null out
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* - CMPEQ with known FDIR ID, to get 0xFFFF or 0 mask
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* - Strip bits from mask, leaving 0 or 1 for FDIR ID
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* - Merge with mbuf_flags
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*/
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/* FLM = 1, FLTSTAT = 0b01, (FLM | FLTSTAT) == 3.
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* Shift left by 28 to avoid having to mask.
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*/
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const __m256i fdir = _mm256_slli_epi32(rss_fdir_bits, 28);
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const __m256i fdir_id = _mm256_set1_epi32(3 << 28);
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/* As above, the fdir_mask to packet mapping is this:
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* order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
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* Then OR FDIR flags to mbuf_flags on FDIR ID hit.
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*/
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RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
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const __m256i pkt_fdir_bit = _mm256_set1_epi32(1 << 13);
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const __m256i fdir_mask = _mm256_cmpeq_epi32(fdir, fdir_id);
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__m256i fdir_bits = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
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mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_bits);
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/* Based on FDIR_MASK, clear the RSS or FDIR value.
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* The FDIR ID value is masked to zero if not a hit,
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* otherwise the mb0_1 register RSS field is zeroed.
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*/
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const __m256i fdir_zero_mask = _mm256_setzero_si256();
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const uint32_t fdir_blend_mask = (1 << 3) | (1 << 7);
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__m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,
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fdir_mask, fdir_blend_mask);
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__m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask);
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mb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1);
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/* Write to mbuf: no stores to combine with, so just a
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* scalar store to push data here.
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*/
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rx_pkts[i + 0]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb0_1, 3);
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rx_pkts[i + 1]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb0_1, 7);
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/* Same as above, only shift the fdir_mask to align
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* the packet FDIR mask with the FDIR_ID desc lane.
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*/
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__m256i tmp2_3 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 12);
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__m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3);
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tmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3,
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fdir_blend_mask);
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mb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3);
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rx_pkts[i + 2]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 3);
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rx_pkts[i + 3]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 7);
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__m256i tmp4_5 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 8);
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__m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5);
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tmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5,
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fdir_blend_mask);
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mb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5);
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rx_pkts[i + 4]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 3);
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rx_pkts[i + 5]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 7);
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__m256i tmp6_7 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 4);
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__m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7);
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tmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7,
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fdir_blend_mask);
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mb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7);
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rx_pkts[i + 6]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 3);
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rx_pkts[i + 7]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 7);
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/* End of 16B descriptor handling */
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#else
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/* 32B descriptor FDIR ID mark handling. Returns bits
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* to be OR-ed into the mbuf olflags.
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*/
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__m256i fdir_add_flags;
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fdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 0);
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mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);
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fdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 2);
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mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);
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fdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 4);
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mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);
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fdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 6);
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mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);
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/* End 32B desc handling */
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#endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
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} /* if() on FDIR enabled */
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/*
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* At this point, we have the 8 sets of flags in the low 16-bits
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* of each 32-bit value in vlan0.
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