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net/igb: implement descriptor status API

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Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Olivier Matz 2017-03-29 10:36:30 +02:00 committed by Thomas Monjalon
parent 8cd01eb049
commit 7d499cb15e
5 changed files with 54 additions and 0 deletions
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2
doc/guides/nics/features/igb.ini
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@ -33,6 +33,8 @@ L3 checksum offload = Y
L4 checksum offload = Y L4 checksum offload = Y
Packet type parsing = Y Packet type parsing = Y
Timesync = Y Timesync = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
FW version = Y FW version = Y

2
doc/guides/nics/features/igb_vf.ini
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@ -17,6 +17,8 @@ QinQ offload = Y
L3 checksum offload = Y L3 checksum offload = Y
L4 checksum offload = Y L4 checksum offload = Y
Packet type parsing = Y Packet type parsing = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
Registers dump = Y Registers dump = Y

3
drivers/net/e1000/e1000_ethdev.h
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@ -311,6 +311,9 @@ uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev,
int eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset); int eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset);
int eth_igb_rx_descriptor_status(void *rx_queue, uint16_t offset);
int eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset);
int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
uint16_t nb_tx_desc, unsigned int socket_id, uint16_t nb_tx_desc, unsigned int socket_id,
const struct rte_eth_txconf *tx_conf); const struct rte_eth_txconf *tx_conf);

2
drivers/net/e1000/igb_ethdev.c
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@ -406,6 +406,8 @@ static const struct eth_dev_ops eth_igb_ops = {
.rx_queue_release = eth_igb_rx_queue_release, .rx_queue_release = eth_igb_rx_queue_release,
.rx_queue_count = eth_igb_rx_queue_count, .rx_queue_count = eth_igb_rx_queue_count,
.rx_descriptor_done = eth_igb_rx_descriptor_done, .rx_descriptor_done = eth_igb_rx_descriptor_done,
.rx_descriptor_status = eth_igb_rx_descriptor_status,
.tx_descriptor_status = eth_igb_tx_descriptor_status,
.tx_queue_setup = eth_igb_tx_queue_setup, .tx_queue_setup = eth_igb_tx_queue_setup,
.tx_queue_release = eth_igb_tx_queue_release, .tx_queue_release = eth_igb_tx_queue_release,
.tx_done_cleanup = eth_igb_tx_done_cleanup, .tx_done_cleanup = eth_igb_tx_done_cleanup,

45
drivers/net/e1000/igb_rxtx.c
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@ -1727,6 +1727,51 @@ eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD); return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
} }
int
eth_igb_rx_descriptor_status(void *rx_queue, uint16_t offset)
{
struct igb_rx_queue *rxq = rx_queue;
volatile uint32_t *status;
uint32_t desc;
if (unlikely(offset >= rxq->nb_rx_desc))
return -EINVAL;
if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
return RTE_ETH_RX_DESC_UNAVAIL;
desc = rxq->rx_tail + offset;
if (desc >= rxq->nb_rx_desc)
desc -= rxq->nb_rx_desc;
status = &rxq->rx_ring[desc].wb.upper.status_error;
if (*status & rte_cpu_to_le_32(E1000_RXD_STAT_DD))
return RTE_ETH_RX_DESC_DONE;
return RTE_ETH_RX_DESC_AVAIL;
}
int
eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset)
{
struct igb_tx_queue *txq = tx_queue;
volatile uint32_t *status;
uint32_t desc;
if (unlikely(offset >= txq->nb_tx_desc))
return -EINVAL;
desc = txq->tx_tail + offset;
if (desc >= txq->nb_tx_desc)
desc -= txq->nb_tx_desc;
status = &txq->tx_ring[desc].wb.status;
if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD))
return RTE_ETH_TX_DESC_DONE;
return RTE_ETH_TX_DESC_FULL;
}
void void
igb_dev_clear_queues(struct rte_eth_dev *dev) igb_dev_clear_queues(struct rte_eth_dev *dev)
{ {