net/sfc/base: update hardware headers for Medford2
The changes to efx_regs_ef10.h are auto-generated and include: - Updated event RX_L4_CLASS which is now 2 bits (was 3). The encoding of TCP, UDP and UNKNOWN are unchanged so the narrower Medford2 field definition is compatible with all controllers. - Fix definition of FATSOv2 option descriptors. These were added manually and differ from the auto-generated values in some fields (not yet used in common code). The field definitions have been corrected to agree with the Linux net driver headers and SF-108452-SW. The remaining changes adapt the common code to use the updated headers. Signed-off-by: Andy Moreton <amoreton@solarflare.com> Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Andy Moreton
Ferruh Yigit
parent
0ecf255632
commit
7e48cfe9ef
@ -868,12 +868,23 @@ ef10_ev_rx(
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#endif
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size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
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cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
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next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
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eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
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mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
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l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
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l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
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cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
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/*
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* RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
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* 2 bits wide on Medford2. Check it is safe to use the Medford2 field
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* and values for all EF10 controllers.
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*/
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EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
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l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
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if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
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/* Drop this event */
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@ -952,10 +963,22 @@ ef10_ev_rx(
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flags |= EFX_CKSUM_IPV4;
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}
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if (l4_class == ESE_DZ_L4_CLASS_TCP) {
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/*
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* RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
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* only 2 bits wide on Medford2. Check it is safe to use the
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* Medford2 field and values for all EF10 controllers.
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*/
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EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
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ESF_DE_RX_L4_CLASS_LBN);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
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ESE_DE_L4_CLASS_UNKNOWN);
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if (l4_class == ESE_FZ_L4_CLASS_TCP) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
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flags |= EFX_PKT_TCP;
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} else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
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} else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
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flags |= EFX_PKT_UDP;
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} else {
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@ -967,10 +990,22 @@ ef10_ev_rx(
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case ESE_DZ_L3_CLASS_IP6_FRAG:
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flags |= EFX_PKT_IPV6;
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if (l4_class == ESE_DZ_L4_CLASS_TCP) {
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/*
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* RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
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* only 2 bits wide on Medford2. Check it is safe to use the
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* Medford2 field and values for all EF10 controllers.
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*/
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EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
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ESF_DE_RX_L4_CLASS_LBN);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
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EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
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ESE_DE_L4_CLASS_UNKNOWN);
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if (l4_class == ESE_FZ_L4_CLASS_TCP) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
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flags |= EFX_PKT_TCP;
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} else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
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} else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
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flags |= EFX_PKT_UDP;
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} else {
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@ -24,7 +24,7 @@ extern "C" {
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*/
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#define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
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@ -38,7 +38,7 @@ extern "C" {
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*/
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#define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
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#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
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#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
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@ -54,7 +54,7 @@ extern "C" {
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*/
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#define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0
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@ -68,7 +68,7 @@ extern "C" {
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*/
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#define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0
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@ -82,7 +82,7 @@ extern "C" {
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*/
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#define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0
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@ -96,7 +96,7 @@ extern "C" {
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*/
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#define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_EVQ_RPTR_REG_STEP 8192
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#define ER_DZ_EVQ_RPTR_REG_ROWS 2048
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#define ER_DZ_EVQ_RPTR_REG_RESET 0x0
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@ -108,13 +108,85 @@ extern "C" {
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#define ERF_DZ_EVQ_RPTR_WIDTH 15
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/*
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* EVQ_RPTR_REG_64K(32bit):
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*
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*/
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#define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536
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#define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048
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#define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0
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#define ERF_FZ_EVQ_RPTR_VLD_LBN 15
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#define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1
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#define ERF_FZ_EVQ_RPTR_LBN 0
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#define ERF_FZ_EVQ_RPTR_WIDTH 15
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/*
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* EVQ_RPTR_REG_16K(32bit):
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*
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*/
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#define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384
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#define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048
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#define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0
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/* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */
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/* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */
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/* defined as ERF_FZ_EVQ_RPTR_LBN 0; */
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/* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */
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/*
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* EVQ_TMR_REG_64K(32bit):
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*
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*/
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#define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_EVQ_TMR_REG_64K_STEP 65536
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#define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048
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#define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
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#define ERF_FZ_TC_TIMER_MODE_LBN 14
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#define ERF_FZ_TC_TIMER_MODE_WIDTH 2
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#define ERF_FZ_TC_TIMER_VAL_LBN 0
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#define ERF_FZ_TC_TIMER_VAL_WIDTH 14
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/*
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* EVQ_TMR_REG_16K(32bit):
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*
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*/
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#define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_EVQ_TMR_REG_16K_STEP 16384
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#define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048
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#define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
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/* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
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/* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */
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/* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
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/* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */
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/*
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* EVQ_TMR_REG(32bit):
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*
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*/
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#define ER_DZ_EVQ_TMR_REG_OFST 0x00000420
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_EVQ_TMR_REG_STEP 8192
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#define ER_DZ_EVQ_TMR_REG_ROWS 2048
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#define ER_DZ_EVQ_TMR_REG_RESET 0x0
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@ -126,13 +198,29 @@ extern "C" {
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#define ERF_DZ_TC_TIMER_VAL_WIDTH 14
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/*
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* RX_DESC_UPD_REG_16K(32bit):
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*
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*/
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#define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384
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#define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048
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#define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0
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#define ERF_FZ_RX_DESC_WPTR_LBN 0
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#define ERF_FZ_RX_DESC_WPTR_WIDTH 12
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/*
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* RX_DESC_UPD_REG(32bit):
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*
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*/
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#define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_RX_DESC_UPD_REG_STEP 8192
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#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048
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#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0
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@ -141,13 +229,74 @@ extern "C" {
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#define ERF_DZ_RX_DESC_WPTR_LBN 0
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#define ERF_DZ_RX_DESC_WPTR_WIDTH 12
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/*
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* RX_DESC_UPD_REG_64K(32bit):
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*
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*/
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#define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536
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#define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048
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#define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0
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/* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */
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/* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */
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/*
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* TX_DESC_UPD_REG_64K(96bit):
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*
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*/
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#define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536
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#define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048
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#define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0
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#define ERF_FZ_RSVD_LBN 76
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#define ERF_FZ_RSVD_WIDTH 20
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#define ERF_FZ_TX_DESC_WPTR_LBN 64
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#define ERF_FZ_TX_DESC_WPTR_WIDTH 12
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#define ERF_FZ_TX_DESC_HWORD_LBN 32
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#define ERF_FZ_TX_DESC_HWORD_WIDTH 32
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#define ERF_FZ_TX_DESC_LWORD_LBN 0
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#define ERF_FZ_TX_DESC_LWORD_WIDTH 32
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/*
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* TX_DESC_UPD_REG_16K(96bit):
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*
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*/
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#define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10
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/* medford2a0=pf_dbell_bar */
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#define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384
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#define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048
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#define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0
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/* defined as ERF_FZ_RSVD_LBN 76; */
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/* defined as ERF_FZ_RSVD_WIDTH 20 */
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/* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */
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/* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */
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/* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */
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/* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */
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/* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */
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/* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */
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/*
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* TX_DESC_UPD_REG(96bit):
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*
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*/
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#define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
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/* hunta0,medforda0=pcie_pf_bar2 */
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/* hunta0,medforda0,medford2a0=pf_dbell_bar */
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#define ER_DZ_TX_DESC_UPD_REG_STEP 8192
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#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048
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#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0
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@ -233,16 +382,24 @@ extern "C" {
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#define ESF_DZ_RX_EV_SOFT2_WIDTH 2
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#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
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#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
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#define ESF_DZ_RX_L4_CLASS_LBN 45
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#define ESF_DZ_RX_L4_CLASS_WIDTH 3
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#define ESE_DZ_L4_CLASS_RSVD7 7
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#define ESE_DZ_L4_CLASS_RSVD6 6
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#define ESE_DZ_L4_CLASS_RSVD5 5
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#define ESE_DZ_L4_CLASS_RSVD4 4
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#define ESE_DZ_L4_CLASS_RSVD3 3
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#define ESE_DZ_L4_CLASS_UDP 2
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#define ESE_DZ_L4_CLASS_TCP 1
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#define ESE_DZ_L4_CLASS_UNKNOWN 0
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#define ESF_DE_RX_L4_CLASS_LBN 45
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#define ESF_DE_RX_L4_CLASS_WIDTH 3
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#define ESE_DE_L4_CLASS_RSVD7 7
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#define ESE_DE_L4_CLASS_RSVD6 6
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#define ESE_DE_L4_CLASS_RSVD5 5
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#define ESE_DE_L4_CLASS_RSVD4 4
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#define ESE_DE_L4_CLASS_RSVD3 3
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#define ESE_DE_L4_CLASS_UDP 2
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#define ESE_DE_L4_CLASS_TCP 1
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#define ESE_DE_L4_CLASS_UNKNOWN 0
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#define ESF_FZ_RX_FASTPD_INDCTR_LBN 47
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#define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1
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#define ESF_FZ_RX_L4_CLASS_LBN 45
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#define ESF_FZ_RX_L4_CLASS_WIDTH 2
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#define ESE_FZ_L4_CLASS_RSVD3 3
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#define ESE_FZ_L4_CLASS_UDP 2
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#define ESE_FZ_L4_CLASS_TCP 1
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#define ESE_FZ_L4_CLASS_UNKNOWN 0
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#define ESF_DZ_RX_L3_CLASS_LBN 42
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#define ESF_DZ_RX_L3_CLASS_WIDTH 3
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#define ESE_DZ_L3_CLASS_RSVD7 7
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@ -419,6 +576,8 @@ extern "C" {
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#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
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#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
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#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
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#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
|
||||
#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
|
||||
@ -429,7 +588,7 @@ extern "C" {
|
||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
|
||||
|
||||
|
||||
/* TX_TSO_FATSO2A_DESC */
|
||||
/* ES_TX_TSO_V2_DESC_A */
|
||||
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
|
||||
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
|
||||
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
|
||||
@ -449,7 +608,7 @@ extern "C" {
|
||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
|
||||
|
||||
|
||||
/* TX_TSO_FATSO2B_DESC */
|
||||
/* ES_TX_TSO_V2_DESC_B */
|
||||
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
|
||||
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
|
||||
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
|
||||
@ -463,12 +622,10 @@ extern "C" {
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
|
||||
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
|
||||
#define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16
|
||||
#define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16
|
||||
#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32
|
||||
#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
|
||||
#define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0
|
||||
#define ESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16
|
||||
#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
|
||||
#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
|
||||
|
||||
|
||||
/* ES_TX_VLAN_DESC */
|
||||
|
||||
@ -325,22 +325,32 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,
|
||||
SFC_ASSERT(false);
|
||||
}
|
||||
|
||||
switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L4_CLASS)) {
|
||||
case ESE_DZ_L4_CLASS_TCP:
|
||||
/*
|
||||
* RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
|
||||
* 2 bits wide on Medford2. Check it is safe to use the Medford2 field
|
||||
* and values for all EF10 controllers.
|
||||
*/
|
||||
RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
|
||||
switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
|
||||
case ESE_FZ_L4_CLASS_TCP:
|
||||
RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
|
||||
l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
|
||||
RTE_PTYPE_INNER_L4_TCP;
|
||||
ol_flags |=
|
||||
(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
|
||||
PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
|
||||
break;
|
||||
case ESE_DZ_L4_CLASS_UDP:
|
||||
case ESE_FZ_L4_CLASS_UDP:
|
||||
RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
|
||||
l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
|
||||
RTE_PTYPE_INNER_L4_UDP;
|
||||
ol_flags |=
|
||||
(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
|
||||
PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
|
||||
break;
|
||||
case ESE_DZ_L4_CLASS_UNKNOWN:
|
||||
case ESE_FZ_L4_CLASS_UNKNOWN:
|
||||
RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
|
||||
ESE_DE_L4_CLASS_UNKNOWN);
|
||||
break;
|
||||
default:
|
||||
/* Unexpected Layer 4 class */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user