net/hns3: add simple Tx path
This patch adds simple Tx process function. When multiple segment packets are not needed, Which means that DEV_TX_OFFLOAD_MBUF_FAST_FREE offload is not set, we can simple Tx process. Signed-off-by: Huisong Li <lihuisong@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
This commit is contained in:
Wei Hu (Xavier)
Ferruh Yigit
parent
521ab3e933
commit
7ef933908f
@ -2352,6 +2352,7 @@ hns3_dev_configure(struct rte_eth_dev *dev)
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goto cfg_err;
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hns->rx_simple_allowed = true;
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hns->tx_simple_allowed = true;
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hns3_init_rx_ptype_tble(dev);
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hw->adapter_state = HNS3_NIC_CONFIGURED;
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@ -2511,6 +2512,10 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
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.rx_drop_en = 1,
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.offloads = 0,
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};
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info->default_txconf = (struct rte_eth_txconf) {
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.tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
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.offloads = 0,
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};
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info->vmdq_queue_num = 0;
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@ -5544,6 +5549,7 @@ static const struct eth_dev_ops hns3_eth_dev_ops = {
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.rxq_info_get = hns3_rxq_info_get,
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.txq_info_get = hns3_txq_info_get,
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.rx_burst_mode_get = hns3_rx_burst_mode_get,
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.tx_burst_mode_get = hns3_tx_burst_mode_get,
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.flow_ctrl_get = hns3_flow_ctrl_get,
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.flow_ctrl_set = hns3_flow_ctrl_set,
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.priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
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@ -643,6 +643,7 @@ struct hns3_adapter {
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};
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bool rx_simple_allowed;
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bool tx_simple_allowed;
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struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
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};
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@ -822,6 +822,7 @@ hns3vf_dev_configure(struct rte_eth_dev *dev)
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goto cfg_err;
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hns->rx_simple_allowed = true;
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hns->tx_simple_allowed = true;
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hns3_init_rx_ptype_tble(dev);
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hw->adapter_state = HNS3_NIC_CONFIGURED;
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@ -956,6 +957,10 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
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.rx_drop_en = 1,
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.offloads = 0,
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};
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info->default_txconf = (struct rte_eth_txconf) {
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.tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
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.offloads = 0,
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};
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info->vmdq_queue_num = 0;
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@ -2540,6 +2545,7 @@ static const struct eth_dev_ops hns3vf_eth_dev_ops = {
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.rxq_info_get = hns3_rxq_info_get,
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.txq_info_get = hns3_txq_info_get,
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.rx_burst_mode_get = hns3_rx_burst_mode_get,
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.tx_burst_mode_get = hns3_tx_burst_mode_get,
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.mac_addr_add = hns3vf_add_mac_addr,
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.mac_addr_remove = hns3vf_remove_mac_addr,
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.mac_addr_set = hns3vf_set_default_mac_addr,
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@ -1952,27 +1952,72 @@ hns3_get_rx_function(struct rte_eth_dev *dev)
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return hns3_recv_scattered_pkts;
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}
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static int
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hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
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uint16_t nb_desc, uint16_t *tx_rs_thresh,
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uint16_t *tx_free_thresh, uint16_t idx)
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{
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#define HNS3_TX_RS_FREE_THRESH_GAP 8
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uint16_t rs_thresh, free_thresh, fast_free_thresh;
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if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
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nb_desc % HNS3_ALIGN_RING_DESC) {
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hns3_err(hw, "number (%u) of tx descriptors is invalid",
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nb_desc);
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return -EINVAL;
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}
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rs_thresh = (conf->tx_rs_thresh > 0) ?
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conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
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free_thresh = (conf->tx_free_thresh > 0) ?
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conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
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if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
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rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
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free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
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hns3_err(hw, "tx_rs_thresh (%d) tx_free_thresh (%d) nb_desc "
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"(%d) of tx descriptors for port=%d queue=%d check "
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"fail!",
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rs_thresh, free_thresh, nb_desc, hw->data->port_id,
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idx);
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return -EINVAL;
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}
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if (conf->tx_free_thresh == 0) {
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/* Fast free Tx memory buffer to improve cache hit rate */
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fast_free_thresh = nb_desc - rs_thresh;
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if (fast_free_thresh >=
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HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
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free_thresh = fast_free_thresh -
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HNS3_TX_FAST_FREE_AHEAD;
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}
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*tx_rs_thresh = rs_thresh;
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*tx_free_thresh = free_thresh;
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return 0;
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}
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int
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hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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unsigned int socket_id, const struct rte_eth_txconf *conf)
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{
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struct hns3_adapter *hns = dev->data->dev_private;
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uint16_t tx_rs_thresh, tx_free_thresh;
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struct hns3_hw *hw = &hns->hw;
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struct hns3_queue_info q_info;
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struct hns3_tx_queue *txq;
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int tx_entry_len;
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int ret;
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if (dev->data->dev_started) {
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hns3_err(hw, "tx_queue_setup after dev_start no supported");
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return -EINVAL;
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}
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if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
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nb_desc % HNS3_ALIGN_RING_DESC) {
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hns3_err(hw, "Number (%u) of tx descriptors is invalid",
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nb_desc);
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return -EINVAL;
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}
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ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
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&tx_rs_thresh, &tx_free_thresh, idx);
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if (ret)
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return ret;
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if (dev->data->tx_queues[idx] != NULL) {
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hns3_tx_queue_release(dev->data->tx_queues[idx]);
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@ -2005,11 +2050,15 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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txq->next_to_use = 0;
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txq->next_to_clean = 0;
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txq->tx_bd_ready = txq->nb_tx_desc - 1;
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txq->tx_free_thresh = tx_free_thresh;
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txq->tx_rs_thresh = tx_rs_thresh;
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txq->port_id = dev->data->port_id;
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txq->pvid_state = hw->port_base_vlan_cfg.state;
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txq->configured = true;
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txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
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idx * HNS3_TQP_REG_SIZE);
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txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
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HNS3_RING_TX_TAIL_REG);
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txq->min_tx_pkt_len = hw->min_tx_pkt_len;
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txq->over_length_pkt_cnt = 0;
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txq->exceed_limit_bd_pkt_cnt = 0;
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@ -2024,12 +2073,6 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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return 0;
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}
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static inline void
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hns3_queue_xmit(struct hns3_tx_queue *txq, uint32_t buf_num)
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{
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hns3_write_dev(txq, HNS3_RING_TX_TAIL_REG, buf_num);
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}
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static void
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hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
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{
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@ -2798,6 +2841,154 @@ hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
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return 0;
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}
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static inline void
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hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
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{
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struct hns3_entry *tx_entry;
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struct hns3_desc *desc;
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uint16_t tx_next_clean;
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int i;
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while (1) {
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if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
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break;
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/*
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* All mbufs can be released only when the VLD bits of all
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* descriptors in a batch are cleared.
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*/
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tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
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txq->nb_tx_desc;
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desc = &txq->tx_ring[tx_next_clean];
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for (i = 0; i < txq->tx_rs_thresh; i++) {
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if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
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BIT(HNS3_TXD_VLD_B))
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return;
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desc--;
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}
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tx_entry = &txq->sw_ring[txq->next_to_clean];
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for (i = 0; i < txq->tx_rs_thresh; i++)
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rte_prefetch0((tx_entry + i)->mbuf);
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for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
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rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
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tx_entry->mbuf = NULL;
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}
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txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
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txq->tx_bd_ready += txq->tx_rs_thresh;
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}
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}
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static inline void
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hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
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{
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tx_entry->mbuf = pkts[0];
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}
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static inline void
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hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
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{
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hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
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hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
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hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
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hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
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}
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static inline void
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hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
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{
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#define PER_LOOP_NUM 4
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const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
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uint64_t dma_addr;
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uint32_t i;
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for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
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dma_addr = rte_mbuf_data_iova(*pkts);
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txdp->addr = rte_cpu_to_le_64(dma_addr);
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txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
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txdp->tx.paylen = 0;
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txdp->tx.type_cs_vlan_tso_len = 0;
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txdp->tx.ol_type_vlan_len_msec = 0;
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txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
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}
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}
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static inline void
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hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
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{
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const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
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uint64_t dma_addr;
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dma_addr = rte_mbuf_data_iova(*pkts);
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txdp->addr = rte_cpu_to_le_64(dma_addr);
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txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
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txdp->tx.paylen = 0;
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txdp->tx.type_cs_vlan_tso_len = 0;
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txdp->tx.ol_type_vlan_len_msec = 0;
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txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
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}
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static inline void
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hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
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struct rte_mbuf **pkts,
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uint16_t nb_pkts)
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{
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#define PER_LOOP_NUM 4
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#define PER_LOOP_MASK (PER_LOOP_NUM - 1)
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struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
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struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
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const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
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const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
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uint32_t i;
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for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
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hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
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hns3_tx_setup_4bd(txdp + i, pkts + i);
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}
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if (unlikely(leftover > 0)) {
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for (i = 0; i < leftover; i++) {
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hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
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pkts + mainpart + i);
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hns3_tx_setup_1bd(txdp + mainpart + i,
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pkts + mainpart + i);
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}
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}
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}
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uint16_t
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hns3_xmit_pkts_simple(void *tx_queue,
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struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts)
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{
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struct hns3_tx_queue *txq = tx_queue;
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uint16_t nb_tx = 0;
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hns3_tx_free_buffer_simple(txq);
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nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
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if (unlikely(nb_pkts == 0)) {
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if (txq->tx_bd_ready == 0)
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txq->queue_full_cnt++;
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return 0;
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}
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txq->tx_bd_ready -= nb_pkts;
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if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
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nb_tx = txq->nb_tx_desc - txq->next_to_use;
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hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
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txq->next_to_use = 0;
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}
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hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
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txq->next_to_use += nb_pkts - nb_tx;
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hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
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return nb_pkts;
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}
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uint16_t
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hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
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{
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@ -2909,11 +3100,47 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
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end_of_tx:
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if (likely(nb_tx))
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hns3_queue_xmit(txq, nb_hold);
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hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
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return nb_tx;
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}
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int
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hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
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struct rte_eth_burst_mode *mode)
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{
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eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
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const char *info = NULL;
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if (pkt_burst == hns3_xmit_pkts_simple)
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info = "Scalar Simple";
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else if (pkt_burst == hns3_xmit_pkts)
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info = "Scalar";
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if (info == NULL)
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return -EINVAL;
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snprintf(mode->info, sizeof(mode->info), "%s", info);
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return 0;
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}
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static eth_tx_burst_t
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hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
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{
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uint64_t offloads = dev->data->dev_conf.txmode.offloads;
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struct hns3_adapter *hns = dev->data->dev_private;
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if (hns->tx_simple_allowed &&
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offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) {
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*prep = NULL;
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return hns3_xmit_pkts_simple;
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}
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*prep = hns3_prep_pkts;
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return hns3_xmit_pkts;
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}
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static uint16_t
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hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
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struct rte_mbuf **pkts __rte_unused,
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@ -2925,12 +3152,13 @@ hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
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void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
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{
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struct hns3_adapter *hns = eth_dev->data->dev_private;
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eth_tx_prep_t prep = NULL;
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if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
|
||||
rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
|
||||
eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
|
||||
eth_dev->tx_pkt_burst = hns3_xmit_pkts;
|
||||
eth_dev->tx_pkt_prepare = hns3_prep_pkts;
|
||||
eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
|
||||
eth_dev->tx_pkt_prepare = prep;
|
||||
} else {
|
||||
eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
|
||||
eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
|
||||
@ -2966,5 +3194,7 @@ hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
|
||||
|
||||
qinfo->nb_desc = txq->nb_tx_desc;
|
||||
qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
|
||||
qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
|
||||
qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
|
||||
qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
|
||||
}
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
#define HNS3_BULK_ALLOC_MBUF_NUM 32
|
||||
|
||||
#define HNS3_DEFAULT_RX_FREE_THRESH 32
|
||||
#define HNS3_DEFAULT_TX_FREE_THRESH 32
|
||||
#define HNS3_DEFAULT_TX_RS_THRESH 32
|
||||
#define HNS3_TX_FAST_FREE_AHEAD 64
|
||||
|
||||
#define HNS3_512_BD_BUF_SIZE 512
|
||||
#define HNS3_1K_BD_BUF_SIZE 1024
|
||||
@ -282,6 +285,7 @@ struct hns3_rx_queue {
|
||||
|
||||
struct hns3_tx_queue {
|
||||
void *io_base;
|
||||
volatile void *io_tail_reg;
|
||||
struct hns3_adapter *hns;
|
||||
struct hns3_desc *tx_ring;
|
||||
uint64_t tx_ring_phys_addr; /* TX ring DMA address */
|
||||
@ -291,10 +295,32 @@ struct hns3_tx_queue {
|
||||
uint16_t queue_id;
|
||||
uint16_t port_id;
|
||||
uint16_t nb_tx_desc;
|
||||
/*
|
||||
* index of next BD whose corresponding rte_mbuf can be released by
|
||||
* driver.
|
||||
*/
|
||||
uint16_t next_to_clean;
|
||||
/* index of next BD to be filled by driver to send packet */
|
||||
uint16_t next_to_use;
|
||||
/* num of remaining BDs ready to be filled by driver to send packet */
|
||||
uint16_t tx_bd_ready;
|
||||
|
||||
/* threshold for free tx buffer if available BDs less than this value */
|
||||
uint16_t tx_free_thresh;
|
||||
|
||||
/*
|
||||
* For better performance in tx datapath, releasing mbuf in batches is
|
||||
* required.
|
||||
* Only checking the VLD bit of the last descriptor in a batch of the
|
||||
* thresh descriptors does not mean that these descriptors are all sent
|
||||
* by hardware successfully. So we need to check that the VLD bits of
|
||||
* all descriptors are cleared. and then free all mbufs in the batch.
|
||||
* - tx_rs_thresh
|
||||
* Number of mbufs released at a time.
|
||||
|
||||
*/
|
||||
uint16_t tx_rs_thresh;
|
||||
|
||||
/*
|
||||
* port based vlan configuration state.
|
||||
* value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
|
||||
@ -360,6 +386,9 @@ struct hns3_tx_queue {
|
||||
uint64_t pkt_padding_fail_cnt;
|
||||
};
|
||||
|
||||
#define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
|
||||
((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
|
||||
|
||||
struct hns3_queue_info {
|
||||
const char *type; /* point to queue memory name */
|
||||
const char *ring_name; /* point to hardware ring name */
|
||||
@ -525,8 +554,13 @@ int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
|
||||
struct rte_eth_burst_mode *mode);
|
||||
uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
|
||||
__rte_unused uint16_t queue_id,
|
||||
struct rte_eth_burst_mode *mode);
|
||||
const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
||||
void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
|
||||
void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user