examples/ip_pipeline: add sample configurations and scripts
This patch includes the configuration and script files of the some applications which can be built using DPDK Packet Framework. A configuration file defines the application structure which include packet processing stages (knowns as pipelines), their connectivity and other parameters necessary to start and run the application. A script file specifies CLI commands required for loading table entries (rules/routes, etc). The configuration/script files for simple applications such as l2 forwarding, l3 forwarding have been presented. In addition, to demonstrate the use and inter-connectivity of various pipeline modules (which are avilable in packet framework), a complex packet processing workload i.e. edge router is considered. The configuration of the pipeline stages used for upstream and downstream flow processing has been specified separately in two configuration files. All these configuration and script files don't affect the compilation. Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com> Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
This commit is contained in:
Jasvinder Singh
Thomas Monjalon
parent
1d63c314b7
commit
7f837dcc8f
85
examples/ip_pipeline/config/edge_router_downstream.cfg
Normal file
85
examples/ip_pipeline/config/edge_router_downstream.cfg
Normal file
@ -0,0 +1,85 @@
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; BSD LICENSE
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;
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; Copyright(c) 2015 Intel Corporation. All rights reserved.
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
|
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; modification, are permitted provided that the following conditions
|
||||
; are met:
|
||||
;
|
||||
; * Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; * Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
||||
; distribution.
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||||
; * Neither the name of Intel Corporation nor the names of its
|
||||
; contributors may be used to endorse or promote products derived
|
||||
; from this software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; An edge router typically sits between two networks such as the provider
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; core network and the provider access network. A typical packet processing
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; pipeline for the downstream traffic (i.e. traffic from core to access
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; network) contains the following functional blocks: Packet RX & Routing,
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; Traffic management and Packet TX. The input packets are assumed to be
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; IPv4, while the output packets are Q-in-Q IPv4.
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; A simple implementation for this functional pipeline is presented below.
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; Packet Rx & Traffic Management Packet Tx
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; Routing (Pass-Through) (Pass-Through)
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; _____________________ SWQ0 ______________________ SWQ4 _____________________
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; RXQ0.0 --->| |----->| |----->| |---> TXQ0.0
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; | | SWQ1 | | SWQ5 | |
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; RXQ1.0 --->| |----->| |----->| |---> TXQ1.0
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; | (P1) | SWQ2 | (P2) | SWQ6 | (P3) |
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; RXQ2.0 --->| |----->| |----->| |---> TXQ2.0
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; | | SWQ3 | | SWQ7 | |
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; RXQ3.0 --->| |----->| |----->| |---> TXQ3.0
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; |_____________________| |______________________| |_____________________|
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; | _|_ ^ _|_ ^ _|_ ^ _|_ ^
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; | |___|||___|||___|||___||
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; +--> SINK0 |___|||___|||___|||___||
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; (route miss) |__| |__| |__| |__|
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; TM0 TM1 TM2 TM3
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[PIPELINE0]
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type = MASTER
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core = 0
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[PIPELINE1]
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type = ROUTING
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core = 1
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pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
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pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
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encap = ethernet_qinq
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qinq_sched = test
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ip_hdr_offset = 270; mbuf (128) + headroom (128) + ethernet header (14) = 270
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[PIPELINE2]
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type = PASS-THROUGH
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core = 2
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pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
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pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7
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[PIPELINE3]
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type = PASS-THROUGH
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core = 3
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pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
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pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
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[MEMPOOL0]
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pool_size = 2M
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10
examples/ip_pipeline/config/edge_router_downstream.sh
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10
examples/ip_pipeline/config/edge_router_downstream.sh
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@ -0,0 +1,10 @@
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################################################################################
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# Routing: Ether QinQ, ARP off
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################################################################################
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p 1 route add default 4 #SINK0
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p 1 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0 qinq 256 257
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p 1 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1 qinq 258 259
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p 1 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2 qinq 260 261
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p 1 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3 qinq 262 263
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p 1 route ls
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110
examples/ip_pipeline/config/edge_router_upstream.cfg
Normal file
110
examples/ip_pipeline/config/edge_router_upstream.cfg
Normal file
@ -0,0 +1,110 @@
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; BSD LICENSE
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;
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; Copyright(c) 2015 Intel Corporation. All rights reserved.
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; All rights reserved.
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;
|
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; Redistribution and use in source and binary forms, with or without
|
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; modification, are permitted provided that the following conditions
|
||||
; are met:
|
||||
;
|
||||
; * Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; * Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
||||
; distribution.
|
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; * Neither the name of Intel Corporation nor the names of its
|
||||
; contributors may be used to endorse or promote products derived
|
||||
; from this software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; An edge router typically sits between two networks such as the provider
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; core network and the provider access network. A typical packet processing
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; pipeline for the upstream traffic (i.e. traffic from access to core
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; network) contains the following functional blocks: Packet RX & Firewall,
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; Flow classification, Metering, Routing and Packet TX. The input packets
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; are assumed to be Q-in-Q IPv4, while the output packets are MPLS IPv4
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; (with variable number of labels per route).
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; A simple implementation for this functional pipeline is presented below.
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; Packet Rx & Pass-Through Flow-Classification Flow-Actions Routing
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: Firewall
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; __________ SWQ0 __________ SWQ4 __________ SWQ8 __________ SWQ12 __________
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; RXQ0.0 --->| |------>| |------>| |------>| |------>| |------> TXQ0.0
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; | | SWQ1 | | SWQ5 | | SWQ9 | | SWQ13 | |
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; RXQ1.0 --->| |------>| |------>| |------>| |------>| |------> TXQ1.0
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; | (P1) | SWQ2 | (P2) | SWQ6 | (P3) | SWQ10 | (P4) | SWQ14 | (P5) |
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; RXQ2.0 --->| |------>| |------>| |------>| |------>| |------> TXQ2.0
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; | | SWQ3 | | SWQ7 | | SWQ11 | | SWQ15 | |
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; RXQ3.0 --->| |------>| |------>| |------>| |------>| |------> TXQ3.0
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; |__________| |__________| |__________| |__________| |__________|
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; | | |
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; +--> SINK0 (Default) +--> SINK1 (Default) +--> SINK2 (Route Miss)
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[PIPELINE0]
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type = MASTER
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core = 0
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[PIPELINE1]
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type = FIREWALL
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core = 1
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pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
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pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
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n_rules = 4096
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pkt_type = qinq_ipv4
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[PIPELINE2]
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type = PASS-THROUGH
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core = 2
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pktq_in = SWQ0 SWQ1 SWQ2 SWQ3
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pktq_out = SWQ4 SWQ5 SWQ6 SWQ7
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dma_size = 8
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dma_dst_offset = 128; mbuf (128)
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dma_src_offset = 268; mbuf (128) + headroom (128) + 1st ethertype offset (12) = 268
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dma_src_mask = 00000FFF00000FFF; qinq
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dma_hash_offset = 136; dma_dst_offset + dma_size = 136
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[PIPELINE3]
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type = FLOW_CLASSIFICATION
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core = 2
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pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
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pktq_out = SWQ8 SWQ9 SWQ10 SWQ11 SINK1
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n_flows = 65536
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key_size = 8; dma_size
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key_offset = 128; dma_dst_offset
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hash_offset = 136; dma_hash_offset
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flowid_offset = 192; mbuf (128) + 64
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[PIPELINE4]
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type = FLOW_ACTIONS
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core = 3
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pktq_in = SWQ8 SWQ9 SWQ10 SWQ11
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pktq_out = SWQ12 SWQ13 SWQ14 SWQ15
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n_flows = 65536
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n_meters_per_flow = 1
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flow_id_offset = 192; flowid_offset
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ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278
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color_offset = 196; flowid_offset + sizeof(flow_id)
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[PIPELINE5]
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type = ROUTING
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core = 4
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pktq_in = SWQ12 SWQ13 SWQ14 SWQ15
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pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK2
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encap = ethernet_mpls
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mpls_color_mark = yes
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ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278
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color_offset = 196; flowid_offset + sizeof(flow_id)
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38
examples/ip_pipeline/config/edge_router_upstream.sh
Normal file
38
examples/ip_pipeline/config/edge_router_upstream.sh
Normal file
@ -0,0 +1,38 @@
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################################################
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# Firewall Rules:4 for 4 ports
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################################################
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p 1 firewall add ipv4 1 0.0.0.0 8 0.0.0.0 10 0 0 0 0 6 1 0
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p 1 firewall add ipv4 1 0.0.0.0 8 0.64.0.0 10 0 0 0 0 6 1 1
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p 1 firewall add ipv4 1 0.0.0.0 8 0.128.0.0 10 0 0 0 0 6 1 2
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p 1 firewall add ipv4 1 0.0.0.0 8 0.192.0.0 10 0 0 0 0 6 1 3
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p 1 firewall add default 4 #SINK0
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################################################################################
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# Flow classification
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################################################################################
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p 3 flow add default 4 #SINK1
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p 3 flow add qinq all 65536 4
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################################################################################
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# Flow Actions - Metering
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################################################################################
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p 4 flows 65536 meter 0 trtcm 1250000000 1250000000 100000000 100000000
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p 4 flows 65536 ports 4
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################################################################################
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# Routing: Ether MPLS, ARP off
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################################################################################
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p 5 route add default 4 #SINK2
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p 5 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0 mpls 0:1
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p 5 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1 mpls 10:11
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p 5 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2 mpls 20:21
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p 5 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3 mpls 30:31
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################################################################################
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# List all configurations
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################################################################################
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p 1 firewall ls
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#p 3 flow ls
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#p 4 flow actions ls
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p 5 route ls
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55
examples/ip_pipeline/config/l2fwd.cfg
Normal file
55
examples/ip_pipeline/config/l2fwd.cfg
Normal file
@ -0,0 +1,55 @@
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; BSD LICENSE
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;
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; Copyright(c) 2015 Intel Corporation. All rights reserved.
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; All rights reserved.
|
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;
|
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; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions
|
||||
; are met:
|
||||
;
|
||||
; * Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; * Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
||||
; distribution.
|
||||
; * Neither the name of Intel Corporation nor the names of its
|
||||
; contributors may be used to endorse or promote products derived
|
||||
; from this software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; The pass-through pipeline below connects the input ports to the output ports
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; as follows: RXQ0.0 -> TXQ1.0, RXQ1.0 -> TXQ0.0, RXQ2.0 -> TXQ3.0 and
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; RXQ3.0 -> TXQ2.0.
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; ________________
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; RXQ0.0 --->|................|---> TXQ1.0
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; | |
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; RXQ1.0 --->|................|---> TXQ0.0
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; | Pass-through |
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; RXQ2.0 --->|................|---> TXQ3.0
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; | |
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; RXQ3.0 --->|................|---> TXQ2.0
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; |________________|
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;
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[PIPELINE0]
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type = MASTER
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core = 0
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[PIPELINE1]
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type = PASS-THROUGH
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core = 1
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pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
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pktq_out = TXQ1.0 TXQ0.0 TXQ3.0 TXQ2.0
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63
examples/ip_pipeline/config/l3fwd.cfg
Normal file
63
examples/ip_pipeline/config/l3fwd.cfg
Normal file
@ -0,0 +1,63 @@
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; BSD LICENSE
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;
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; Copyright(c) 2015 Intel Corporation. All rights reserved.
|
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; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions
|
||||
; are met:
|
||||
;
|
||||
; * Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; * Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
||||
; distribution.
|
||||
; * Neither the name of Intel Corporation nor the names of its
|
||||
; contributors may be used to endorse or promote products derived
|
||||
; from this software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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; _______________
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; RXQ0.0 --->| |---> TXQ0.0
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; | |
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; RXQ1.0 --->| |---> TXQ1.0
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; | Routing |
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; RXQ2.0 --->| |---> TXQ2.0
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; | |
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; RXQ3.0 --->| |---> TXQ3.0
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; |_______________|
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; |
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; +-----------> SINK0 (route miss)
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;
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; Input packet: Ethernet/IPv4
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;
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; Packet buffer layout:
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; # Field Name Offset (Bytes) Size (Bytes)
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; 0 Mbuf 0 128
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; 1 Headroom 128 128
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; 2 Ethernet header 256 14
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; 3 IPv4 header 270 20
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[PIPELINE0]
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type = MASTER
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core = 0
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[PIPELINE1]
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type = ROUTING
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core = 1
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pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
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pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK0
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encap = ethernet; encap = ethernet / ethernet_qinq / ethernet_mpls
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ip_hdr_offset = 270
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9
examples/ip_pipeline/config/l3fwd.sh
Normal file
9
examples/ip_pipeline/config/l3fwd.sh
Normal file
@ -0,0 +1,9 @@
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################################################################################
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# Routing: encap = ethernet, arp = off
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################################################################################
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p 1 route add default 4 #SINK0
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p 1 route add 0.0.0.0 10 port 0 ether a0:b0:c0:d0:e0:f0
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p 1 route add 0.64.0.0 10 port 1 ether a1:b1:c1:d1:e1:f1
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p 1 route add 0.128.0.0 10 port 2 ether a2:b2:c2:d2:e2:f2
|
||||
p 1 route add 0.192.0.0 10 port 3 ether a3:b3:c3:d3:e3:f3
|
||||
p 1 route ls
|
||||
Loading…
Reference in New Issue
Block a user