net/sfc/base: support inner checksum offload on transmit
Inner checksum offloads may be used only if firmware supports these tunnels. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
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@ -84,12 +84,16 @@ efx_mcdi_init_txq(
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MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
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MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
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MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
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MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS,
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INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
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INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
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(flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
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INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
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(flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
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INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN,
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(flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0,
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INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN,
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(flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
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INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
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INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
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INIT_TXQ_IN_CRC_MODE, 0,
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@ -194,14 +198,23 @@ ef10_tx_qcreate(
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__in efx_txq_t *etp,
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__out unsigned int *addedp)
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{
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efx_nic_cfg_t *encp = &enp->en_nic_cfg;
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uint16_t inner_csum;
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efx_qword_t desc;
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efx_rc_t rc;
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_NOTE(ARGUNUSED(id))
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inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
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if (((flags & inner_csum) != 0) &&
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(encp->enc_tunnel_encapsulations_supported == 0)) {
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rc = EINVAL;
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goto fail1;
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}
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if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
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esmp)) != 0)
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goto fail1;
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goto fail2;
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/*
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* A previous user of this TX queue may have written a descriptor to the
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@ -212,19 +225,25 @@ ef10_tx_qcreate(
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* a no-op TX option descriptor. See bug29981 for details.
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*/
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*addedp = 1;
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EFX_POPULATE_QWORD_4(desc,
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EFX_POPULATE_QWORD_6(desc,
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ESF_DZ_TX_DESC_IS_OPT, 1,
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ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
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ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
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(flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
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ESF_DZ_TX_OPTION_IP_CSUM,
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(flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
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(flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
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ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
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(flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
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ESF_DZ_TX_OPTION_INNER_IP_CSUM,
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(flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
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EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
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ef10_tx_qpush(etp, *addedp, 0);
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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@ -2107,9 +2107,11 @@ efx_tx_fini(
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#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
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#define EFX_TXQ_CKSUM_IPV4 0x0001
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#define EFX_TXQ_CKSUM_TCPUDP 0x0002
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#define EFX_TXQ_FATSOV2 0x0004
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#define EFX_TXQ_CKSUM_IPV4 0x0001
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#define EFX_TXQ_CKSUM_TCPUDP 0x0002
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#define EFX_TXQ_FATSOV2 0x0004
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#define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
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#define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
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extern __checkReturn efx_rc_t
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efx_tx_qcreate(
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@ -899,6 +899,7 @@ siena_tx_qcreate(
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_oword_t oword;
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uint32_t size;
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uint16_t inner_csum;
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efx_rc_t rc;
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_NOTE(ARGUNUSED(esmp))
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@ -928,6 +929,12 @@ siena_tx_qcreate(
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goto fail3;
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}
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inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
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if ((flags & inner_csum) != 0) {
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rc = EINVAL;
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goto fail4;
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}
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/* Set up the new descriptor queue */
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*addedp = 0;
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@ -950,6 +957,8 @@ siena_tx_qcreate(
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return (0);
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fail4:
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EFSYS_PROBE(fail4);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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