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event/cnxk: fix base pointer for SSO head wait

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Function roc_sso_hws_head_wait() expects a base as input pointer, and it
will itself get tag_op from the base. By passing tag_op instead of base
pointer to this function will add SSOW_LF_GWS_TAG register offset twice,
which will lead to accessing wrong register.

Fixes: 1f5b3d55c0 ("event/cnxk: store and reuse workslot status")
Cc: stable@dpdk.org

Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Volodymyr Fialko 2022-03-25 11:59:39 +01:00 committed by Jerin Jacob
parent b450a990b0
commit 80bb303d3b
6 changed files with 10 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/crypto/cnxk/cn10k_cryptodev_ops.c
View File

@ -265,7 +265,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
}
uint16_t
cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)
{
union rte_event_crypto_metadata *ec_mdata;
struct cpt_inflight_req *infl_req;
@ -328,7 +328,7 @@ cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
}
if (!rsp_info->sched_type)
roc_sso_hws_head_wait(tag_op);
roc_sso_hws_head_wait(base);
lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);

2
drivers/crypto/cnxk/cn10k_cryptodev_ops.h
View File

@ -13,7 +13,7 @@ extern struct rte_cryptodev_ops cn10k_cpt_ops;
void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
__rte_internal
uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,
uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base,
struct rte_crypto_op *op);
__rte_internal
uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);

4
drivers/crypto/cnxk/cn9k_cryptodev_ops.c
View File

@ -317,7 +317,7 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
}
uint16_t
cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)
{
union rte_event_crypto_metadata *ec_mdata;
struct cpt_inflight_req *infl_req;
@ -374,7 +374,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
}
if (!rsp_info->sched_type)
roc_sso_hws_head_wait(tag_op);
roc_sso_hws_head_wait(base);
cn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr);

2
drivers/crypto/cnxk/cn9k_cryptodev_ops.h
View File

@ -12,7 +12,7 @@ extern struct rte_cryptodev_ops cn9k_cpt_ops;
void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
__rte_internal
uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,
uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t base,
struct rte_crypto_op *op);
__rte_internal
uintptr_t cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);

3
drivers/event/cnxk/cn10k_worker.c
View File

@ -68,6 +68,5 @@ cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
return cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,
ev->event_ptr);
return cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);
}

7
drivers/event/cnxk/cn9k_worker.c
View File

@ -128,8 +128,7 @@ cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
return cn9k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,
ev->event_ptr);
return cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);
}
uint16_t __rte_hot
@ -139,6 +138,6 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
return cn9k_cpt_crypto_adapter_enqueue(
dws->base[!dws->vws] + SSOW_LF_GWS_TAG, ev->event_ptr);
return cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws],
ev->event_ptr);
}