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net/hinic/base: add various headers

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Add various headers that define mgmt commands, cmdq commands
and basic defines for use in the code.

Signed-off-by: Ziyang Xuan <xuanziyang2@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Ziyang Xuan 2019-06-27 16:17:45 +08:00 committed by Ferruh Yigit
parent 828d3e15a9
commit 81d53291a4
2 changed files with 709 additions and 0 deletions
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256
drivers/net/hinic/base/hinic_compat.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*/
#ifndef _HINIC_COMPAT_H_
#define _HINIC_COMPAT_H_
#include <stdint.h>
#include <sys/time.h>
#include <rte_common.h>
#include <rte_byteorder.h>
#include <rte_memzone.h>
#include <rte_memcpy.h>
#include <rte_malloc.h>
#include <rte_atomic.h>
#include <rte_spinlock.h>
#include <rte_cycles.h>
#include <rte_log.h>
#include <rte_config.h>
typedef uint8_t u8;
typedef int8_t s8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef int32_t s32;
typedef uint64_t u64;
#ifndef dma_addr_t
typedef uint64_t dma_addr_t;
#endif
#ifndef gfp_t
#define gfp_t unsigned
#endif
#ifndef bool
#define bool int
#endif
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#ifndef false
#define false (0)
#endif
#ifndef true
#define true (1)
#endif
#ifndef NULL
#define NULL ((void *)0)
#endif
#define HINIC_ERROR (-1)
#define HINIC_OK (0)
#ifndef BIT
#define BIT(n) (1 << (n))
#endif
#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
#define lower_32_bits(n) ((u32)(n))
/* Returns X / Y, rounding up. X must be nonnegative to round correctly. */
#define DIV_ROUND_UP(X, Y) (((X) + ((Y) - 1)) / (Y))
/* Returns X rounded up to the nearest multiple of Y. */
#define ROUND_UP(X, Y) (DIV_ROUND_UP(X, Y) * (Y))
#undef ALIGN
#define ALIGN(x, a) RTE_ALIGN(x, a)
#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
/* Reported driver name. */
#define HINIC_DRIVER_NAME "net_hinic"
extern int hinic_logtype;
#define PMD_DRV_LOG(level, fmt, args...) \
rte_log(RTE_LOG_ ## level, hinic_logtype, \
HINIC_DRIVER_NAME": " fmt "\n", ##args)
/* common definition */
#ifndef ETH_ALEN
#define ETH_ALEN 6
#endif
#define ETH_HLEN 14
#define ETH_CRC_LEN 4
#define VLAN_PRIO_SHIFT 13
#define VLAN_N_VID 4096
/* bit order interface */
#define cpu_to_be16(o) rte_cpu_to_be_16(o)
#define cpu_to_be32(o) rte_cpu_to_be_32(o)
#define cpu_to_be64(o) rte_cpu_to_be_64(o)
#define cpu_to_le32(o) rte_cpu_to_le_32(o)
#define be16_to_cpu(o) rte_be_to_cpu_16(o)
#define be32_to_cpu(o) rte_be_to_cpu_32(o)
#define be64_to_cpu(o) rte_be_to_cpu_64(o)
#define le32_to_cpu(o) rte_le_to_cpu_32(o)
/* virt memory and dma phy memory */
#define __iomem
#define GFP_KERNEL RTE_MEMZONE_IOVA_CONTIG
#define HINIC_PAGE_SHIFT 12
#define HINIC_PAGE_SIZE RTE_PGSIZE_4K
#define HINIC_MEM_ALLOC_ALIGNE_MIN 8
#define HINIC_PAGE_SIZE_DPDK 6
static inline int hinic_test_bit(int nr, volatile unsigned long *addr)
{
int res;
rte_mb();
res = ((*addr) & (1UL << nr)) != 0;
rte_mb();
return res;
}
static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr)
{
__sync_fetch_and_or(addr, (1UL << nr));
}
static inline void hinic_clear_bit(int nr, volatile unsigned long *addr)
{
__sync_fetch_and_and(addr, ~(1UL << nr));
}
static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = (1UL << nr);
return __sync_fetch_and_and(addr, ~mask) & mask;
}
static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = (1UL << nr);
return __sync_fetch_and_or(addr, mask) & mask;
}
void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle,
gfp_t flag);
void *dma_zalloc_coherent_aligned(void *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag);
void *dma_zalloc_coherent_aligned256k(void *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys);
/* dma pool alloc and free */
#define pci_pool dma_pool
#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
struct dma_pool *dma_pool_create(const char *name, void *dev, size_t size,
size_t align, size_t boundary);
void dma_pool_destroy(struct dma_pool *pool);
void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr);
void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma);
#define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGNE_MIN)
#define kzalloc_aligned(size, flag) rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE)
#define kfree(ptr) rte_free(ptr)
/* mmio interface */
static inline void writel(u32 value, volatile void *addr)
{
*(volatile u32 *)addr = value;
}
static inline u32 readl(const volatile void *addr)
{
return *(const volatile u32 *)addr;
}
#define __raw_writel(value, reg) writel((value), (reg))
#define __raw_readl(reg) readl((reg))
/* Spinlock related interface */
#define hinic_spinlock_t rte_spinlock_t
#define spinlock_t rte_spinlock_t
#define spin_lock_init(spinlock_prt) rte_spinlock_init(spinlock_prt)
#define spin_lock_deinit(lock)
#define spin_lock(spinlock_prt) rte_spinlock_lock(spinlock_prt)
#define spin_unlock(spinlock_prt) rte_spinlock_unlock(spinlock_prt)
static inline unsigned long get_timeofday_ms(void)
{
struct timeval tv;
(void)gettimeofday(&tv, NULL);
return (unsigned long)tv.tv_sec * 1000 + tv.tv_usec / 1000;
}
#define jiffies get_timeofday_ms()
#define msecs_to_jiffies(ms) (ms)
#define time_before(now, end) ((now) < (end))
/* misc kernel utils */
static inline u16 ilog2(u32 n)
{
u16 res = 0;
while (n > 1) {
n >>= 1;
res++;
}
return res;
}
/**
* hinic_cpu_to_be32 - convert data to big endian 32 bit format
* @data: the data to convert
* @len: length of data to convert, must be Multiple of 4B
**/
static inline void hinic_cpu_to_be32(void *data, u32 len)
{
u32 i;
u32 *mem = (u32 *)data;
for (i = 0; i < (len >> 2); i++) {
*mem = cpu_to_be32(*mem);
mem++;
}
}
/**
* hinic_be32_to_cpu - convert data from big endian 32 bit format
* @data: the data to convert
* @len: length of data to convert, must be Multiple of 4B
**/
static inline void hinic_be32_to_cpu(void *data, u32 len)
{
u32 i;
u32 *mem = (u32 *)data;
for (i = 0; i < (len >> 2); i++) {
*mem = be32_to_cpu(*mem);
mem++;
}
}
#endif /* _HINIC_COMPAT_H_ */

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drivers/net/hinic/base/hinic_pmd_cmd.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2017 Huawei Technologies Co., Ltd
*/
#ifndef _HINIC_PORT_CMD_H_
#define _HINIC_PORT_CMD_H_
enum hinic_eq_type {
HINIC_AEQ,
HINIC_CEQ
};
enum hinic_resp_aeq_num {
HINIC_AEQ0 = 0,
HINIC_AEQ1 = 1,
HINIC_AEQ2 = 2,
HINIC_AEQ3 = 3,
};
enum hinic_mod_type {
HINIC_MOD_COMM = 0, /* HW communication module */
HINIC_MOD_L2NIC = 1, /* L2NIC module */
HINIC_MOD_CFGM = 7, /* Configuration module */
HINIC_MOD_HILINK = 14,
HINIC_MOD_MAX = 15
};
/* cmd of mgmt CPU message for NIC module */
enum hinic_port_cmd {
HINIC_PORT_CMD_MGMT_RESET = 0x0,
HINIC_PORT_CMD_CHANGE_MTU = 0x2,
HINIC_PORT_CMD_ADD_VLAN = 0x3,
HINIC_PORT_CMD_DEL_VLAN,
HINIC_PORT_CMD_SET_ETS = 0x7,
HINIC_PORT_CMD_GET_ETS,
HINIC_PORT_CMD_SET_MAC = 0x9,
HINIC_PORT_CMD_GET_MAC,
HINIC_PORT_CMD_DEL_MAC,
HINIC_PORT_CMD_SET_RX_MODE = 0xc,
HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xd,
HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,
HINIC_PORT_CMD_SET_PAUSE_INFO,
HINIC_PORT_CMD_GET_LINK_STATE = 0x18,
HINIC_PORT_CMD_SET_LRO = 0x19,
HINIC_PORT_CMD_SET_RX_CSUM = 0x1a,
HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1b,
HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1c,
HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,
HINIC_PORT_CMD_GET_VPORT_STAT,
HINIC_PORT_CMD_CLEAN_VPORT_STAT,
HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,
HINIC_PORT_CMD_SET_PORT_ENABLE = 0x29,
HINIC_PORT_CMD_GET_PORT_ENABLE,
HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2b,
HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,
HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,
HINIC_PORT_CMD_GET_RSS_HASH_ENGINE,
HINIC_PORT_CMD_GET_RSS_CTX_TBL,
HINIC_PORT_CMD_SET_RSS_CTX_TBL,
HINIC_PORT_CMD_RSS_TEMP_MGR,
HINIC_PORT_CMD_RSS_CFG = 0x42,
HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,
HINIC_PORT_CMD_INIT_FUNC = 0x45,
HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a,
HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b,
HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c,
HINIC_PORT_CMD_SET_VPORT_ENABLE,
HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5e,
HINIC_PORT_CMD_GET_LRO = 0x63,
HINIC_PORT_CMD_GET_DMA_CS = 0x64,
HINIC_PORT_CMD_SET_DMA_CS,
HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66,
HINIC_PORT_CMD_SET_PFC_MISC = 0x67,
HINIC_PORT_CMD_GET_PFC_MISC,
HINIC_PORT_CMD_SET_VF_RATE = 0x69,
HINIC_PORT_CMD_SET_VF_VLAN,
HINIC_PORT_CMD_CLR_VF_VLAN,
HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73,
HINIC_PORT_CMD_SET_PFC_THD = 0x75,
HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xa0,
HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xa3,
HINIC_PORT_CMD_UPDATE_MAC = 0xa4,
HINIC_PORT_CMD_GET_PORT_INFO = 0xaa,
HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb,
HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc,
HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,
HINIC_PORT_CMD_SET_SPEED = 0xDA,
HINIC_PORT_CMD_SET_AUTONEG = 0xDB,
HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD,
HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE,
HINIC_PORT_CMD_SET_VF_COS = 0xDF,
HINIC_PORT_CMD_GET_VF_COS = 0xE1,
HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5,
HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6,
HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8,
HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB,
HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3,
HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4,
HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,
HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,
};
/* cmd of mgmt CPU message for HW module */
enum hinic_mgmt_cmd {
HINIC_MGMT_CMD_RESET_MGMT = 0x0,
HINIC_MGMT_CMD_START_FLR = 0x1,
HINIC_MGMT_CMD_FLUSH_DOORBELL = 0x2,
HINIC_MGMT_CMD_GET_IO_STATUS = 0x3,
HINIC_MGMT_CMD_DMA_ATTR_SET = 0x4,
HINIC_MGMT_CMD_CMDQ_CTXT_SET = 0x10,
HINIC_MGMT_CMD_CMDQ_CTXT_GET,
HINIC_MGMT_CMD_VAT_SET = 0x12,
HINIC_MGMT_CMD_VAT_GET,
HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET = 0x14,
HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,
HINIC_MGMT_CMD_PPF_HT_GPA_SET = 0x23,
HINIC_MGMT_CMD_RES_STATE_SET = 0x24,
HINIC_MGMT_CMD_FUNC_CACHE_OUT = 0x25,
HINIC_MGMT_CMD_FFM_SET = 0x26,
HINIC_MGMT_CMD_FUNC_RES_CLEAR = 0x29,
HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP = 0x33,
HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,
HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,
HINIC_MGMT_CMD_VF_RANDOM_ID_SET = 0x36,
HINIC_MGMT_CMD_FAULT_REPORT = 0x37,
HINIC_MGMT_CMD_VPD_SET = 0x40,
HINIC_MGMT_CMD_VPD_GET,
HINIC_MGMT_CMD_LABEL_SET,
HINIC_MGMT_CMD_LABEL_GET,
HINIC_MGMT_CMD_SATIC_MAC_SET,
HINIC_MGMT_CMD_SATIC_MAC_GET,
HINIC_MGMT_CMD_SYNC_TIME = 0x46,
HINIC_MGMT_CMD_SET_LED_STATUS = 0x4A,
HINIC_MGMT_CMD_L2NIC_RESET = 0x4b,
HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET = 0x4d,
HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT = 0x4E,
HINIC_MGMT_CMD_ACTIVATE_FW = 0x4F,
HINIC_MGMT_CMD_PAGESIZE_SET = 0x50,
HINIC_MGMT_CMD_PAGESIZE_GET = 0x51,
HINIC_MGMT_CMD_GET_BOARD_INFO = 0x52,
HINIC_MGMT_CMD_WATCHDOG_INFO = 0x56,
HINIC_MGMT_CMD_FMW_ACT_NTC = 0x57,
HINIC_MGMT_CMD_SET_VF_RANDOM_ID = 0x61,
HINIC_MGMT_CMD_GET_PPF_STATE = 0x63,
HINIC_MGMT_CMD_PCIE_DFX_NTC = 0x65,
HINIC_MGMT_CMD_PCIE_DFX_GET = 0x66,
};
/* cmd of mgmt CPU message for HILINK module */
enum hinic_hilink_cmd {
HINIC_HILINK_CMD_GET_LINK_INFO = 0x3,
HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8,
};
/* uCode related commands */
enum hinic_ucode_cmd {
HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT = 0,
HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
HINIC_UCODE_CMD_ARM_SQ,
HINIC_UCODE_CMD_ARM_RQ,
HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
HINIC_UCODE_CMD_SET_IQ_ENABLE,
HINIC_UCODE_CMD_SET_RQ_FLUSH = 10
};
enum cfg_sub_cmd {
/* PPF(PF) <-> FW */
HINIC_CFG_NIC_CAP = 0,
CFG_FW_VERSION,
CFG_UCODE_VERSION,
HINIC_CFG_MBOX_CAP = 6
};
enum hinic_ack_type {
HINIC_ACK_TYPE_CMDQ,
HINIC_ACK_TYPE_SHARE_CQN,
HINIC_ACK_TYPE_APP_CQN,
HINIC_MOD_ACK_MAX = 15,
};
enum sq_l4offload_type {
OFFLOAD_DISABLE = 0,
TCP_OFFLOAD_ENABLE = 1,
SCTP_OFFLOAD_ENABLE = 2,
UDP_OFFLOAD_ENABLE = 3,
};
enum sq_vlan_offload_flag {
VLAN_OFFLOAD_DISABLE = 0,
VLAN_OFFLOAD_ENABLE = 1,
};
enum sq_pkt_parsed_flag {
PKT_NOT_PARSED = 0,
PKT_PARSED = 1,
};
enum sq_l3_type {
UNKNOWN_L3TYPE = 0,
IPV6_PKT = 1,
IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
};
enum sq_md_type {
UNKNOWN_MD_TYPE = 0,
};
enum sq_l2type {
ETHERNET = 0,
};
enum sq_tunnel_l4_type {
NOT_TUNNEL,
TUNNEL_UDP_NO_CSUM,
TUNNEL_UDP_CSUM,
};
#define NIC_RSS_CMD_TEMP_ALLOC 0x01
#define NIC_RSS_CMD_TEMP_FREE 0x02
#define HINIC_RSS_TYPE_VALID_SHIFT 23
#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24
#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25
#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26
#define HINIC_RSS_TYPE_IPV6_SHIFT 27
#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28
#define HINIC_RSS_TYPE_IPV4_SHIFT 29
#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30
#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31
#define HINIC_RSS_TYPE_SET(val, member) \
(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
#define HINIC_RSS_TYPE_GET(val, member) \
(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
enum hinic_speed {
HINIC_SPEED_10MB_LINK = 0,
HINIC_SPEED_100MB_LINK,
HINIC_SPEED_1000MB_LINK,
HINIC_SPEED_10GB_LINK,
HINIC_SPEED_25GB_LINK,
HINIC_SPEED_40GB_LINK,
HINIC_SPEED_100GB_LINK,
HINIC_SPEED_UNKNOWN = 0xFF,
};
enum {
HINIC_IFLA_VF_LINK_STATE_AUTO, /* link state of the uplink */
HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */
HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */
};
#define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0
#define HINIC_AF0_P2P_IDX_SHIFT 10
#define HINIC_AF0_PCI_INTF_IDX_SHIFT 14
#define HINIC_AF0_VF_IN_PF_SHIFT 16
#define HINIC_AF0_FUNC_TYPE_SHIFT 24
#define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF
#define HINIC_AF0_P2P_IDX_MASK 0xF
#define HINIC_AF0_PCI_INTF_IDX_MASK 0x3
#define HINIC_AF0_VF_IN_PF_MASK 0xFF
#define HINIC_AF0_FUNC_TYPE_MASK 0x1
#define HINIC_AF0_GET(val, member) \
(((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
#define HINIC_AF1_PPF_IDX_SHIFT 0
#define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8
#define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12
#define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20
#define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24
#define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30
#define HINIC_AF1_PF_INIT_STATUS_SHIFT 31
#define HINIC_AF1_PPF_IDX_MASK 0x1F
#define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3
#define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7
#define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF
#define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7
#define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1
#define HINIC_AF1_PF_INIT_STATUS_MASK 0x1
#define HINIC_AF1_GET(val, member) \
(((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16
#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF
#define HINIC_AF2_GET(val, member) \
(((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
#define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0
#define HINIC_AF4_DOORBELL_CTRL_SHIFT 1
#define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1
#define HINIC_AF4_DOORBELL_CTRL_MASK 0x1
#define HINIC_AF4_GET(val, member) \
(((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
#define HINIC_AF4_SET(val, member) \
(((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
#define HINIC_AF4_CLEAR(val, member) \
((val) & (~(HINIC_AF4_##member##_MASK << \
HINIC_AF4_##member##_SHIFT)))
#define HINIC_AF5_PF_STATUS_SHIFT 0
#define HINIC_AF5_PF_STATUS_MASK 0xFFFF
#define HINIC_AF5_SET(val, member) \
(((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
#define HINIC_AF5_GET(val, member) \
(((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
#define HINIC_AF5_CLEAR(val, member) \
((val) & (~(HINIC_AF5_##member##_MASK << \
HINIC_AF5_##member##_SHIFT)))
#define HINIC_PPF_ELECTION_IDX_SHIFT 0
#define HINIC_PPF_ELECTION_IDX_MASK 0x1F
#define HINIC_PPF_ELECTION_SET(val, member) \
(((val) & HINIC_PPF_ELECTION_##member##_MASK) << \
HINIC_PPF_ELECTION_##member##_SHIFT)
#define HINIC_PPF_ELECTION_GET(val, member) \
(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
HINIC_PPF_ELECTION_##member##_MASK)
#define HINIC_PPF_ELECTION_CLEAR(val, member) \
((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
<< HINIC_PPF_ELECTION_##member##_SHIFT)))
#define DB_IDX(db, db_base) \
((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \
HINIC_DB_PAGE_SIZE))
enum hinic_pcie_nosnoop {
HINIC_PCIE_SNOOP = 0,
HINIC_PCIE_NO_SNOOP = 1,
};
enum hinic_pcie_tph {
HINIC_PCIE_TPH_DISABLE = 0,
HINIC_PCIE_TPH_ENABLE = 1,
};
enum hinic_outbound_ctrl {
ENABLE_OUTBOUND = 0x0,
DISABLE_OUTBOUND = 0x1,
};
enum hinic_doorbell_ctrl {
ENABLE_DOORBELL = 0x0,
DISABLE_DOORBELL = 0x1,
};
enum hinic_pf_status {
HINIC_PF_STATUS_INIT = 0X0,
HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
};
/* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
#define HINIC_DB_DWQE_SIZE 0x00080000
/* db/dwqe page size: 4K */
#define HINIC_DB_PAGE_SIZE 0x00001000ULL
#define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
#define HINIC_PCI_MSIX_ENTRY_SIZE 16
#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
struct hinic_mgmt_msg_head {
u8 status;
u8 version;
u8 resp_aeq_num;
u8 rsvd0[5];
};
struct hinic_root_ctxt {
struct hinic_mgmt_msg_head mgmt_msg_head;
u16 func_idx;
u16 rsvd1;
u8 set_cmdq_depth;
u8 cmdq_depth;
u8 lro_en;
u8 rsvd2;
u8 ppf_idx;
u8 rsvd3;
u16 rq_depth;
u16 rx_buf_sz;
u16 sq_depth;
};
#endif /* _HINIC_PORT_CMD_H_ */