dma/idxd: add datapath structures
Add data structures required for the data path for IDXD devices. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com> Reviewed-by: Conor Walsh <conor.walsh@intel.com> Reviewed-by: Chengwen Feng <fengchengwen@huawei.com>
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@ -96,6 +96,7 @@ idxd_dev_close(struct rte_dma_dev *dev)
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static const struct rte_dma_dev_ops idxd_bus_ops = {
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.dev_close = idxd_dev_close,
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.dev_dump = idxd_dump,
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};
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static void *
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@ -10,6 +10,35 @@
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#define IDXD_PMD_NAME_STR "dmadev_idxd"
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int
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idxd_dump(const struct rte_dma_dev *dev, FILE *f)
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{
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struct idxd_dmadev *idxd = dev->fp_obj->dev_private;
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unsigned int i;
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fprintf(f, "== IDXD Private Data ==\n");
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fprintf(f, " Portal: %p\n", idxd->portal);
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fprintf(f, " Config: { ring_size: %u }\n",
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idxd->qcfg.nb_desc);
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fprintf(f, " Batch ring (sz = %u, max_batches = %u):\n\t",
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idxd->max_batches + 1, idxd->max_batches);
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for (i = 0; i <= idxd->max_batches; i++) {
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fprintf(f, " %u ", idxd->batch_idx_ring[i]);
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if (i == idxd->batch_idx_read && i == idxd->batch_idx_write)
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fprintf(f, "[rd ptr, wr ptr] ");
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else if (i == idxd->batch_idx_read)
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fprintf(f, "[rd ptr] ");
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else if (i == idxd->batch_idx_write)
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fprintf(f, "[wr ptr] ");
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if (i == idxd->max_batches)
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fprintf(f, "\n");
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}
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fprintf(f, " Curr batch: start = %u, size = %u\n", idxd->batch_start, idxd->batch_size);
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fprintf(f, " IDS: avail = %u, returned: %u\n", idxd->ids_avail, idxd->ids_returned);
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return 0;
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}
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int
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idxd_dmadev_create(const char *name, struct rte_device *dev,
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const struct idxd_dmadev *base_idxd,
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@ -19,6 +48,10 @@ idxd_dmadev_create(const char *name, struct rte_device *dev,
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struct rte_dma_dev *dmadev = NULL;
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int ret = 0;
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RTE_BUILD_BUG_ON(sizeof(struct idxd_hw_desc) != 64);
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RTE_BUILD_BUG_ON(offsetof(struct idxd_hw_desc, size) != 32);
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RTE_BUILD_BUG_ON(sizeof(struct idxd_completion) != 32);
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if (!name) {
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IDXD_PMD_ERR("Invalid name of the device!");
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ret = -EINVAL;
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@ -5,6 +5,47 @@
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#ifndef _IDXD_HW_DEFS_H_
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#define _IDXD_HW_DEFS_H_
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/*
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* Defines used in the data path for interacting with IDXD hardware.
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*/
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#define IDXD_CMD_OP_SHIFT 24
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enum rte_idxd_ops {
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idxd_op_nop = 0,
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idxd_op_batch,
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idxd_op_drain,
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idxd_op_memmove,
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idxd_op_fill
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};
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#define IDXD_FLAG_FENCE (1 << 0)
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#define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)
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#define IDXD_FLAG_REQUEST_COMPLETION (1 << 3)
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#define IDXD_FLAG_CACHE_CONTROL (1 << 8)
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/**
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* Hardware descriptor used by DSA hardware, for both bursts and
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* for individual operations.
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*/
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struct idxd_hw_desc {
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uint32_t pasid;
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uint32_t op_flags;
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rte_iova_t completion;
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RTE_STD_C11
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union {
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rte_iova_t src; /* source address for copy ops etc. */
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rte_iova_t desc_addr; /* descriptor pointer for batch */
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};
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rte_iova_t dst;
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uint32_t size; /* length of data for op, or batch size */
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uint16_t intr_handle; /* completion interrupt handle */
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/* remaining 26 bytes are reserved */
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uint16_t __reserved[13];
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} __rte_aligned(64);
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#define IDXD_COMP_STATUS_INCOMPLETE 0
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#define IDXD_COMP_STATUS_SUCCESS 1
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#define IDXD_COMP_STATUS_INVALID_OPCODE 0x10
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@ -40,6 +40,8 @@ struct idxd_pci_common {
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};
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struct idxd_dmadev {
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struct idxd_hw_desc *desc_ring;
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/* counters to track the batches */
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unsigned short max_batches;
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unsigned short batch_idx_read;
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@ -63,6 +65,7 @@ struct idxd_dmadev {
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unsigned short max_batch_size;
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struct rte_dma_dev *dmadev;
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struct rte_dma_vchan_conf qcfg;
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uint8_t sva_support;
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uint8_t qid;
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@ -77,5 +80,6 @@ struct idxd_dmadev {
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int idxd_dmadev_create(const char *name, struct rte_device *dev,
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const struct idxd_dmadev *base_idxd, const struct rte_dma_dev_ops *ops);
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int idxd_dump(const struct rte_dma_dev *dev, FILE *f);
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#endif /* _IDXD_INTERNAL_H_ */
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@ -77,12 +77,14 @@ idxd_pci_dev_close(struct rte_dma_dev *dev)
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/* free device memory */
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IDXD_PMD_DEBUG("Freeing device driver memory");
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rte_free(idxd->batch_idx_ring);
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rte_free(idxd->desc_ring);
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return 0;
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}
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static const struct rte_dma_dev_ops idxd_pci_ops = {
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.dev_close = idxd_pci_dev_close,
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.dev_dump = idxd_dump,
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};
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/* each portal uses 4 x 4k pages */
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