net/i40e/base: add AQ command for read/write PHY registers
This patch adds new additional command for accessing to PHY registers. Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
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@ -245,6 +245,8 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_set_phy_debug = 0x0622,
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i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
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i40e_aqc_opc_run_phy_activity = 0x0626,
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i40e_aqc_opc_set_phy_register = 0x0628,
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i40e_aqc_opc_get_phy_register = 0x0629,
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/* NVM commands */
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i40e_aqc_opc_nvm_read = 0x0701,
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@ -2128,6 +2130,22 @@ struct i40e_aqc_run_phy_activity {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
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/* Set PHY Register command (0x0628) */
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/* Get PHY Register command (0x0629) */
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struct i40e_aqc_phy_register_access {
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u8 phy_interface;
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#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
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#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
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#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
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u8 dev_addres;
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u8 reserved1[2];
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u32 reg_address;
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u32 reg_value;
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u8 reserved2[4];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
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/* NVM Read command (indirect 0x0701)
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* NVM Erase commands (direct 0x0702)
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* NVM Update commands (indirect 0x0703)
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@ -6863,6 +6863,76 @@ void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
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if (status || use_register)
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wr32(hw, reg_addr, reg_val);
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}
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/**
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* i40e_aq_set_phy_register
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* @hw: pointer to the hw struct
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* @phy_select: select which phy should be accessed
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* @dev_addr: PHY device address
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* @reg_addr: PHY register address
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* @reg_val: new register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Write the external PHY register.
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**/
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enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
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u8 phy_select, u8 dev_addr,
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u32 reg_addr, u32 reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_phy_register_access *cmd =
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(struct i40e_aqc_phy_register_access *)&desc.params.raw;
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enum i40e_status_code status;
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i40e_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_set_phy_register);
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cmd->phy_interface = phy_select;
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cmd->dev_addres = dev_addr;
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cmd->reg_address = reg_addr;
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cmd->reg_value = reg_val;
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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return status;
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}
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/**
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* i40e_aq_get_phy_register
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* @hw: pointer to the hw struct
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* @phy_select: select which phy should be accessed
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* @dev_addr: PHY device address
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* @reg_addr: PHY register address
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* @reg_val: read register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Read the external PHY register.
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**/
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enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
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u8 phy_select, u8 dev_addr,
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u32 reg_addr, u32 *reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_phy_register_access *cmd =
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(struct i40e_aqc_phy_register_access *)&desc.params.raw;
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enum i40e_status_code status;
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i40e_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_get_phy_register);
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cmd->phy_interface = phy_select;
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cmd->dev_addres = dev_addr;
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cmd->reg_address = reg_addr;
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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if (!status)
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*reg_val = cmd->reg_value;
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return status;
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}
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#ifdef VF_DRIVER
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/**
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@ -533,6 +533,15 @@ enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
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u32 reg_addr, u32 reg_val,
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struct i40e_asq_cmd_details *cmd_details);
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void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
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enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
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u8 phy_select, u8 dev_addr,
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u32 reg_addr, u32 reg_val,
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struct i40e_asq_cmd_details *cmd_details);
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enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
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u8 phy_select, u8 dev_addr,
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u32 reg_addr, u32 *reg_val,
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struct i40e_asq_cmd_details *cmd_details);
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enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
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struct i40e_aqc_arp_proxy_data *proxy_config,
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struct i40e_asq_cmd_details *cmd_details);
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