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eal/arm64: fix memory barrier definition

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dsb instruction based barrier is used for non smp
version of memory barrier.

Fixes: d708f01b7102 ("eal/arm: add atomic operations for ARMv8")
Cc: stable@dpdk.org

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
This commit is contained in:
Jerin Jacob 2017-01-18 06:51:20 +05:30 committed by Thomas Monjalon
parent b41508b7a4
commit 84733fd0d7
1 changed files with 5 additions and 4 deletions
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9
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
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@ -43,7 +43,8 @@ extern "C" {
#include "generic/rte_atomic.h"
#define dmb(opt) do { asm volatile("dmb " #opt : : : "memory"); } while (0)
#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
/**
* General memory barrier.
@ -54,7 +55,7 @@ extern "C" {
*/
static inline void rte_mb(void)
{
dmb(ish);
dsb(sy);
}
/**
@ -66,7 +67,7 @@ static inline void rte_mb(void)
*/
static inline void rte_wmb(void)
{
dmb(ishst);
dsb(st);
}
/**
@ -78,7 +79,7 @@ static inline void rte_wmb(void)
*/
static inline void rte_rmb(void)
{
dmb(ishld);
dsb(ld);
}
#define rte_smp_mb() rte_mb()