crypto/octeontx: add hardware register access for misc poll
Adding hardware register accesses required for misc poll Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
This commit is contained in:
Ankur Dwivedi
Akhil Goyal
parent
0dc1cffa4d
commit
84eb02f778
519
drivers/common/cpt/cpt_hw_types.h
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519
drivers/common/cpt/cpt_hw_types.h
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@ -0,0 +1,519 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Cavium, Inc
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*/
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#ifndef _CPT_HW_TYPES_H_
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#define _CPT_HW_TYPES_H_
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#include <rte_byteorder.h>
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/*
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* This file defines HRM specific structs.
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*
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*/
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#define CPT_VF_INTR_MBOX_MASK (1<<0)
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#define CPT_VF_INTR_DOVF_MASK (1<<1)
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#define CPT_VF_INTR_IRDE_MASK (1<<2)
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#define CPT_VF_INTR_NWRP_MASK (1<<3)
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#define CPT_VF_INTR_SWERR_MASK (1<<4)
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#define CPT_VF_INTR_HWERR_MASK (1<<5)
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#define CPT_VF_INTR_FAULT_MASK (1<<6)
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/*
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* CPT_INST_S software command definitions
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* Words EI (0-3)
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*/
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typedef union {
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uint64_t u64;
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struct {
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uint16_t opcode;
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uint16_t param1;
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uint16_t param2;
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uint16_t dlen;
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} s;
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} vq_cmd_word0_t;
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typedef union {
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uint64_t u64;
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struct {
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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uint64_t grp : 3;
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uint64_t cptr : 61;
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#else
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uint64_t cptr : 61;
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uint64_t grp : 3;
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#endif
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} s;
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} vq_cmd_word3_t;
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typedef struct cpt_vq_command {
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vq_cmd_word0_t cmd;
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uint64_t dptr;
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uint64_t rptr;
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vq_cmd_word3_t cptr;
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} cpt_vq_cmd_t;
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/**
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* Structure cpt_inst_s
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*
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* CPT Instruction Structure
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* This structure specifies the instruction layout.
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* Instructions are stored in memory as little-endian unless
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* CPT()_PF_Q()_CTL[INST_BE] is set.
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*/
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typedef union cpt_inst_s {
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uint64_t u[8];
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struct cpt_inst_s_8s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_17_63 : 47;
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/* [ 16: 16] Done interrupt.
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* 0 = No interrupts related to this instruction.
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* 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
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* will be incremented, and based on the rules described
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* there an interrupt may occur.
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*/
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uint64_t doneint : 1;
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uint64_t reserved_0_15 : 16;
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#else /* Word 0 - Little Endian */
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uint64_t reserved_0_15 : 16;
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uint64_t doneint : 1;
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uint64_t reserved_17_63 : 47;
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#endif /* Word 0 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
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/* [127: 64] Result IOVA.
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* If nonzero, specifies where to write CPT_RES_S.
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* If zero, no result structure will be written.
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* Address must be 16-byte aligned.
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*
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* Bits <63:49> are ignored by hardware; software should
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* use a sign-extended bit <48> for forward compatibility.
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*/
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uint64_t res_addr : 64;
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#else /* Word 1 - Little Endian */
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uint64_t res_addr : 64;
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#endif /* Word 1 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
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uint64_t reserved_172_191 : 20;
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/* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
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* use when CPT submits work to SSO.
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* For the SSO to not discard the add-work request, FPA_PF_MAP()
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* must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
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*/
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uint64_t grp : 10;
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/* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
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* when CPT submits work to SSO.
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*/
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uint64_t tt : 2;
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/* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
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* CPT submits work to SSO.
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*/
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uint64_t tag : 32;
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#else /* Word 2 - Little Endian */
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uint64_t tag : 32;
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uint64_t tt : 2;
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uint64_t grp : 10;
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uint64_t reserved_172_191 : 20;
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#endif /* Word 2 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
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/** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
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* work-queue entry that CPT submits work to SSO after all
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* context, output data, and result write operations are
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* visible to other CNXXXX units and the cores.
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* Bits <2:0> must be zero.
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* Bits <63:49> are ignored by hardware; software should use a
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* sign-extended bit <48> for forward compatibility.
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* Internal:Bits <63:49>, <2:0> are ignored by hardware,
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* treated as always 0x0.
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**/
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uint64_t wq_ptr : 64;
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#else /* Word 3 - Little Endian */
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uint64_t wq_ptr : 64;
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#endif /* Word 3 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
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union {
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/** [319:256] Engine instruction word 0. Passed to the
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* AE/SE.
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**/
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uint64_t ei0 : 64;
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vq_cmd_word0_t vq_cmd_w0;
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};
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#else /* Word 4 - Little Endian */
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union {
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uint64_t ei0 : 64;
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vq_cmd_word0_t vq_cmd_w0;
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};
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#endif /* Word 4 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
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union {
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/** [383:320] Engine instruction word 1. Passed to the
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* AE/SE.
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**/
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uint64_t ei1 : 64;
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uint64_t dptr;
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};
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#else /* Word 5 - Little Endian */
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union {
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uint64_t ei1 : 64;
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uint64_t dptr;
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};
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#endif /* Word 5 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
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union {
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/** [447:384] Engine instruction word 2. Passed to the
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* AE/SE.
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**/
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uint64_t ei2 : 64;
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uint64_t rptr;
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};
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#else /* Word 6 - Little Endian */
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union {
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uint64_t ei2 : 64;
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uint64_t rptr;
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};
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#endif /* Word 6 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
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union {
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/** [511:448] Engine instruction word 3. Passed to the
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* AE/SE.
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**/
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uint64_t ei3 : 64;
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vq_cmd_word3_t vq_cmd_w3;
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};
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#else /* Word 7 - Little Endian */
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union {
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uint64_t ei3 : 64;
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vq_cmd_word3_t vq_cmd_w3;
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};
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#endif /* Word 7 - End */
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} s8x;
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} cpt_inst_s_t;
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/**
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* Structure cpt_res_s
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*
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* CPT Result Structure
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* The CPT coprocessor writes the result structure after it completes a
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* CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
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* instruction completion produces exactly one result structure.
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*
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* This structure is stored in memory as little-endian unless
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* CPT()_PF_Q()_CTL[INST_BE] is set.
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*/
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typedef union cpt_res_s {
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uint64_t u[2];
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struct cpt_res_s_8s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_17_63 : 47;
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/** [ 16: 16] Done interrupt. This bit is copied from the
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* corresponding instruction's CPT_INST_S[DONEINT].
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**/
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uint64_t doneint : 1;
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uint64_t reserved_8_15 : 8;
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/** [ 7: 0] Indicates completion/error status of the CPT
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* coprocessor for the associated instruction, as enumerated by
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* CPT_COMP_E. Core software may write the memory location
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* containing [COMPCODE] to 0x0 before ringing the doorbell, and
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* then poll for completion by checking for a nonzero value.
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*
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* Once the core observes a nonzero [COMPCODE] value in this
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* case, the CPT coprocessor will have also completed L2/DRAM
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* write operations.
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**/
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uint64_t compcode : 8;
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#else /* Word 0 - Little Endian */
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uint64_t compcode : 8;
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uint64_t reserved_8_15 : 8;
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uint64_t doneint : 1;
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uint64_t reserved_17_63 : 47;
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#endif /* Word 0 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
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uint64_t reserved_64_127 : 64;
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#else /* Word 1 - Little Endian */
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uint64_t reserved_64_127 : 64;
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#endif /* Word 1 - End */
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} s8x;
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} cpt_res_s_t;
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/**
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* Register (NCB) cpt#_vq#_ctl
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*
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* CPT VF Queue Control Registers
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* This register configures queues. This register should be changed (other than
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* clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
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*/
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typedef union {
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uint64_t u;
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struct cptx_vqx_ctl_s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_1_63 : 63;
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/** [ 0: 0](R/W/H) Enables the logical instruction queue.
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* See also CPT()_PF_Q()_CTL[CONT_ERR] and
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* CPT()_VQ()_INPROG[INFLIGHT].
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* 1 = Queue is enabled.
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* 0 = Queue is disabled.
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**/
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uint64_t ena : 1;
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#else /* Word 0 - Little Endian */
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uint64_t ena : 1;
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uint64_t reserved_1_63 : 63;
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#endif /* Word 0 - End */
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} s;
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} cptx_vqx_ctl_t;
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/**
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* Register (NCB) cpt#_vq#_done
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*
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* CPT Queue Done Count Registers
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* These registers contain the per-queue instruction done count.
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*/
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typedef union {
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uint64_t u;
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struct cptx_vqx_done_s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_20_63 : 44;
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/** [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
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* and that instruction completes,CPT()_VQ()_DONE[DONE] is
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* incremented when the instruction finishes. Write to this
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* field are for diagnostic use only; instead software writes
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* CPT()_VQ()_DONE_ACK with the number of decrements for this
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* field.
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*
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* Interrupts are sent as follows:
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*
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* When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
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* the interrupt coalescing timer is held to zero, and an
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* interrupt is not sent.
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*
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* When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
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* coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
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* _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
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* _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
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* results have arrived, then the interrupt is sent. Otherwise,
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* it is not sent due to coalescing.
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*
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* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
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* written but this is not typical), the interrupt coalescing
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* timer restarts. Note after decrementing this interrupt
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* equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
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* >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
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* zero, the interrupt will be resent immediately. (This covers
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* the race case between software acknowledging an interrupt and
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* a result returning.)
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*
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* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
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* sent, but the counting described above still occurs.
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*
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* Since CPT instructions complete out-of-order, if software is
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* using completion interrupts the suggested scheme is to
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* request a DONEINT on each request, and when an interrupt
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* arrives perform a "greedy" scan for completions; even if a
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* later command is acknowledged first this will not result in
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* missing a completion.
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*
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* Software is responsible for making sure [DONE] does not
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* overflow; for example by insuring there are not more than
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* 2^20-1 instructions in flight that may request interrupts.
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**/
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uint64_t done : 20;
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#else /* Word 0 - Little Endian */
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uint64_t done : 20;
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uint64_t reserved_20_63 : 44;
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#endif /* Word 0 - End */
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} s;
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} cptx_vqx_done_t;
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/**
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* Register (NCB) cpt#_vq#_done_ack
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*
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* CPT Queue Done Count Ack Registers
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* This register is written by software to acknowledge interrupts.
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*/
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typedef union {
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uint64_t u;
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struct cptx_vqx_done_ack_s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_20_63 : 44;
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/** [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE
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* [DONE]. Reads CPT()_VQ()_DONE[DONE].
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*
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* Written by software to acknowledge interrupts. If CPT()_VQ()_
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* DONE[DONE] is still nonzero the interrupt will be re-sent if
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* the conditions described in CPT()_VQ()_DONE[DONE] are
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* satisfied.
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**/
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uint64_t done_ack : 20;
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#else /* Word 0 - Little Endian */
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uint64_t done_ack : 20;
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uint64_t reserved_20_63 : 44;
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#endif /* Word 0 - End */
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} s;
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} cptx_vqx_done_ack_t;
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/**
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* Register (NCB) cpt#_vq#_done_wait
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*
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* CPT Queue Done Interrupt Coalescing Wait Registers
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* Specifies the per queue interrupt coalescing settings.
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*/
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typedef union {
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uint64_t u;
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struct cptx_vqx_done_wait_s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_48_63 : 16;
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/** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
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* 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
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* the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
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* ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
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* disabled.
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**/
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uint64_t time_wait : 16;
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uint64_t reserved_20_31 : 12;
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/** [ 19: 0](R/W) Number of messages hold-off. When
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* CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
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* ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
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* 0x1.
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**/
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uint64_t num_wait : 20;
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#else /* Word 0 - Little Endian */
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uint64_t num_wait : 20;
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uint64_t reserved_20_31 : 12;
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uint64_t time_wait : 16;
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uint64_t reserved_48_63 : 16;
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#endif /* Word 0 - End */
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} s;
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} cptx_vqx_done_wait_t;
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/**
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* Register (NCB) cpt#_vq#_doorbell
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*
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* CPT Queue Doorbell Registers
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* Doorbells for the CPT instruction queues.
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*/
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typedef union {
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uint64_t u;
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struct cptx_vqx_doorbell_s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_20_63 : 44;
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uint64_t dbell_cnt : 20;
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/** [ 19: 0](R/W/H) Number of instruction queue 64-bit words
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* to add to the CPT instruction doorbell count. Readback value
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* is the the current number of pending doorbell requests.
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*
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* If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
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*
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* To reset the count back to zero, write one to clear
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* CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value
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* of 2^20 minus the read [DBELL_CNT], then write one to
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* CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
|
||||
* CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
|
||||
*
|
||||
* Must be a multiple of 8. All CPT instructions are 8 words
|
||||
* and require a doorbell count of multiple of 8.
|
||||
**/
|
||||
#else /* Word 0 - Little Endian */
|
||||
uint64_t dbell_cnt : 20;
|
||||
uint64_t reserved_20_63 : 44;
|
||||
#endif /* Word 0 - End */
|
||||
} s;
|
||||
} cptx_vqx_doorbell_t;
|
||||
|
||||
/**
|
||||
* Register (NCB) cpt#_vq#_inprog
|
||||
*
|
||||
* CPT Queue In Progress Count Registers
|
||||
* These registers contain the per-queue instruction in flight registers.
|
||||
*/
|
||||
typedef union {
|
||||
uint64_t u;
|
||||
struct cptx_vqx_inprog_s {
|
||||
#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
|
||||
uint64_t reserved_8_63 : 56;
|
||||
/** [ 7: 0](RO/H) Inflight count. Counts the number of
|
||||
* instructions for the VF for which CPT is fetching, executing
|
||||
* or responding to instructions. However this does not include
|
||||
* any interrupts that are awaiting software handling
|
||||
* (CPT()_VQ()_DONE[DONE] != 0x0).
|
||||
*
|
||||
* A queue may not be reconfigured until:
|
||||
* 1. CPT()_VQ()_CTL[ENA] is cleared by software.
|
||||
* 2. [INFLIGHT] is polled until equals to zero.
|
||||
**/
|
||||
uint64_t inflight : 8;
|
||||
#else /* Word 0 - Little Endian */
|
||||
uint64_t inflight : 8;
|
||||
uint64_t reserved_8_63 : 56;
|
||||
#endif /* Word 0 - End */
|
||||
} s;
|
||||
} cptx_vqx_inprog_t;
|
||||
|
||||
/**
|
||||
* Register (NCB) cpt#_vq#_misc_int
|
||||
*
|
||||
* CPT Queue Misc Interrupt Register
|
||||
* These registers contain the per-queue miscellaneous interrupts.
|
||||
*/
|
||||
typedef union {
|
||||
uint64_t u;
|
||||
struct cptx_vqx_misc_int_s {
|
||||
#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
|
||||
uint64_t reserved_7_63 : 57;
|
||||
/** [ 6: 6](R/W1C/H) Translation fault detected. */
|
||||
uint64_t fault : 1;
|
||||
/** [ 5: 5](R/W1C/H) Hardware error from engines. */
|
||||
uint64_t hwerr : 1;
|
||||
/** [ 4: 4](R/W1C/H) Software error from engines. */
|
||||
uint64_t swerr : 1;
|
||||
/** [ 3: 3](R/W1C/H) NCB result write response error. */
|
||||
uint64_t nwrp : 1;
|
||||
/** [ 2: 2](R/W1C/H) Instruction NCB read response error. */
|
||||
uint64_t irde : 1;
|
||||
/** [ 1: 1](R/W1C/H) Doorbell overflow. */
|
||||
uint64_t dovf : 1;
|
||||
/** [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when
|
||||
* CPT()_VF()_PF_MBOX(0) is written.
|
||||
**/
|
||||
uint64_t mbox : 1;
|
||||
#else /* Word 0 - Little Endian */
|
||||
uint64_t mbox : 1;
|
||||
uint64_t dovf : 1;
|
||||
uint64_t irde : 1;
|
||||
uint64_t nwrp : 1;
|
||||
uint64_t swerr : 1;
|
||||
uint64_t hwerr : 1;
|
||||
uint64_t fault : 1;
|
||||
uint64_t reserved_5_63 : 59;
|
||||
#endif /* Word 0 - End */
|
||||
} s;
|
||||
} cptx_vqx_misc_int_t;
|
||||
|
||||
/**
|
||||
* Register (NCB) cpt#_vq#_saddr
|
||||
*
|
||||
* CPT Queue Starting Buffer Address Registers
|
||||
* These registers set the instruction buffer starting address.
|
||||
*/
|
||||
typedef union {
|
||||
uint64_t u;
|
||||
struct cptx_vqx_saddr_s {
|
||||
#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
|
||||
uint64_t reserved_49_63 : 15;
|
||||
/** [ 48: 6](R/W/H) Instruction buffer IOVA <48:6>
|
||||
* (64-byte aligned). When written, it is the initial buffer
|
||||
* starting address; when read, it is the next read pointer to
|
||||
* be requested from L2C. The PTR field is overwritten with the
|
||||
* next pointer each time that the command buffer segment is
|
||||
* exhausted. New commands will then be read from the newly
|
||||
* specified command buffer pointer.
|
||||
**/
|
||||
uint64_t ptr : 43;
|
||||
uint64_t reserved_0_5 : 6;
|
||||
#else /* Word 0 - Little Endian */
|
||||
uint64_t reserved_0_5 : 6;
|
||||
uint64_t ptr : 43;
|
||||
uint64_t reserved_49_63 : 15;
|
||||
#endif /* Word 0 - End */
|
||||
} s;
|
||||
} cptx_vqx_saddr_t;
|
||||
|
||||
#endif /*_CPT_HW_TYPES_H_ */
|
||||
@ -3,11 +3,19 @@
|
||||
*/
|
||||
#include <string.h>
|
||||
|
||||
#include <rte_branch_prediction.h>
|
||||
#include <rte_common.h>
|
||||
|
||||
#include "otx_cryptodev_hw_access.h"
|
||||
|
||||
#include "cpt_pmd_logs.h"
|
||||
#include "cpt_hw_types.h"
|
||||
|
||||
/*
|
||||
* VF HAL functions
|
||||
* Access its own BAR0/4 registers by passing VF number as 0.
|
||||
* OS/PCI maps them accordingly.
|
||||
*/
|
||||
|
||||
static int
|
||||
otx_cpt_vf_init(struct cpt_vf *cptvf)
|
||||
@ -19,10 +27,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read Interrupt status of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static uint64_t
|
||||
otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)
|
||||
{
|
||||
return CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear mailbox interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.mbox = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear instruction NCB read error interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.irde = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear NCB result write response error interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.nwrp = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear swerr interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.swerr = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear hwerr interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.hwerr = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear translation fault interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.fault = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear doorbell overflow interrupt of the VF
|
||||
*
|
||||
* @param cptvf cptvf structure
|
||||
*/
|
||||
static void
|
||||
otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)
|
||||
{
|
||||
cptx_vqx_misc_int_t vqx_misc_int;
|
||||
|
||||
vqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0));
|
||||
/* W1C for the VF */
|
||||
vqx_misc_int.s.dovf = 1;
|
||||
CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
|
||||
CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
|
||||
}
|
||||
|
||||
void
|
||||
otx_cpt_poll_misc(struct cpt_vf *cptvf)
|
||||
{
|
||||
RTE_SET_USED(cptvf);
|
||||
uint64_t intr;
|
||||
|
||||
intr = otx_cpt_read_vf_misc_intr_status(cptvf);
|
||||
|
||||
if (!intr)
|
||||
return;
|
||||
|
||||
/* Check for MISC interrupt types */
|
||||
if (likely(intr & CPT_VF_INTR_MBOX_MASK)) {
|
||||
CPT_LOG_DP_DEBUG("%s: Mailbox interrupt 0x%lx on CPT VF %d",
|
||||
cptvf->dev_name, (unsigned int long)intr, cptvf->vfid);
|
||||
otx_cpt_clear_mbox_intr(cptvf);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {
|
||||
otx_cpt_clear_irde_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: Instruction NCB read error interrupt "
|
||||
"0x%lx on CPT VF %d", cptvf->dev_name,
|
||||
(unsigned int long)intr, cptvf->vfid);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {
|
||||
otx_cpt_clear_nwrp_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: NCB response write error interrupt 0x%lx"
|
||||
" on CPT VF %d", cptvf->dev_name,
|
||||
(unsigned int long)intr, cptvf->vfid);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {
|
||||
otx_cpt_clear_swerr_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: Software error interrupt 0x%lx on CPT VF "
|
||||
"%d", cptvf->dev_name, (unsigned int long)intr,
|
||||
cptvf->vfid);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {
|
||||
otx_cpt_clear_hwerr_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: Hardware error interrupt 0x%lx on CPT VF "
|
||||
"%d", cptvf->dev_name, (unsigned int long)intr,
|
||||
cptvf->vfid);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {
|
||||
otx_cpt_clear_fault_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: Translation fault interrupt 0x%lx on CPT VF "
|
||||
"%d", cptvf->dev_name, (unsigned int long)intr,
|
||||
cptvf->vfid);
|
||||
} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {
|
||||
otx_cpt_clear_dovf_intr(cptvf);
|
||||
CPT_LOG_DP_DEBUG("%s: Doorbell overflow interrupt 0x%lx on CPT VF "
|
||||
"%d", cptvf->dev_name, (unsigned int long)intr,
|
||||
cptvf->vfid);
|
||||
} else
|
||||
CPT_LOG_DP_ERR("%s: Unhandled interrupt 0x%lx in CPT VF %d",
|
||||
cptvf->dev_name, (unsigned int long)intr,
|
||||
cptvf->vfid);
|
||||
}
|
||||
|
||||
int
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <rte_io.h>
|
||||
#include <rte_memory.h>
|
||||
|
||||
#include "cpt_common.h"
|
||||
@ -16,6 +17,16 @@
|
||||
/* Default command queue length */
|
||||
#define DEFAULT_CMD_QCHUNKS 2
|
||||
|
||||
#define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)
|
||||
|
||||
/* Read hw register */
|
||||
#define CPT_READ_CSR(__hw_addr, __offset) \
|
||||
rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
|
||||
|
||||
/* Write hw register */
|
||||
#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
|
||||
rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
|
||||
|
||||
/* cpt instance */
|
||||
struct cpt_instance {
|
||||
uint32_t queue_id;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user