config: set cache line as 128B for generic arm64

armv8 implementations may have 64B or 128B cache line.
Setting to the maximum available cache line size in generic config to
address minimum DMA alignment across all arm64 implementations.

Increasing the cacheline size has no negative impact to cache invalidation
on systems with a smaller cache line.

The need for the minimum DMA alignment has impact on functional aspects
of the platform so default config should cater the functional aspects.

There is an impact on memory usage with this scheme, but that's not too
important for the single image arm64 distribution use case.

The arm64 linux kernel followed the similar approach for single
arm64 image use case.
http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>

config/defconfig_arm64-armv8a-linuxapp-gcc

@@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y
 CONFIG_RTE_TOOLCHAIN="gcc"
 CONFIG_RTE_TOOLCHAIN_GCC=y
 
+# Maximum available cache line size in arm64 implementations.
+# Setting to maximum available cache line size in generic config
+# to address minimum DMA alignment across all arm64 implementations.
+CONFIG_RTE_CACHE_LINE_SIZE=128
+
 CONFIG_RTE_EAL_IGB_UIO=n
 
 CONFIG_RTE_LIBRTE_FM10K_PMD=n

config/defconfig_arm64-dpaa2-linuxapp-gcc

@@ -41,6 +41,7 @@ CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd"
 #
 CONFIG_RTE_MAX_LCORE=8
 CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_CACHE_LINE_SIZE=64
 
 CONFIG_RTE_PKTMBUF_HEADROOM=256
 

config/defconfig_arm64-xgene1-linuxapp-gcc

@@ -32,3 +32,4 @@
 #include "defconfig_arm64-armv8a-linuxapp-gcc"
 
 CONFIG_RTE_MACHINE="xgene1"
+CONFIG_RTE_CACHE_LINE_SIZE=64