common/cnxk: add BPHY communication with atf
Messages can be exchanged between userspace software and firmware via set of two dedicated registers, namely scratch1 and scratch0. scratch1 acts as a command register i.e message is sent to firmware, while scratch0 holds response to previously sent message. Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Jakub Palider <jpalider@marvell.com> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Tomasz Duszynski
Thomas Monjalon
parent
0399ff9d2b
commit
857721d62d
@ -2,8 +2,13 @@
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* Copyright(C) 2021 Marvell.
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*/
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#include "roc_api.h"
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#include <pthread.h>
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#include "roc_api.h"
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#include "roc_priv.h"
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#define CGX_CMRX_INT 0x40
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#define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
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/*
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* CN10K stores number of lmacs in 4 bit filed
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* in contraty to CN9K which uses only 3 bits.
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@ -15,6 +20,8 @@
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*/
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#define CGX_CMRX_RX_LMACS 0x128
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#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
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#define CGX_CMRX_SCRATCH0 0x1050
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#define CGX_CMRX_SCRATCH1 0x1058
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static uint64_t
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roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
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@ -25,6 +32,138 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
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return plt_read64(base + (lmac << shift) + offset);
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}
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static void
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roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
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uint64_t value)
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{
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int shift = roc_model_is_cn10k() ? 20 : 18;
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uint64_t base = (uint64_t)roc_cgx->bar0_va;
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plt_write64(value, base + (lmac << shift) + offset);
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}
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static void
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roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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uint64_t val;
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/* clear interrupt */
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val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
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val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
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/* ack fw response */
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*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
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}
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static int
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roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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int tries = 5000;
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uint64_t scr1;
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do {
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*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
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scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
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if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
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break;
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/* clear async events if any */
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
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ETH_EVT_ASYNC &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
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roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
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plt_delay_ms(1);
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} while (--tries);
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return tries ? 0 : -ETIMEDOUT;
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}
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static int
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roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t *scr0)
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{
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int tries = 5000;
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uint64_t scr1;
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do {
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*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
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scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
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if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
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FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
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break;
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plt_delay_ms(1);
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} while (--tries);
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return tries ? 0 : -ETIMEDOUT;
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}
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static int __rte_unused
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roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
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uint64_t scr1, uint64_t *scr0)
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{
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uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
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int ret;
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pthread_mutex_lock(&roc_cgx->lock);
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/* wait for ownership */
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ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
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if (ret) {
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plt_err("timed out waiting for ownership");
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goto out;
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}
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/* write command */
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scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
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roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
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/* wait for command ack */
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ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
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if (ret) {
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plt_err("timed out waiting for response");
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goto out;
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}
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if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
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goto out;
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
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plt_err("received async event instead of cmd resp event");
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ret = -EIO;
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goto out;
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}
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
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plt_err("received resp for cmd %d expected for cmd %d",
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(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
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ret = -EIO;
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goto out;
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}
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if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
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plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
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roc_cgx->id, lmac,
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(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
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ret = -EIO;
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}
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out:
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roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
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pthread_mutex_unlock(&roc_cgx->lock);
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return ret;
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}
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static unsigned int
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roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
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{
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@ -38,10 +177,15 @@ int
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roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
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{
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uint64_t val;
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int ret;
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if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
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return -EINVAL;
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ret = pthread_mutex_init(&roc_cgx->lock, NULL);
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if (ret)
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return ret;
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val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
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val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
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if (roc_model_is_cn9k())
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@ -58,5 +202,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
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if (!roc_cgx)
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return -EINVAL;
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pthread_mutex_destroy(&roc_cgx->lock);
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return 0;
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}
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@ -5,6 +5,8 @@
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#ifndef _ROC_BPHY_CGX_H_
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#define _ROC_BPHY_CGX_H_
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#include <pthread.h>
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#include "roc_api.h"
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struct roc_bphy_cgx {
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@ -12,6 +14,8 @@ struct roc_bphy_cgx {
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void *bar0_va;
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uint64_t lmac_bmap;
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unsigned int id;
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/* serialize access to the whole structure */
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pthread_mutex_t lock;
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} __plt_cache_aligned;
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__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
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54
drivers/common/cnxk/roc_bphy_cgx_priv.h
Normal file
54
drivers/common/cnxk/roc_bphy_cgx_priv.h
Normal file
@ -0,0 +1,54 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_BPHY_CGX_PRIV_H_
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#define _ROC_BPHY_CGX_PRIV_H_
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/* REQUEST ID types. Input to firmware */
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enum eth_cmd_id {
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ETH_CMD_INTF_SHUTDOWN = 12,
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};
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/* event types - cause of interrupt */
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enum eth_evt_type {
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ETH_EVT_ASYNC,
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ETH_EVT_CMD_RESP,
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};
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enum eth_stat {
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ETH_STAT_SUCCESS,
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ETH_STAT_FAIL,
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};
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enum eth_cmd_own {
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/* default ownership with kernel/uefi/u-boot */
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ETH_OWN_NON_SECURE_SW,
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/* set by kernel/uefi/u-boot after posting a new request to ATF */
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ETH_OWN_FIRMWARE,
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};
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/* scratchx(0) CSR used for ATF->non-secure SW communication.
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* This acts as the status register
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* Provides details on command ack/status, link status, error details
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*/
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/* struct eth_evt_sts_s */
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#define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0)
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#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
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#define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2)
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#define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3)
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/* struct eth_lnk_sts_s */
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#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
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/* scratchx(1) CSR used for non-secure SW->ATF communication
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* This CSR acts as a command register
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*/
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/* struct eth_cmd */
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#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
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#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
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#endif /* _ROC_BPHY_CGX_PRIV_H_ */
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@ -32,4 +32,7 @@
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/* TIM */
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#include "roc_tim_priv.h"
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/* BPHY CGX */
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#include "roc_bphy_cgx_priv.h"
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#endif /* _ROC_PRIV_H_ */
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