net/mlx5: add Direct Verbs prepare function
This function allocates the Direct Verbs device flow, and introduce the relevant PRM structures. This commit also adds the matcher object. The matcher object acts as a mask and should be shared between flows. For example all rules that should match source IP with full mask should use the same matcher. A flow that should match dest IP or source IP but without full mask should have a new matcher allocated. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
This commit is contained in:
Ori Kam
Ferruh Yigit
parent
3d69434113
commit
865a0c1567
@ -213,6 +213,7 @@ struct priv {
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LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
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/* Verbs Indirection tables. */
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LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
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LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
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uint32_t link_speed_capa; /* Link speed capabilities. */
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struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
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int primary_socket; /* Unix socket for primary process. */
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@ -108,6 +108,37 @@
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/* Max number of actions per DV flow. */
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#define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
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/* Matcher PRM representation */
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struct mlx5_flow_dv_match_params {
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size_t size;
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/**< Size of match value. Do NOT split size and key! */
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uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
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/**< Matcher value. This value is used as the mask or as a key. */
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};
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/* Matcher structure. */
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struct mlx5_flow_dv_matcher {
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LIST_ENTRY(mlx5_flow_dv_matcher) next;
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/* Pointer to the next element. */
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rte_atomic32_t refcnt; /**< Reference counter. */
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void *matcher_object; /**< Pointer to DV matcher */
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uint16_t crc; /**< CRC of key. */
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uint16_t priority; /**< Priority of matcher. */
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uint8_t egress; /**< Egress matcher. */
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struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
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};
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/* DV flows structure. */
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struct mlx5_flow_dv {
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uint64_t hash_fields; /**< Fields that participate in the hash. */
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struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
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/* Flow DV api: */
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struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
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struct mlx5_flow_dv_match_params value;
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/**< Holds the value that the packet is compared to. */
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struct ibv_flow *flow; /**< Installed flow. */
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};
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/* Verbs specification header. */
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struct ibv_spec_header {
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enum ibv_flow_spec_type type;
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@ -134,7 +165,8 @@ struct mlx5_flow {
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struct rte_flow *flow; /**< Pointer to the main flow. */
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uint32_t layers; /**< Bit-fields that holds the detected layers. */
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union {
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struct mlx5_flow_verbs verbs; /**< Holds the verbs dev-flow. */
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struct mlx5_flow_dv dv;
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struct mlx5_flow_verbs verbs;
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};
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};
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@ -294,6 +294,49 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
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return 0;
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}
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/**
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* Internal preparation function. Allocates the DV flow size,
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* this size is constant.
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*
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* @param[in] attr
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* Pointer to the flow attributes.
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* @param[in] items
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* Pointer to the list of items.
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* @param[in] actions
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* Pointer to the list of actions.
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* @param[out] item_flags
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* Pointer to bit mask of all items detected.
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* @param[out] action_flags
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* Pointer to bit mask of all actions detected.
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* @param[out] error
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* Pointer to the error structure.
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*
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* @return
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* Pointer to mlx5_flow object on success,
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* otherwise NULL and rte_ernno is set.
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*/
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static struct mlx5_flow *
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flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
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const struct rte_flow_item items[] __rte_unused,
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const struct rte_flow_action actions[] __rte_unused,
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uint64_t *item_flags __rte_unused,
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uint64_t *action_flags __rte_unused,
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struct rte_flow_error *error)
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{
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uint32_t size = sizeof(struct mlx5_flow);
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struct mlx5_flow *flow;
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flow = rte_calloc(__func__, 1, size, 0);
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if (!flow) {
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rte_flow_error_set(error, ENOMEM,
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RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
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"not enough memory to create flow");
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return NULL;
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}
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flow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);
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return flow;
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}
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/**
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* Fills the flow_ops with the function pointers.
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*
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@ -305,7 +348,7 @@ mlx5_flow_dv_get_driver_ops(struct mlx5_flow_driver_ops *flow_ops)
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{
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*flow_ops = (struct mlx5_flow_driver_ops) {
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.validate = flow_dv_validate,
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.prepare = NULL,
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.prepare = flow_dv_prepare,
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.translate = NULL,
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.apply = NULL,
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.remove = NULL,
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@ -280,6 +280,219 @@ struct mlx5_cqe {
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/* CQE format value. */
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#define MLX5_COMPRESSED 0x3
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/* The field of packet to be modified. */
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enum mlx5_modificaiton_field {
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MLX5_MODI_OUT_SMAC_47_16 = 1,
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MLX5_MODI_OUT_SMAC_15_0,
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MLX5_MODI_OUT_ETHERTYPE,
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MLX5_MODI_OUT_DMAC_47_16,
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MLX5_MODI_OUT_DMAC_15_0,
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MLX5_MODI_OUT_IP_DSCP,
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MLX5_MODI_OUT_TCP_FLAGS,
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MLX5_MODI_OUT_TCP_SPORT,
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MLX5_MODI_OUT_TCP_DPORT,
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MLX5_MODI_OUT_IPV4_TTL,
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MLX5_MODI_OUT_UDP_SPORT,
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MLX5_MODI_OUT_UDP_DPORT,
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MLX5_MODI_OUT_SIPV6_127_96,
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MLX5_MODI_OUT_SIPV6_95_64,
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MLX5_MODI_OUT_SIPV6_63_32,
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MLX5_MODI_OUT_SIPV6_31_0,
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MLX5_MODI_OUT_DIPV6_127_96,
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MLX5_MODI_OUT_DIPV6_95_64,
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MLX5_MODI_OUT_DIPV6_63_32,
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MLX5_MODI_OUT_DIPV6_31_0,
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MLX5_MODI_OUT_SIPV4,
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MLX5_MODI_OUT_DIPV4,
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MLX5_MODI_IN_SMAC_47_16 = 0x31,
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MLX5_MODI_IN_SMAC_15_0,
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MLX5_MODI_IN_ETHERTYPE,
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MLX5_MODI_IN_DMAC_47_16,
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MLX5_MODI_IN_DMAC_15_0,
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MLX5_MODI_IN_IP_DSCP,
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MLX5_MODI_IN_TCP_FLAGS,
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MLX5_MODI_IN_TCP_SPORT,
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MLX5_MODI_IN_TCP_DPORT,
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MLX5_MODI_IN_IPV4_TTL,
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MLX5_MODI_IN_UDP_SPORT,
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MLX5_MODI_IN_UDP_DPORT,
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MLX5_MODI_IN_SIPV6_127_96,
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MLX5_MODI_IN_SIPV6_95_64,
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MLX5_MODI_IN_SIPV6_63_32,
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MLX5_MODI_IN_SIPV6_31_0,
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MLX5_MODI_IN_DIPV6_127_96,
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MLX5_MODI_IN_DIPV6_95_64,
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MLX5_MODI_IN_DIPV6_63_32,
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MLX5_MODI_IN_DIPV6_31_0,
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MLX5_MODI_IN_SIPV4,
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MLX5_MODI_IN_DIPV4,
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MLX5_MODI_OUT_IPV6_HOPLIMIT,
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MLX5_MODI_IN_IPV6_HOPLIMIT,
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MLX5_MODI_META_DATA_REG_A,
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MLX5_MODI_META_DATA_REG_B = 0x50,
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};
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/* Modification sub command. */
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struct mlx5_modification_cmd {
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union {
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uint32_t data0;
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struct {
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unsigned int bits:5;
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unsigned int rsvd0:3;
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unsigned int src_offset:5; /* Start bit offset. */
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unsigned int rsvd1:3;
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unsigned int src_field:12;
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unsigned int type:4;
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};
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};
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union {
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uint32_t data1;
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uint8_t data[4];
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struct {
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unsigned int rsvd2:8;
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unsigned int dst_offset:8;
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unsigned int dst_field:12;
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unsigned int rsvd3:4;
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};
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};
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};
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
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#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
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#define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
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(&(__mlx5_nullp(typ)->fld)))
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#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
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(__mlx5_bit_off(typ, fld) & 0x1f))
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#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
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#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
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__mlx5_dw_bit_off(typ, fld))
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#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
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#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
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#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
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(__mlx5_bit_off(typ, fld) & 0xf))
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#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
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#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
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#define MLX5_ST_SZ_DB(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
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#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
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#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
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/* insert a value to a struct */
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#define MLX5_SET(typ, p, fld, v) \
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do { \
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u32 _v = v; \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
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__mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | \
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(((_v) & __mlx5_mask(typ, fld)) << \
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__mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_GET16(typ, p, fld) \
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((rte_be_to_cpu_16(*((__be16 *)(p) + \
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__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
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__mlx5_mask16(typ, fld))
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#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
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struct mlx5_ifc_fte_match_set_misc_bits {
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u8 reserved_at_0[0x8];
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u8 source_sqn[0x18];
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u8 reserved_at_20[0x10];
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u8 source_port[0x10];
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u8 outer_second_prio[0x3];
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u8 outer_second_cfi[0x1];
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u8 outer_second_vid[0xc];
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u8 inner_second_prio[0x3];
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u8 inner_second_cfi[0x1];
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u8 inner_second_vid[0xc];
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u8 outer_second_cvlan_tag[0x1];
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u8 inner_second_cvlan_tag[0x1];
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u8 outer_second_svlan_tag[0x1];
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u8 inner_second_svlan_tag[0x1];
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u8 reserved_at_64[0xc];
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u8 gre_protocol[0x10];
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u8 gre_key_h[0x18];
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u8 gre_key_l[0x8];
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u8 vxlan_vni[0x18];
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u8 reserved_at_b8[0x8];
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u8 reserved_at_c0[0x20];
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u8 reserved_at_e0[0xc];
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u8 outer_ipv6_flow_label[0x14];
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u8 reserved_at_100[0xc];
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u8 inner_ipv6_flow_label[0x14];
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u8 reserved_at_120[0xe0];
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};
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struct mlx5_ifc_ipv4_layout_bits {
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u8 reserved_at_0[0x60];
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u8 ipv4[0x20];
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};
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struct mlx5_ifc_ipv6_layout_bits {
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u8 ipv6[16][0x8];
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};
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union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
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struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
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struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
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u8 reserved_at_0[0x80];
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};
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struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
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u8 smac_47_16[0x20];
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u8 smac_15_0[0x10];
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u8 ethertype[0x10];
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u8 dmac_47_16[0x20];
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u8 dmac_15_0[0x10];
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u8 first_prio[0x3];
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u8 first_cfi[0x1];
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u8 first_vid[0xc];
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u8 ip_protocol[0x8];
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u8 ip_dscp[0x6];
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u8 ip_ecn[0x2];
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u8 cvlan_tag[0x1];
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u8 svlan_tag[0x1];
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u8 frag[0x1];
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u8 ip_version[0x4];
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u8 tcp_flags[0x9];
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u8 tcp_sport[0x10];
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u8 tcp_dport[0x10];
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u8 reserved_at_c0[0x20];
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u8 udp_sport[0x10];
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u8 udp_dport[0x10];
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union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
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union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
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};
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struct mlx5_ifc_fte_match_mpls_bits {
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u8 mpls_label[0x14];
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u8 mpls_exp[0x3];
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u8 mpls_s_bos[0x1];
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u8 mpls_ttl[0x8];
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};
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struct mlx5_ifc_fte_match_set_misc2_bits {
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struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
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struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
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struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
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struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
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u8 reserved_at_80[0x100];
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u8 metadata_reg_a[0x20];
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u8 reserved_at_1a0[0x60];
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};
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/* Flow matcher. */
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struct mlx5_ifc_fte_match_param_bits {
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struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
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struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
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struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
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struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
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u8 reserved_at_800[0x800];
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};
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/* CQE format mask. */
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#define MLX5E_CQE_FORMAT_MASK 0xc
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