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net/atlantic: implement firmware operations

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AQC NICs comes in fields with two major
FW generations: 1x and 3x.

This is part of linux atlantic driver shared code,
responsible for internal NIC firmware interactions,
including link management ops, FW initialization,
various lifecycle features.

Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: Pavel Belous <pavel.belous@aquantia.com>
This commit is contained in:
Igor Russkikh 2018-10-12 11:09:14 +00:00 committed by Ferruh Yigit
parent 31617c04e7
commit 86d36773bd
6 changed files with 2169 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/atlantic/Makefile
View File

@ -26,6 +26,8 @@ VPATH += $(SRCDIR)/hw_atl
#
SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c
SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c
SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c
SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c
SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c
include $(RTE_SDK)/mk/rte.lib.mk

95
drivers/net/atlantic/atl_types.h
View File

@ -22,8 +22,103 @@ typedef uint64_t u64;
#define min(a, b) RTE_MIN(a, b)
#define max(a, b) RTE_MAX(a, b)
#include "hw_atl/hw_atl_utils.h"
struct aq_hw_link_status_s {
unsigned int mbps;
};
struct aq_stats_s {
u64 uprc;
u64 mprc;
u64 bprc;
u64 erpt;
u64 uptc;
u64 mptc;
u64 bptc;
u64 erpr;
u64 mbtc;
u64 bbtc;
u64 mbrc;
u64 bbrc;
u64 ubrc;
u64 ubtc;
u64 dpc;
u64 dma_pkt_rc;
u64 dma_pkt_tc;
u64 dma_oct_rc;
u64 dma_oct_tc;
};
struct aq_hw_cfg_s {
bool is_lro;
int wol;
int link_speed_msk;
int irq_type;
int irq_mask;
unsigned int vecs;
uint32_t flow_control;
};
struct aq_hw_s {
u8 rbl_enabled:1;
struct aq_hw_cfg_s *aq_nic_cfg;
const struct aq_fw_ops *aq_fw_ops;
void *mmio;
struct aq_hw_link_status_s aq_link_status;
struct hw_aq_atl_utils_mbox mbox;
struct hw_atl_stats_s last_stats;
struct aq_stats_s curr_stats;
unsigned int chip_features;
u32 fw_ver_actual;
u32 mbox_addr;
u32 rpc_addr;
u32 rpc_tid;
struct hw_aq_atl_utils_fw_rpc rpc;
};
struct aq_fw_ops {
int (*init)(struct aq_hw_s *self);
int (*deinit)(struct aq_hw_s *self);
int (*reset)(struct aq_hw_s *self);
int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);
int (*set_link_speed)(struct aq_hw_s *self, u32 speed);
int (*set_state)(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state);
int (*update_link_status)(struct aq_hw_s *self);
int (*update_stats)(struct aq_hw_s *self);
int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
u8 *mac);
int (*get_temp)(struct aq_hw_s *self, int *temp);
int (*get_cable_len)(struct aq_hw_s *self, int *cable_len);
int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);
int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,
u32 *supported_rates);
int (*set_flow_control)(struct aq_hw_s *self);
int (*led_control)(struct aq_hw_s *self, u32 mode);
int (*get_eeprom)(struct aq_hw_s *self, u32 *data, u32 len);
int (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len);
};
#endif

942
drivers/net/atlantic/hw_atl/hw_atl_utils.c Normal file
View File

@ -0,0 +1,942 @@
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
/* Copyright (C) 2014-2017 aQuantia Corporation. */
/* File hw_atl_utils.c: Definition of common functions for Atlantic hardware
* abstraction layer.
*/
#include <stdio.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
#include <stdarg.h>
#include <inttypes.h>
#include <rte_ether.h>
#include "../atl_hw_regs.h"
#include "hw_atl_llh.h"
#include "hw_atl_llh_internal.h"
#include "../atl_logs.h"
#define HW_ATL_UCP_0X370_REG 0x0370U
#define HW_ATL_MIF_CMD 0x0200U
#define HW_ATL_MIF_ADDR 0x0208U
#define HW_ATL_MIF_VAL 0x020CU
#define HW_ATL_FW_SM_RAM 0x2U
#define HW_ATL_MPI_FW_VERSION 0x18
#define HW_ATL_MPI_CONTROL_ADR 0x0368U
#define HW_ATL_MPI_STATE_ADR 0x036CU
#define HW_ATL_MPI_STATE_MSK 0x00FFU
#define HW_ATL_MPI_STATE_SHIFT 0U
#define HW_ATL_MPI_SPEED_MSK 0x00FF0000U
#define HW_ATL_MPI_SPEED_SHIFT 16U
#define HW_ATL_MPI_DIRTY_WAKE_MSK 0x02000000U
#define HW_ATL_MPI_DAISY_CHAIN_STATUS 0x704
#define HW_ATL_MPI_BOOT_EXIT_CODE 0x388
#define HW_ATL_MAC_PHY_CONTROL 0x4000
#define HW_ATL_MAC_PHY_MPI_RESET_BIT 0x1D
#define HW_ATL_FW_VER_1X 0x01050006U
#define HW_ATL_FW_VER_2X 0x02000000U
#define HW_ATL_FW_VER_3X 0x03000000U
#define FORCE_FLASHLESS 0
static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state);
int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
{
int err = 0;
err = hw_atl_utils_soft_reset(self);
if (err)
return err;
hw_atl_utils_hw_chip_features_init(self,
&self->chip_features);
hw_atl_utils_get_fw_version(self, &self->fw_ver_actual);
if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X,
self->fw_ver_actual) == 0) {
*fw_ops = &aq_fw_1x_ops;
} else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_2X,
self->fw_ver_actual) == 0) {
*fw_ops = &aq_fw_2x_ops;
} else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_3X,
self->fw_ver_actual) == 0) {
*fw_ops = &aq_fw_2x_ops;
} else {
PMD_DRV_LOG(ERR, "Bad FW version detected: %x\n",
self->fw_ver_actual);
return -EOPNOTSUPP;
}
self->aq_fw_ops = *fw_ops;
err = self->aq_fw_ops->init(self);
return err;
}
static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self)
{
u32 gsr, val;
int k = 0;
aq_hw_write_reg(self, 0x404, 0x40e1);
AQ_HW_SLEEP(50);
/* Cleanup SPI */
val = aq_hw_read_reg(self, 0x53C);
aq_hw_write_reg(self, 0x53C, val | 0x10);
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000);
/* Kickstart MAC */
aq_hw_write_reg(self, 0x404, 0x80e0);
aq_hw_write_reg(self, 0x32a8, 0x0);
aq_hw_write_reg(self, 0x520, 0x1);
/* Reset SPI again because of possible interrupted SPI burst */
val = aq_hw_read_reg(self, 0x53C);
aq_hw_write_reg(self, 0x53C, val | 0x10);
AQ_HW_SLEEP(10);
/* Clear SPI reset state */
aq_hw_write_reg(self, 0x53C, val & ~0x10);
aq_hw_write_reg(self, 0x404, 0x180e0);
for (k = 0; k < 1000; k++) {
u32 flb_status = aq_hw_read_reg(self,
HW_ATL_MPI_DAISY_CHAIN_STATUS);
flb_status = flb_status & 0x10;
if (flb_status)
break;
AQ_HW_SLEEP(10);
}
if (k == 1000) {
PMD_DRV_LOG(ERR, "MAC kickstart failed\n");
return -EIO;
}
/* FW reset */
aq_hw_write_reg(self, 0x404, 0x80e0);
AQ_HW_SLEEP(50);
aq_hw_write_reg(self, 0x3a0, 0x1);
/* Kickstart PHY - skipped */
/* Global software reset*/
hw_atl_rx_rx_reg_res_dis_set(self, 0U);
hw_atl_tx_tx_reg_res_dis_set(self, 0U);
aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL,
BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT),
HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0);
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000);
for (k = 0; k < 1000; k++) {
u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
if (fw_state)
break;
AQ_HW_SLEEP(10);
}
if (k == 1000) {
PMD_DRV_LOG(ERR, "FW kickstart failed\n");
return -EIO;
}
/* Old FW requires fixed delay after init */
AQ_HW_SLEEP(15);
return 0;
}
static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self)
{
u32 gsr, val, rbl_status;
int k;
aq_hw_write_reg(self, 0x404, 0x40e1);
aq_hw_write_reg(self, 0x3a0, 0x1);
aq_hw_write_reg(self, 0x32a8, 0x0);
/* Alter RBL status */
aq_hw_write_reg(self, 0x388, 0xDEAD);
/* Cleanup SPI */
val = aq_hw_read_reg(self, 0x53C);
aq_hw_write_reg(self, 0x53C, val | 0x10);
/* Global software reset*/
hw_atl_rx_rx_reg_res_dis_set(self, 0U);
hw_atl_tx_tx_reg_res_dis_set(self, 0U);
aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL,
BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT),
HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0);
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR,
(gsr & 0xFFFFBFFF) | 0x8000);
if (FORCE_FLASHLESS)
aq_hw_write_reg(self, 0x534, 0x0);
aq_hw_write_reg(self, 0x404, 0x40e0);
/* Wait for RBL boot */
for (k = 0; k < 1000; k++) {
rbl_status = aq_hw_read_reg(self, 0x388) & 0xFFFF;
if (rbl_status && rbl_status != 0xDEAD)
break;
AQ_HW_SLEEP(10);
}
if (!rbl_status || rbl_status == 0xDEAD) {
PMD_DRV_LOG(ERR, "RBL Restart failed");
return -EIO;
}
/* Restore NVR */
if (FORCE_FLASHLESS)
aq_hw_write_reg(self, 0x534, 0xA0);
if (rbl_status == 0xF1A7) {
PMD_DRV_LOG(ERR, "No FW detected. Dynamic FW load not implemented\n");
return -EOPNOTSUPP;
}
for (k = 0; k < 1000; k++) {
u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
if (fw_state)
break;
AQ_HW_SLEEP(10);
}
if (k == 1000) {
PMD_DRV_LOG(ERR, "FW kickstart failed\n");
return -EIO;
}
/* Old FW requires fixed delay after init */
AQ_HW_SLEEP(15);
return 0;
}
int hw_atl_utils_soft_reset(struct aq_hw_s *self)
{
int err = 0;
int k;
u32 boot_exit_code = 0;
for (k = 0; k < 1000; ++k) {
u32 flb_status = aq_hw_read_reg(self,
HW_ATL_MPI_DAISY_CHAIN_STATUS);
boot_exit_code = aq_hw_read_reg(self,
HW_ATL_MPI_BOOT_EXIT_CODE);
if (flb_status != 0x06000000 || boot_exit_code != 0)
break;
}
if (k == 1000) {
PMD_DRV_LOG(ERR, "Neither RBL nor FLB firmware started\n");
return -EOPNOTSUPP;
}
self->rbl_enabled = (boot_exit_code != 0);
/* FW 1.x may bootup in an invalid POWER state (WOL feature).
* We should work around this by forcing its state back to DEINIT
*/
if (!hw_atl_utils_ver_match(HW_ATL_FW_VER_1X,
aq_hw_read_reg(self,
HW_ATL_MPI_FW_VERSION))) {
hw_atl_utils_mpi_set_state(self, MPI_DEINIT);
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) &
HW_ATL_MPI_STATE_MSK) == MPI_DEINIT,
10, 1000U);
}
if (self->rbl_enabled)
err = hw_atl_utils_soft_reset_rbl(self);
else
err = hw_atl_utils_soft_reset_flb(self);
return err;
}
int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
u32 *p, u32 cnt)
{
int err = 0;
AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,
HW_ATL_FW_SM_RAM) == 1U,
1U, 10000U);
if (err < 0) {
bool is_locked;
hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
if (!is_locked) {
err = -ETIMEDOUT;
goto err_exit;
}
}
aq_hw_write_reg(self, HW_ATL_MIF_ADDR, a);
for (++cnt; --cnt && !err;) {
aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U);
if (IS_CHIP_FEATURE(REVISION_B1))
AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self,
HW_ATL_MIF_ADDR),
1, 1000U);
else
AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self,
HW_ATL_MIF_CMD)),
1, 1000U);
*(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL);
a += 4;
}
hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
err_exit:
return err;
}
int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
u32 cnt)
{
int err = 0;
bool is_locked;
is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
if (!is_locked) {
err = -ETIMEDOUT;
goto err_exit;
}
if (IS_CHIP_FEATURE(REVISION_B1)) {
u32 offset = 0;
for (; offset < cnt; ++offset) {
aq_hw_write_reg(self, 0x328, p[offset]);
aq_hw_write_reg(self, 0x32C,
(0x80000000 | (0xFFFF & (offset * 4))));
hw_atl_mcp_up_force_intr_set(self, 1);
/* 1000 times by 10us = 10ms */
AQ_HW_WAIT_FOR((aq_hw_read_reg(self,
0x32C) & 0xF0000000) != 0x80000000,
10, 1000);
}
} else {
u32 offset = 0;
aq_hw_write_reg(self, 0x208, a);
for (; offset < cnt; ++offset) {
aq_hw_write_reg(self, 0x20C, p[offset]);
aq_hw_write_reg(self, 0x200, 0xC000);
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U)
& 0x100) == 0, 10, 1000);
}
}
hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
err_exit:
return err;
}
static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual)
{
int err = 0;
const u32 dw_major_mask = 0xff000000U;
const u32 dw_minor_mask = 0x00ffffffU;
err = (dw_major_mask & (ver_expected ^ ver_actual)) ? -EOPNOTSUPP : 0;
if (err < 0)
goto err_exit;
err = ((dw_minor_mask & ver_expected) > (dw_minor_mask & ver_actual)) ?
-EOPNOTSUPP : 0;
err_exit:
return err;
}
static int hw_atl_utils_init_ucp(struct aq_hw_s *self)
{
int err = 0;
if (!aq_hw_read_reg(self, 0x370U)) {
unsigned int rnd = (uint32_t)rte_rand();
unsigned int ucp_0x370 = 0U;
ucp_0x370 = 0x02020202U | (0xFEFEFEFEU & rnd);
aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
}
hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
/* check 10 times by 1ms */
AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
aq_hw_read_reg(self, 0x334U)), 1000U, 100U);
return err;
}
#define HW_ATL_RPC_CONTROL_ADR 0x0338U
#define HW_ATL_RPC_STATE_ADR 0x033CU
struct aq_hw_atl_utils_fw_rpc_tid_s {
union {
u32 val;
struct {
u16 tid;
u16 len;
};
};
};
#define hw_atl_utils_fw_rpc_init(_H_) hw_atl_utils_fw_rpc_wait(_H_, NULL)
int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size)
{
int err = 0;
struct aq_hw_atl_utils_fw_rpc_tid_s sw;
if (!IS_CHIP_FEATURE(MIPS)) {
err = -1;
goto err_exit;
}
err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
(u32 *)(void *)&self->rpc,
(rpc_size + sizeof(u32) -
sizeof(u8)) / sizeof(u32));
if (err < 0)
goto err_exit;
sw.tid = 0xFFFFU & (++self->rpc_tid);
sw.len = (u16)rpc_size;
aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val);
err_exit:
return err;
}
int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
struct hw_aq_atl_utils_fw_rpc **rpc)
{
int err = 0;
struct aq_hw_atl_utils_fw_rpc_tid_s sw;
struct aq_hw_atl_utils_fw_rpc_tid_s fw;
do {
sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR);
self->rpc_tid = sw.tid;
AQ_HW_WAIT_FOR(sw.tid ==
(fw.val =
aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR),
fw.tid), 1000U, 100U);
if (err < 0)
goto err_exit;
if (fw.len == 0xFFFFU) {
err = hw_atl_utils_fw_rpc_call(self, sw.len);
if (err < 0)
goto err_exit;
}
} while (sw.tid != fw.tid || 0xFFFFU == fw.len);
if (err < 0)
goto err_exit;
if (rpc) {
if (fw.len) {
err =
hw_atl_utils_fw_downld_dwords(self,
self->rpc_addr,
(u32 *)(void *)
&self->rpc,
(fw.len + sizeof(u32) -
sizeof(u8)) /
sizeof(u32));
if (err < 0)
goto err_exit;
}
*rpc = &self->rpc;
}
err_exit:
return err;
}
static int hw_atl_utils_mpi_create(struct aq_hw_s *self)
{
int err = 0;
err = hw_atl_utils_init_ucp(self);
if (err < 0)
goto err_exit;
err = hw_atl_utils_fw_rpc_init(self);
if (err < 0)
goto err_exit;
err_exit:
return err;
}
int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
struct hw_aq_atl_utils_mbox_header *pmbox)
{
return hw_atl_utils_fw_downld_dwords(self,
self->mbox_addr,
(u32 *)(void *)pmbox,
sizeof(*pmbox) / sizeof(u32));
}
void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
struct hw_aq_atl_utils_mbox *pmbox)
{
int err = 0;
err = hw_atl_utils_fw_downld_dwords(self,
self->mbox_addr,
(u32 *)(void *)pmbox,
sizeof(*pmbox) / sizeof(u32));
if (err < 0)
goto err_exit;
if (IS_CHIP_FEATURE(REVISION_A0)) {
unsigned int mtu = 1514;
pmbox->stats.ubrc = pmbox->stats.uprc * mtu;
pmbox->stats.ubtc = pmbox->stats.uptc * mtu;
} else {
pmbox->stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self);
}
err_exit:;
}
static
int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed)
{
u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
val = val & ~HW_ATL_MPI_SPEED_MSK;
val |= speed << HW_ATL_MPI_SPEED_SHIFT;
aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val);
return 0;
}
int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state)
{
int err = 0;
u32 transaction_id = 0;
struct hw_aq_atl_utils_mbox_header mbox;
u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
if (state == MPI_RESET) {
hw_atl_utils_mpi_read_mbox(self, &mbox);
transaction_id = mbox.transaction_id;
AQ_HW_WAIT_FOR(transaction_id !=
(hw_atl_utils_mpi_read_mbox(self, &mbox),
mbox.transaction_id),
1000U, 100U);
if (err < 0)
goto err_exit;
}
/* On interface DEINIT we disable DW (raise bit)
* Otherwise enable DW (clear bit)
*/
if (state == MPI_DEINIT || state == MPI_POWER)
val |= HW_ATL_MPI_DIRTY_WAKE_MSK;
else
val &= ~HW_ATL_MPI_DIRTY_WAKE_MSK;
/* Set new state bits */
val = val & ~HW_ATL_MPI_STATE_MSK;
val |= state & HW_ATL_MPI_STATE_MSK;
aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val);
err_exit:
return err;
}
int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self)
{
u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
u32 link_speed_mask = cp0x036C >> HW_ATL_MPI_SPEED_SHIFT;
struct aq_hw_link_status_s *link_status = &self->aq_link_status;
if (!link_speed_mask) {
link_status->mbps = 0U;
} else {
switch (link_speed_mask) {
case HAL_ATLANTIC_RATE_10G:
link_status->mbps = 10000U;
break;
case HAL_ATLANTIC_RATE_5G:
case HAL_ATLANTIC_RATE_5GSR:
link_status->mbps = 5000U;
break;
case HAL_ATLANTIC_RATE_2GS:
link_status->mbps = 2500U;
break;
case HAL_ATLANTIC_RATE_1G:
link_status->mbps = 1000U;
break;
case HAL_ATLANTIC_RATE_100M:
link_status->mbps = 100U;
break;
default:
return -EBUSY;
}
}
return 0;
}
static int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
u8 *mac)
{
int err = 0;
u32 h = 0U;
u32 l = 0U;
u32 mac_addr[2];
if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) {
unsigned int rnd = (uint32_t)rte_rand();
unsigned int ucp_0x370 = 0;
//get_random_bytes(&rnd, sizeof(unsigned int));
ucp_0x370 = 0x02020202 | (0xFEFEFEFE & rnd);
aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
}
err = hw_atl_utils_fw_downld_dwords(self,
aq_hw_read_reg(self, 0x00000374U) +
(40U * 4U),
mac_addr,
ARRAY_SIZE(mac_addr));
if (err < 0) {
mac_addr[0] = 0U;
mac_addr[1] = 0U;
err = 0;
} else {
mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
}
ether_addr_copy((struct ether_addr *)mac_addr,
(struct ether_addr *)mac);
if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
/* chip revision */
l = 0xE3000000U
| (0xFFFFU & aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG))
| (0x00 << 16);
h = 0x8001300EU;
mac[5] = (u8)(0xFFU & l);
l >>= 8;
mac[4] = (u8)(0xFFU & l);
l >>= 8;
mac[3] = (u8)(0xFFU & l);
l >>= 8;
mac[2] = (u8)(0xFFU & l);
mac[1] = (u8)(0xFFU & h);
h >>= 8;
mac[0] = (u8)(0xFFU & h);
}
return err;
}
unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps)
{
unsigned int ret = 0U;
switch (mbps) {
case 100U:
ret = 5U;
break;
case 1000U:
ret = 4U;
break;
case 2500U:
ret = 3U;
break;
case 5000U:
ret = 1U;
break;
case 10000U:
ret = 0U;
break;
default:
break;
}
return ret;
}
void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)
{
u32 chip_features = 0U;
u32 val = hw_atl_reg_glb_mif_id_get(self);
u32 mif_rev = val & 0xFFU;
if ((0xFU & mif_rev) == 1U) {
chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 |
HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
HAL_ATLANTIC_UTILS_CHIP_MIPS;
} else if ((0xFU & mif_rev) == 2U) {
chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 |
HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
HAL_ATLANTIC_UTILS_CHIP_MIPS |
HAL_ATLANTIC_UTILS_CHIP_TPO2 |
HAL_ATLANTIC_UTILS_CHIP_RPF2;
} else if ((0xFU & mif_rev) == 0xAU) {
chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 |
HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
HAL_ATLANTIC_UTILS_CHIP_MIPS |
HAL_ATLANTIC_UTILS_CHIP_TPO2 |
HAL_ATLANTIC_UTILS_CHIP_RPF2;
}
*p = chip_features;
}
static int hw_atl_fw1x_deinit(struct aq_hw_s *self)
{
hw_atl_utils_mpi_set_speed(self, 0);
hw_atl_utils_mpi_set_state(self, MPI_DEINIT);
return 0;
}
int hw_atl_utils_update_stats(struct aq_hw_s *self)
{
struct hw_aq_atl_utils_mbox mbox;
hw_atl_utils_mpi_read_stats(self, &mbox);
#define AQ_SDELTA(_N_) (self->curr_stats._N_ += \
mbox.stats._N_ - self->last_stats._N_)
if (1) {//self->aq_link_status.mbps) {
AQ_SDELTA(uprc);
AQ_SDELTA(mprc);
AQ_SDELTA(bprc);
AQ_SDELTA(erpt);
AQ_SDELTA(uptc);
AQ_SDELTA(mptc);
AQ_SDELTA(bptc);
AQ_SDELTA(erpr);
AQ_SDELTA(ubrc);
AQ_SDELTA(ubtc);
AQ_SDELTA(mbrc);
AQ_SDELTA(mbtc);
AQ_SDELTA(bbrc);
AQ_SDELTA(bbtc);
AQ_SDELTA(dpc);
}
#undef AQ_SDELTA
self->curr_stats.dma_pkt_rc =
hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self) +
((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32);
self->curr_stats.dma_pkt_tc =
hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self) +
((u64)hw_atl_stats_tx_dma_good_pkt_countermsw_get(self) << 32);
self->curr_stats.dma_oct_rc =
hw_atl_stats_rx_dma_good_octet_counterlsw_get(self) +
((u64)hw_atl_stats_rx_dma_good_octet_countermsw_get(self) << 32);
self->curr_stats.dma_oct_tc =
hw_atl_stats_tx_dma_good_octet_counterlsw_get(self) +
((u64)hw_atl_stats_tx_dma_good_octet_countermsw_get(self) << 32);
self->curr_stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self);
memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats));
return 0;
}
struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self)
{
return &self->curr_stats;
}
static const u32 hw_atl_utils_hw_mac_regs[] = {
0x00005580U, 0x00005590U, 0x000055B0U, 0x000055B4U,
0x000055C0U, 0x00005B00U, 0x00005B04U, 0x00005B08U,
0x00005B0CU, 0x00005B10U, 0x00005B14U, 0x00005B18U,
0x00005B1CU, 0x00005B20U, 0x00005B24U, 0x00005B28U,
0x00005B2CU, 0x00005B30U, 0x00005B34U, 0x00005B38U,
0x00005B3CU, 0x00005B40U, 0x00005B44U, 0x00005B48U,
0x00005B4CU, 0x00005B50U, 0x00005B54U, 0x00005B58U,
0x00005B5CU, 0x00005B60U, 0x00005B64U, 0x00005B68U,
0x00005B6CU, 0x00005B70U, 0x00005B74U, 0x00005B78U,
0x00005B7CU, 0x00007C00U, 0x00007C04U, 0x00007C08U,
0x00007C0CU, 0x00007C10U, 0x00007C14U, 0x00007C18U,
0x00007C1CU, 0x00007C20U, 0x00007C40U, 0x00007C44U,
0x00007C48U, 0x00007C4CU, 0x00007C50U, 0x00007C54U,
0x00007C58U, 0x00007C5CU, 0x00007C60U, 0x00007C80U,
0x00007C84U, 0x00007C88U, 0x00007C8CU, 0x00007C90U,
0x00007C94U, 0x00007C98U, 0x00007C9CU, 0x00007CA0U,
0x00007CC0U, 0x00007CC4U, 0x00007CC8U, 0x00007CCCU,
0x00007CD0U, 0x00007CD4U, 0x00007CD8U, 0x00007CDCU,
0x00007CE0U, 0x00000300U, 0x00000304U, 0x00000308U,
0x0000030cU, 0x00000310U, 0x00000314U, 0x00000318U,
0x0000031cU, 0x00000360U, 0x00000364U, 0x00000368U,
0x0000036cU, 0x00000370U, 0x00000374U, 0x00006900U,
};
unsigned int hw_atl_utils_hw_get_reg_length(void)
{
return ARRAY_SIZE(hw_atl_utils_hw_mac_regs);
}
int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
u32 *regs_buff)
{
unsigned int i = 0U;
unsigned int mac_regs_count = hw_atl_utils_hw_get_reg_length();
for (i = 0; i < mac_regs_count; i++)
regs_buff[i] = aq_hw_read_reg(self,
hw_atl_utils_hw_mac_regs[i]);
return 0;
}
int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version)
{
*fw_version = aq_hw_read_reg(self, 0x18U);
return 0;
}
static int aq_fw1x_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac)
{
struct hw_aq_atl_utils_fw_rpc *prpc = NULL;
unsigned int rpc_size = 0U;
int err = 0;
err = hw_atl_utils_fw_rpc_wait(self, &prpc);
if (err < 0)
goto err_exit;
memset(prpc, 0, sizeof(*prpc));
if (wol_enabled) {
rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_wol);
prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD;
prpc->msg_wol.priority = 0x10000000; /* normal priority */
prpc->msg_wol.pattern_id = 1U;
prpc->msg_wol.wol_packet_type = 2U; /* Magic Packet */
ether_addr_copy((struct ether_addr *)mac,
(struct ether_addr *)&prpc->msg_wol.wol_pattern);
} else {
rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_del_id);
prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL;
prpc->msg_wol.pattern_id = 1U;
}
err = hw_atl_utils_fw_rpc_call(self, rpc_size);
if (err < 0)
goto err_exit;
err_exit:
return err;
}
static
int aq_fw1x_set_power(struct aq_hw_s *self,
unsigned int power_state __rte_unused,
u8 *mac)
{
struct hw_aq_atl_utils_fw_rpc *prpc = NULL;
unsigned int rpc_size = 0U;
int err = 0;
if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
err = aq_fw1x_set_wol(self, 1, mac);
if (err < 0)
goto err_exit;
rpc_size = sizeof(prpc->msg_id) +
sizeof(prpc->msg_enable_wakeup);
err = hw_atl_utils_fw_rpc_wait(self, &prpc);
if (err < 0)
goto err_exit;
memset(prpc, 0, rpc_size);
prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP;
prpc->msg_enable_wakeup.pattern_mask = 0x00000002;
err = hw_atl_utils_fw_rpc_call(self, rpc_size);
if (err < 0)
goto err_exit;
}
hw_atl_utils_mpi_set_speed(self, 0);
hw_atl_utils_mpi_set_state(self, MPI_POWER);
err_exit:
return err;
}
const struct aq_fw_ops aq_fw_1x_ops = {
.init = hw_atl_utils_mpi_create,
.deinit = hw_atl_fw1x_deinit,
.reset = NULL,
.get_mac_permanent = hw_atl_utils_get_mac_permanent,
.set_link_speed = hw_atl_utils_mpi_set_speed,
.set_state = hw_atl_utils_mpi_set_state,
.update_link_status = hw_atl_utils_mpi_get_link_status,
.update_stats = hw_atl_utils_update_stats,
.set_power = aq_fw1x_set_power,
.get_temp = NULL,
.get_cable_len = NULL,
.set_eee_rate = NULL,
.get_eee_rate = NULL,
.set_flow_control = NULL,
.led_control = NULL,
.get_eeprom = NULL,
.set_eeprom = NULL,
};

510
drivers/net/atlantic/hw_atl/hw_atl_utils.h Normal file
View File

@ -0,0 +1,510 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
/* Copyright (C) 2014-2017 aQuantia Corporation. */
/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
* abstraction layer.
*/
#ifndef HW_ATL_UTILS_H
#define HW_ATL_UTILS_H
#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
/* Hardware tx descriptor */
struct hw_atl_txd_s {
u64 buf_addr;
union {
struct {
u32 type:3;
u32:1;
u32 len:16;
u32 dd:1;
u32 eop:1;
u32 cmd:8;
u32:14;
u32 ct_idx:1;
u32 ct_en:1;
u32 pay_len:18;
} __attribute__((__packed__));
u64 flags;
};
} __attribute__((__packed__));
/* Hardware tx context descriptor */
union hw_atl_txc_s {
struct {
u64 flags1;
u64 flags2;
};
struct {
u64:40;
u32 tun_len:8;
u32 out_len:16;
u32 type:3;
u32 idx:1;
u32 vlan_tag:16;
u32 cmd:4;
u32 l2_len:7;
u32 l3_len:9;
u32 l4_len:8;
u32 mss_len:16;
} __attribute__((__packed__));
} __attribute__((__packed__));
enum aq_tx_desc_type {
tx_desc_type_desc = 1,
tx_desc_type_ctx = 2,
};
enum aq_tx_desc_cmd {
tx_desc_cmd_vlan = 1,
tx_desc_cmd_fcs = 2,
tx_desc_cmd_ipv4 = 4,
tx_desc_cmd_l4cs = 8,
tx_desc_cmd_lso = 0x10,
tx_desc_cmd_wb = 0x20,
};
/* Hardware rx descriptor */
struct hw_atl_rxd_s {
u64 buf_addr;
u64 hdr_addr;
} __attribute__((__packed__));
/* Hardware rx descriptor writeback */
struct hw_atl_rxd_wb_s {
u32 rss_type:4;
u32 pkt_type:8;
u32 type:20;
u32 rss_hash;
u16 dd:1;
u16 eop:1;
u16 rx_stat:4;
u16 rx_estat:6;
u16 rsc_cnt:4;
u16 pkt_len;
u16 next_desc_ptr;
u16 vlan;
} __attribute__((__packed__));
struct hw_atl_stats_s {
u32 uprc;
u32 mprc;
u32 bprc;
u32 erpt;
u32 uptc;
u32 mptc;
u32 bptc;
u32 erpr;
u32 mbtc;
u32 bbtc;
u32 mbrc;
u32 bbrc;
u32 ubrc;
u32 ubtc;
u32 dpc;
} __attribute__((__packed__));
union ip_addr {
struct {
u8 addr[16];
} v6;
struct {
u8 padding[12];
u8 addr[4];
} v4;
} __attribute__((__packed__));
struct hw_aq_atl_utils_fw_rpc {
u32 msg_id;
union {
struct {
u32 pong;
} msg_ping;
struct {
u8 mac_addr[6];
u32 ip_addr_cnt;
struct {
union ip_addr addr;
union ip_addr mask;
} ip[1];
} msg_arp;
struct {
u32 len;
u8 packet[1514U];
} msg_inject;
struct {
u32 priority;
u32 wol_packet_type;
u32 pattern_id;
u32 next_wol_pattern_offset;
union {
struct {
u32 flags;
u8 ipv4_source_address[4];
u8 ipv4_dest_address[4];
u16 tcp_source_port_number;
u16 tcp_dest_port_number;
} ipv4_tcp_syn_parameters;
struct {
u32 flags;
u8 ipv6_source_address[16];
u8 ipv6_dest_address[16];
u16 tcp_source_port_number;
u16 tcp_dest_port_number;
} ipv6_tcp_syn_parameters;
struct {
u32 flags;
} eapol_request_id_message_parameters;
struct {
u32 flags;
u32 mask_offset;
u32 mask_size;
u32 pattern_offset;
u32 pattern_size;
} wol_bit_map_pattern;
struct {
u8 mac_addr[6];
} wol_magic_packet_pattern;
} wol_pattern;
} msg_wol;
struct {
u16 tc_quanta[8];
u16 tc_threshold[8];
} msg_msm_pfc_quantas;
struct {
union {
u32 pattern_mask;
struct {
u32 aq_pm_wol_reason_arp_v4_pkt : 1;
u32 aq_pm_wol_reason_ipv4_ping_pkt : 1;
u32 aq_pm_wol_reason_ipv6_ns_pkt : 1;
u32 aq_pm_wol_reason_ipv6_ping_pkt : 1;
u32 aq_pm_wol_reason_link_up : 1;
u32 aq_pm_wol_reason_link_down : 1;
u32 aq_pm_wol_reason_maximum : 1;
};
};
union {
u32 offload_mask;
};
} msg_enable_wakeup;
struct {
u32 priority;
u32 protocol_offload_type;
u32 protocol_offload_id;
u32 next_protocol_offload_offset;
union {
struct {
u32 flags;
u8 remote_ipv4_addr[4];
u8 host_ipv4_addr[4];
u8 mac_addr[6];
} ipv4_arp_params;
};
} msg_offload;
struct {
u32 id;
} msg_del_id;
};
} __attribute__((__packed__));
struct hw_aq_atl_utils_mbox_header {
u32 version;
u32 transaction_id;
u32 error;
} __attribute__((__packed__));
struct hw_aq_info {
u8 reserved[6];
u16 phy_fault_code;
u16 phy_temperature;
u8 cable_len;
u8 reserved1;
u32 cable_diag_data[4];
u8 reserved2[32];
u32 caps_lo;
u32 caps_hi;
} __attribute__((__packed__));
struct hw_aq_atl_utils_mbox {
struct hw_aq_atl_utils_mbox_header header;
struct hw_atl_stats_s stats;
struct hw_aq_info info;
} __attribute__((__packed__));
/* fw2x */
typedef u16 in_port_t;
typedef u32 ip4_addr_t;
typedef int int32_t;
typedef short int16_t;
typedef u32 fw_offset_t;
struct ip6_addr {
u32 addr[4];
} __attribute__((__packed__));
struct offload_ka_v4 {
u32 timeout;
in_port_t local_port;
in_port_t remote_port;
u8 remote_mac_addr[6];
u16 win_size;
u32 seq_num;
u32 ack_num;
ip4_addr_t local_ip;
ip4_addr_t remote_ip;
} __attribute__((__packed__));
struct offload_ka_v6 {
u32 timeout;
in_port_t local_port;
in_port_t remote_port;
u8 remote_mac_addr[6];
u16 win_size;
u32 seq_num;
u32 ack_num;
struct ip6_addr local_ip;
struct ip6_addr remote_ip;
} __attribute__((__packed__));
struct offload_ip_info {
u8 v4_local_addr_count;
u8 v4_addr_count;
u8 v6_local_addr_count;
u8 v6_addr_count;
fw_offset_t v4_addr;
fw_offset_t v4_prefix;
fw_offset_t v6_addr;
fw_offset_t v6_prefix;
} __attribute__((__packed__));
struct offload_port_info {
u16 udp_port_count;
u16 tcp_port_count;
fw_offset_t udp_port;
fw_offset_t tcp_port;
} __attribute__((__packed__));
struct offload_ka_info {
u16 v4_ka_count;
u16 v6_ka_count;
u32 retry_count;
u32 retry_interval;
fw_offset_t v4_ka;
fw_offset_t v6_ka;
} __attribute__((__packed__));
struct offload_rr_info {
u32 rr_count;
u32 rr_buf_len;
fw_offset_t rr_id_x;
fw_offset_t rr_buf;
} __attribute__((__packed__));
struct offload_info {
u32 version; // current version is 0x00000000
u32 len; // The whole structure length
// including the variable-size buf
u8 mac_addr[6]; // 8 bytes to keep alignment. Only
// first 6 meaningful.
u8 reserved[2];
struct offload_ip_info ips;
struct offload_port_info ports;
struct offload_ka_info kas;
struct offload_rr_info rrs;
u8 buf[0];
} __attribute__((__packed__));
struct smbus_read_request {
u32 offset; /* not used */
u32 device_id;
u32 address;
u32 length;
} __attribute__((__packed__));
struct smbus_write_request {
u32 offset; /* not used */
u32 device_id;
u32 address;
u32 length;
} __attribute__((__packed__));
#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U
#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
self->chip_features)
enum hal_atl_utils_fw_state_e {
MPI_DEINIT = 0,
MPI_RESET = 1,
MPI_INIT = 2,
MPI_POWER = 4,
};
#define HAL_ATLANTIC_RATE_10G BIT(0)
#define HAL_ATLANTIC_RATE_5G BIT(1)
#define HAL_ATLANTIC_RATE_5GSR BIT(2)
#define HAL_ATLANTIC_RATE_2GS BIT(3)
#define HAL_ATLANTIC_RATE_1G BIT(4)
#define HAL_ATLANTIC_RATE_100M BIT(5)
#define HAL_ATLANTIC_RATE_INVALID BIT(6)
#define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U
#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U
#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U
#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U
#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U
#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U
#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U
#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U
#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U
#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U
#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd
#define SMBUS_READ_REQUEST BIT(13)
#define SMBUS_WRITE_REQUEST BIT(14)
#define SMBUS_DEVICE_ID 0x50
enum hw_atl_fw2x_rate {
FW2X_RATE_100M = 0x20,
FW2X_RATE_1G = 0x100,
FW2X_RATE_2G5 = 0x200,
FW2X_RATE_5G = 0x400,
FW2X_RATE_10G = 0x800,
};
enum hw_atl_fw2x_caps_lo {
CAPS_LO_10BASET_HD = 0x00,
CAPS_LO_10BASET_FD,
CAPS_LO_100BASETX_HD,
CAPS_LO_100BASET4_HD,
CAPS_LO_100BASET2_HD,
CAPS_LO_100BASETX_FD,
CAPS_LO_100BASET2_FD,
CAPS_LO_1000BASET_HD,
CAPS_LO_1000BASET_FD,
CAPS_LO_2P5GBASET_FD,
CAPS_LO_5GBASET_FD,
CAPS_LO_10GBASET_FD,
};
enum hw_atl_fw2x_caps_hi {
CAPS_HI_RESERVED1 = 0x00,
CAPS_HI_10BASET_EEE,
CAPS_HI_RESERVED2,
CAPS_HI_PAUSE,
CAPS_HI_ASYMMETRIC_PAUSE,
CAPS_HI_100BASETX_EEE,
CAPS_HI_RESERVED3,
CAPS_HI_RESERVED4,
CAPS_HI_1000BASET_FD_EEE,
CAPS_HI_2P5GBASET_FD_EEE,
CAPS_HI_5GBASET_FD_EEE,
CAPS_HI_10GBASET_FD_EEE,
CAPS_HI_RESERVED5,
CAPS_HI_RESERVED6,
CAPS_HI_RESERVED7,
CAPS_HI_RESERVED8,
CAPS_HI_RESERVED9,
CAPS_HI_CABLE_DIAG,
CAPS_HI_TEMPERATURE,
CAPS_HI_DOWNSHIFT,
CAPS_HI_PTP_AVB_EN,
CAPS_HI_MEDIA_DETECT,
CAPS_HI_LINK_DROP,
CAPS_HI_SLEEP_PROXY,
CAPS_HI_WOL,
CAPS_HI_MAC_STOP,
CAPS_HI_EXT_LOOPBACK,
CAPS_HI_INT_LOOPBACK,
CAPS_HI_EFUSE_AGENT,
CAPS_HI_WOL_TIMER,
CAPS_HI_STATISTICS,
CAPS_HI_TRANSACTION_ID,
};
struct aq_hw_s;
struct aq_fw_ops;
struct aq_hw_link_status_s;
int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
int hw_atl_utils_soft_reset(struct aq_hw_s *self);
void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
struct hw_aq_atl_utils_mbox_header *pmbox);
void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
struct hw_aq_atl_utils_mbox *pmbox);
void hw_atl_utils_mpi_set(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state,
u32 speed);
int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
unsigned int hw_atl_utils_hw_get_reg_length(void);
int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
u32 *regs_buff);
int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
unsigned int power_state);
int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
int hw_atl_utils_update_stats(struct aq_hw_s *self);
struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
u32 *p, u32 cnt);
int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
u32 cnt);
int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
struct hw_aq_atl_utils_fw_rpc **rpc);
extern const struct aq_fw_ops aq_fw_1x_ops;
extern const struct aq_fw_ops aq_fw_2x_ops;
#endif /* HW_ATL_UTILS_H */

618
drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c Normal file
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@ -0,0 +1,618 @@
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
/* Copyright (C) 2014-2017 aQuantia Corporation. */
/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
* Atlantic hardware abstraction layer.
*/
#include <rte_ether.h>
#include "../atl_hw_regs.h"
#include "../atl_types.h"
#include "hw_atl_utils.h"
#include "hw_atl_llh.h"
#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
#define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
#define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
#define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
#define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
#define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
#define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
#define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
#define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
#define HW_ATL_FW_FEATURE_EEPROM 0x03010025
#define HW_ATL_FW_FEATURE_LED 0x03010026
struct fw2x_msg_wol_pattern {
u8 mask[16];
u32 crc;
} __attribute__((__packed__));
struct fw2x_msg_wol {
u32 msg_id;
u8 hw_addr[6];
u8 magic_packet_enabled;
u8 filter_count;
struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
u8 link_up_enabled;
u8 link_down_enabled;
u16 reserved;
u32 link_up_timeout;
u32 link_down_timeout;
} __attribute__((__packed__));
static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
static int aq_fw2x_set_state(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state);
static int aq_fw2x_init(struct aq_hw_s *self)
{
int err = 0;
/* check 10 times by 1ms */
AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
1000U, 10U);
AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
1000U, 100U);
return err;
}
static int aq_fw2x_deinit(struct aq_hw_s *self)
{
int err = aq_fw2x_set_link_speed(self, 0);
if (!err)
err = aq_fw2x_set_state(self, MPI_DEINIT);
return err;
}
static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
{
enum hw_atl_fw2x_rate rate = 0;
if (speed & AQ_NIC_RATE_10G)
rate |= FW2X_RATE_10G;
if (speed & AQ_NIC_RATE_5G)
rate |= FW2X_RATE_5G;
if (speed & AQ_NIC_RATE_5G5R)
rate |= FW2X_RATE_5G;
if (speed & AQ_NIC_RATE_2G5)
rate |= FW2X_RATE_2G5;
if (speed & AQ_NIC_RATE_1G)
rate |= FW2X_RATE_1G;
if (speed & AQ_NIC_RATE_100M)
rate |= FW2X_RATE_100M;
return rate;
}
static u32 fw2x_to_eee_mask(u32 speed)
{
u32 rate = 0;
if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
rate |= AQ_NIC_RATE_EEE_10G;
if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
rate |= AQ_NIC_RATE_EEE_5G;
if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
rate |= AQ_NIC_RATE_EEE_2G5;
if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
rate |= AQ_NIC_RATE_EEE_1G;
return rate;
}
static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
{
u32 val = link_speed_mask_2fw2x_ratemask(speed);
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
return 0;
}
static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
{
if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
*mpi_state |= BIT(CAPS_HI_PAUSE);
else
*mpi_state &= ~BIT(CAPS_HI_PAUSE);
if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
*mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
else
*mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
}
static int aq_fw2x_set_state(struct aq_hw_s *self,
enum hal_atl_utils_fw_state_e state)
{
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
switch (state) {
case MPI_INIT:
mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
aq_fw2x_set_mpi_flow_control(self, &mpi_state);
break;
case MPI_DEINIT:
mpi_state |= BIT(CAPS_HI_LINK_DROP);
break;
case MPI_RESET:
case MPI_POWER:
/* No actions */
break;
}
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
return 0;
}
static int aq_fw2x_update_link_status(struct aq_hw_s *self)
{
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
struct aq_hw_link_status_s *link_status = &self->aq_link_status;
if (speed) {
if (speed & FW2X_RATE_10G)
link_status->mbps = 10000;
else if (speed & FW2X_RATE_5G)
link_status->mbps = 5000;
else if (speed & FW2X_RATE_2G5)
link_status->mbps = 2500;
else if (speed & FW2X_RATE_1G)
link_status->mbps = 1000;
else if (speed & FW2X_RATE_100M)
link_status->mbps = 100;
else
link_status->mbps = 10000;
} else {
link_status->mbps = 0;
}
return 0;
}
static
int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
{
int err = 0;
u32 h = 0U;
u32 l = 0U;
u32 mac_addr[2] = { 0 };
u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
if (efuse_addr != 0) {
err = hw_atl_utils_fw_downld_dwords(self,
efuse_addr + (40U * 4U),
mac_addr,
ARRAY_SIZE(mac_addr));
if (err)
return err;
mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
}
ether_addr_copy((struct ether_addr *)mac_addr,
(struct ether_addr *)mac);
if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
unsigned int rnd = (uint32_t)rte_rand();
//get_random_bytes(&rnd, sizeof(unsigned int));
l = 0xE3000000U
| (0xFFFFU & rnd)
| (0x00 << 16);
h = 0x8001300EU;
mac[5] = (u8)(0xFFU & l);
l >>= 8;
mac[4] = (u8)(0xFFU & l);
l >>= 8;
mac[3] = (u8)(0xFFU & l);
l >>= 8;
mac[2] = (u8)(0xFFU & l);
mac[1] = (u8)(0xFFU & h);
h >>= 8;
mac[0] = (u8)(0xFFU & h);
}
return err;
}
static int aq_fw2x_update_stats(struct aq_hw_s *self)
{
int err = 0;
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
/* Toggle statistics bit for FW to update */
mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
/* Wait FW to report back */
AQ_HW_WAIT_FOR(orig_stats_val !=
(aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
BIT(CAPS_HI_STATISTICS)),
1U, 10000U);
if (err)
return err;
return hw_atl_utils_update_stats(self);
}
static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp)
{
int err = 0;
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE);
u32 temp_res;
/* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */
mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE);
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
/* Wait FW to report back */
AQ_HW_WAIT_FOR(temp_val !=
(aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U);
err = hw_atl_utils_fw_downld_dwords(self,
self->mbox_addr +
offsetof(struct hw_aq_atl_utils_mbox, info) +
offsetof(struct hw_aq_info, phy_temperature),
&temp_res,
sizeof(temp_res) / sizeof(u32));
if (err)
return err;
*temp = temp_res * 100 / 256;
return 0;
}
static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len)
{
int err = 0;
u32 cable_len_res;
err = hw_atl_utils_fw_downld_dwords(self,
self->mbox_addr +
offsetof(struct hw_aq_atl_utils_mbox, info) +
offsetof(struct hw_aq_info, phy_temperature),
&cable_len_res,
sizeof(cable_len_res) / sizeof(u32));
if (err)
return err;
*cable_len = (cable_len_res >> 16) & 0xFF;
return 0;
}
#ifndef ETH_ALEN
#define ETH_ALEN 6
#endif
static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
{
int err = 0;
struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
struct offload_info *cfg = NULL;
unsigned int rpc_size = 0U;
u32 mpi_opts;
rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
err = hw_atl_utils_fw_rpc_wait(self, &rpc);
if (err < 0)
goto err_exit;
memset(rpc, 0, rpc_size);
cfg = (struct offload_info *)(&rpc->msg_id + 1);
memcpy(cfg->mac_addr, mac, ETH_ALEN);
cfg->len = sizeof(*cfg);
/* Clear bit 0x36C.23 */
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
err = hw_atl_utils_fw_rpc_call(self, rpc_size);
if (err < 0)
goto err_exit;
/* Set bit 0x36C.23 */
mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U);
err_exit:
return err;
}
static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
{
int err = 0;
struct fw2x_msg_wol *msg = NULL;
u32 mpi_opts;
struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
err = hw_atl_utils_fw_rpc_wait(self, &rpc);
if (err < 0)
goto err_exit;
msg = (struct fw2x_msg_wol *)rpc;
msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
msg->magic_packet_enabled = true;
memcpy(msg->hw_addr, mac, ETH_ALEN);
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL);
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
if (err < 0)
goto err_exit;
/* Set bit 0x36C.24 */
mpi_opts |= HW_ATL_FW2X_CAP_WOL;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
HW_ATL_FW2X_CAP_WOL), 1U, 10000U);
err_exit:
return err;
}
static int aq_fw2x_set_power(struct aq_hw_s *self,
unsigned int power_state __rte_unused,
u8 *mac)
{
int err = 0;
if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
err = aq_fw2x_set_sleep_proxy(self, mac);
if (err < 0)
goto err_exit;
err = aq_fw2x_set_wol_params(self, mac);
if (err < 0)
goto err_exit;
}
err_exit:
return err;
}
static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
{
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK |
HW_ATL_FW2X_CAP_EEE_10G_MASK);
if (speed & AQ_NIC_RATE_EEE_10G)
mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
if (speed & AQ_NIC_RATE_EEE_5G)
mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
if (speed & AQ_NIC_RATE_EEE_2G5)
mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
if (speed & AQ_NIC_RATE_EEE_1G)
mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
return 0;
}
static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
u32 *supported_rates)
{
int err = 0;
u32 caps_hi;
u32 mpi_state;
err = hw_atl_utils_fw_downld_dwords(self,
self->mbox_addr +
offsetof(struct hw_aq_atl_utils_mbox, info) +
offsetof(struct hw_aq_info, caps_hi),
&caps_hi,
sizeof(caps_hi) / sizeof(u32));
if (err)
return err;
*supported_rates = fw2x_to_eee_mask(caps_hi);
mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
*rate = fw2x_to_eee_mask(mpi_state);
return err;
}
static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
{
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
aq_fw2x_set_mpi_flow_control(self, &mpi_state);
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
return 0;
}
static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
{
if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED)
return -EOPNOTSUPP;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
return 0;
}
static int aq_fw2x_get_eeprom(struct aq_hw_s *self, u32 *data, u32 len)
{
int err = 0;
struct smbus_read_request request;
u32 mpi_opts;
u32 result = 0;
if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
return -EOPNOTSUPP;
request.device_id = SMBUS_DEVICE_ID;
request.address = 0;
request.length = len;
/* Write SMBUS request to cfg memory */
err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
(u32 *)(void *)&request,
RTE_ALIGN(sizeof(request), sizeof(u32)));
if (err < 0)
return err;
/* Toggle 0x368.SMBUS_READ_REQUEST bit */
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
mpi_opts ^= SMBUS_READ_REQUEST;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
/* Wait until REQUEST_BIT matched in 0x370 */
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
SMBUS_READ_REQUEST) == (mpi_opts & SMBUS_READ_REQUEST),
10U, 10000U);
if (err < 0)
return err;
err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
&result,
RTE_ALIGN(sizeof(result), sizeof(u32)));
if (err < 0)
return err;
if (result == 0) {
err = hw_atl_utils_fw_downld_dwords(self,
self->rpc_addr + sizeof(u32) * 2,
data,
RTE_ALIGN(len, sizeof(u32)));
if (err < 0)
return err;
}
return 0;
}
static int aq_fw2x_set_eeprom(struct aq_hw_s *self, u32 *data, u32 len)
{
struct smbus_write_request request;
u32 mpi_opts, result = 0;
int err = 0;
if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
return -EOPNOTSUPP;
request.device_id = SMBUS_DEVICE_ID;
request.address = 0;
request.length = len;
/* Write SMBUS request to cfg memory */
err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
(u32 *)(void *)&request,
RTE_ALIGN(sizeof(request), sizeof(u32)));
if (err < 0)
return err;
/* Write SMBUS data to cfg memory */
err = hw_atl_utils_fw_upload_dwords(self,
self->rpc_addr + sizeof(request),
(u32 *)(void *)data,
RTE_ALIGN(len, sizeof(u32)));
if (err < 0)
return err;
/* Toggle 0x368.SMBUS_WRITE_REQUEST bit */
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
mpi_opts ^= SMBUS_WRITE_REQUEST;
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
/* Wait until REQUEST_BIT matched in 0x370 */
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
SMBUS_WRITE_REQUEST) == (mpi_opts & SMBUS_WRITE_REQUEST),
10U, 10000U);
if (err < 0)
return err;
/* Read status of write operation */
err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
&result,
RTE_ALIGN(sizeof(result), sizeof(u32)));
if (err < 0)
return err;
return 0;
}
const struct aq_fw_ops aq_fw_2x_ops = {
.init = aq_fw2x_init,
.deinit = aq_fw2x_deinit,
.reset = NULL,
.get_mac_permanent = aq_fw2x_get_mac_permanent,
.set_link_speed = aq_fw2x_set_link_speed,
.set_state = aq_fw2x_set_state,
.update_link_status = aq_fw2x_update_link_status,
.update_stats = aq_fw2x_update_stats,
.set_power = aq_fw2x_set_power,
.get_temp = aq_fw2x_get_temp,
.get_cable_len = aq_fw2x_get_cable_len,
.set_eee_rate = aq_fw2x_set_eee_rate,
.get_eee_rate = aq_fw2x_get_eee_rate,
.set_flow_control = aq_fw2x_set_flow_control,
.led_control = aq_fw2x_led_control,
.get_eeprom = aq_fw2x_get_eeprom,
.set_eeprom = aq_fw2x_set_eeprom,
};

2
drivers/net/atlantic/meson.build
View File

@ -5,4 +5,6 @@ sources = files(
'atl_ethdev.c',
'atl_hw_regs.c',
'hw_atl/hw_atl_llh.c',
'hw_atl/hw_atl_utils_fw2x.c',
'hw_atl/hw_atl_utils.c',
)