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net/ixgbe/base: fix register access error

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This patch corrects the FLA/GSCL/GSCN access offset values according
to the datasheet.

Fixes: 0790adeb56 ("ixgbe/base: support X550em_a device")

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
This commit is contained in:
Beilei Xing 2016-06-23 15:22:27 +08:00 committed by Bruce Richardson
parent 1062ba821b
commit 87d2b7c5ce
1 changed files with 41 additions and 1 deletions
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42
drivers/net/ixgbe/base/ixgbe_type.h
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@ -196,7 +196,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_FLA_X540 IXGBE_FLA
#define IXGBE_FLA_X550 IXGBE_FLA
#define IXGBE_FLA_X550EM_x IXGBE_FLA
#define IXGBE_FLA_X550EM_a 0x15F6C
#define IXGBE_FLA_X550EM_a 0x15F68
#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA)
#define IXGBE_EEMNGCTL 0x10110
@ -1080,16 +1080,40 @@ struct ixgbe_dmac_config {
#define IXGBE_PCIEPIPEDAT 0x11008
#define IXGBE_GSCL_1 0x11010
#define IXGBE_GSCL_2 0x11014
#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1
#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2
#define IXGBE_GSCL_3 0x11018
#define IXGBE_GSCL_4 0x1101C
#define IXGBE_GSCN_0 0x11020
#define IXGBE_GSCN_1 0x11024
#define IXGBE_GSCN_2 0x11028
#define IXGBE_GSCN_3 0x1102C
#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0
#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1
#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2
#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3
#define IXGBE_FACTPS 0x10150
#define IXGBE_FACTPS_X540 IXGBE_FACTPS
#define IXGBE_GSCL_1_X550 0x11800
#define IXGBE_GSCL_2_X550 0x11804
#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550
#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550
#define IXGBE_GSCN_0_X550 0x11820
#define IXGBE_GSCN_1_X550 0x11824
#define IXGBE_GSCN_2_X550 0x11828
#define IXGBE_GSCN_3_X550 0x1182C
#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550
#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550
#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550
#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550
#define IXGBE_FACTPS_X550 IXGBE_FACTPS
#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
#define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550
#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550
#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550
#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550
#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550
#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550
#define IXGBE_FACTPS_X550EM_a 0x15FEC
#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS)
@ -1126,6 +1150,10 @@ struct ixgbe_dmac_config {
#define IXGBE_GSCL_6_82599 0x11034
#define IXGBE_GSCL_7_82599 0x11038
#define IXGBE_GSCL_8_82599 0x1103C
#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599
#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599
#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599
#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599
#define IXGBE_PHYADR_82599 0x11040
#define IXGBE_PHYDAT_82599 0x11044
#define IXGBE_PHYCTL_82599 0x11048
@ -1136,10 +1164,22 @@ struct ixgbe_dmac_config {
#define IXGBE_CIAD_82599 IXGBE_CIAD
#define IXGBE_CIAA_X540 IXGBE_CIAA
#define IXGBE_CIAD_X540 IXGBE_CIAD
#define IXGBE_GSCL_5_X550 0x11810
#define IXGBE_GSCL_6_X550 0x11814
#define IXGBE_GSCL_7_X550 0x11818
#define IXGBE_GSCL_8_X550 0x1181C
#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550
#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550
#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550
#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550
#define IXGBE_CIAA_X550 0x11508
#define IXGBE_CIAD_X550 0x11510
#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550
#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550
#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550
#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550
#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)