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net/ice/base: update to register definition file

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Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
This commit is contained in:
Qi Zhang 2019-08-29 10:36:48 +08:00 committed by Ferruh Yigit
parent 6632c0556d
commit 8b4cd4eda0
1 changed files with 34 additions and 0 deletions
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34
drivers/net/ice/base/ice_hw_autogen.h
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@ -5330,6 +5330,29 @@
#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
#define GL_MDCK_RX_DESC_ADDR_S 0
#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
#define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
#define GL_MDET_RX_QNUM_S 0
#define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
@ -5363,6 +5386,17 @@
#define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
#define GL_MDET_TX_TCLAN_VALID_S 31
#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
#define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
#define GL_MDET_TX_TDPU_QNUM_S 0
#define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
#define GL_MDET_TX_TDPU_VF_NUM_S 15
#define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
#define GL_MDET_TX_TDPU_PF_NUM_S 23
#define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
#define GL_MDET_TX_TDPU_MAL_TYPE_S 26
#define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
#define GL_MDET_TX_TDPU_VALID_S 31
#define GL_MDET_TX_TDPU_VALID_M BIT(31)
#define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)