net/igc: support device initialization

Update base codes, add readme. Add OS specific functions and definitions. Add device initialization codes. Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-04-15 16:48:01 +08:00 · 2020-04-15 16:48:01 +08:00 · 8cb7c57d9b
commit 8cb7c57d9b
parent 66fde1b943
28 changed files with 17361 additions and 10 deletions
--- a/drivers/net/igc/Makefile
+++ b/drivers/net/igc/Makefile
@ -13,12 +13,24 @@ CFLAGS += $(WERROR_FLAGS)
 LDLIBS += -lrte_eal
 LDLIBS += -lrte_ethdev
 LDLIBS += -lrte_bus_pci
+LDLIBS += -lrte_mbuf
+LDLIBS += -lrte_mempool

 EXPORT_MAP := rte_pmd_igc_version.map

+VPATH += $(SRCDIR)/base
+
 #
 # all source are stored in SRCS-y
 #
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_api.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_base.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_i225.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_mac.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_manage.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_nvm.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_osdep.c
+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_phy.c
 SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_logs.c
 SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_ethdev.c

--- a/drivers/net/igc/base/README
+++ b/drivers/net/igc/base/README
@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+Intel® IGC driver
+==================
+
+This directory contains source code of FreeBSD igc driver of version
+2019.10.18 released by the team which develops basic drivers for any
+i225 NIC.
+The directory of base/ contains the original source package.
+This driver is valid for the product(s) listed below
+
+* Intel® Ethernet Network Adapters I225
+
+Updating the driver
+===================
+
+NOTE:
+- To avoid namespace issues with e1000 PMD, all prefix e1000_ or E1000_
+of the definition, macro and file names ware replaced with igc_ or IGC_.
+- Since some codes are not required, they have been removed from the
+base codes, such as the I350 and I210 series NICs related codes.
+- Some registers are used by the base codes but not defined in the base
+codes, so they ware added to them.
+- OS and DPDK specified definitions and macros ware added in following
+files:
+  igc_osdep.h
+  igc_osdep.c
--- a/drivers/net/igc/base/igc_82571.h
+++ b/drivers/net/igc/base/igc_82571.h
@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_82571_H_
+#define _IGC_82571_H_
+
+#define ID_LED_RESERVED_F746	0xF746
+#define ID_LED_DEFAULT_82573	((ID_LED_DEF1_DEF2 << 12) | \
+				 (ID_LED_OFF1_ON2  <<  8) | \
+				 (ID_LED_DEF1_DEF2 <<  4) | \
+				 (ID_LED_DEF1_DEF2))
+
+#define IGC_GCR_L1_ACT_WITHOUT_L0S_RX	0x08000000
+#define AN_RETRY_COUNT		5 /* Autoneg Retry Count value */
+
+/* Intr Throttling - RW */
+#define IGC_EITR_82574(_n)	(0x000E8 + (0x4 * (_n)))
+
+#define IGC_EIAC_82574	0x000DC /* Ext. Interrupt Auto Clear - RW */
+#define IGC_EIAC_MASK_82574	0x01F00000
+
+#define IGC_IVAR_INT_ALLOC_VALID	0x8
+
+/* Manageability Operation Mode mask */
+#define IGC_NVM_INIT_CTRL2_MNGM	0x6000
+
+#define IGC_BASE1000T_STATUS		10
+#define IGC_IDLE_ERROR_COUNT_MASK	0xFF
+#define IGC_RECEIVE_ERROR_COUNTER	21
+#define IGC_RECEIVE_ERROR_MAX		0xFFFF
+bool igc_check_phy_82574(struct igc_hw *hw);
+bool igc_get_laa_state_82571(struct igc_hw *hw);
+void igc_set_laa_state_82571(struct igc_hw *hw, bool state);
+
+#endif
--- a/drivers/net/igc/base/igc_82575.h
+++ b/drivers/net/igc/base/igc_82575.h
@ -0,0 +1,351 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_82575_H_
+#define _IGC_82575_H_
+
+#define ID_LED_DEFAULT_82575_SERDES	((ID_LED_DEF1_DEF2 << 12) | \
+					 (ID_LED_DEF1_DEF2 <<  8) | \
+					 (ID_LED_DEF1_DEF2 <<  4) | \
+					 (ID_LED_OFF1_ON2))
+/*
+ * Receive Address Register Count
+ * Number of high/low register pairs in the RAR.  The RAR (Receive Address
+ * Registers) holds the directed and multicast addresses that we monitor.
+ * These entries are also used for MAC-based filtering.
+ */
+/*
+ * For 82576, there are an additional set of RARs that begin at an offset
+ * separate from the first set of RARs.
+ */
+#define IGC_RAR_ENTRIES_82575	16
+#define IGC_RAR_ENTRIES_82576	24
+#define IGC_RAR_ENTRIES_82580	24
+#define IGC_RAR_ENTRIES_I350	32
+#define IGC_SW_SYNCH_MB	0x00000100
+#define IGC_STAT_DEV_RST_SET	0x00100000
+
+struct igc_adv_data_desc {
+	__le64 buffer_addr;    /* Address of the descriptor's data buffer */
+	union {
+		u32 data;
+		struct {
+			u32 datalen:16; /* Data buffer length */
+			u32 rsvd:4;
+			u32 dtyp:4;  /* Descriptor type */
+			u32 dcmd:8;  /* Descriptor command */
+		} config;
+	} lower;
+	union {
+		u32 data;
+		struct {
+			u32 status:4;  /* Descriptor status */
+			u32 idx:4;
+			u32 popts:6;  /* Packet Options */
+			u32 paylen:18; /* Payload length */
+		} options;
+	} upper;
+};
+
+#define IGC_TXD_DTYP_ADV_C	0x2  /* Advanced Context Descriptor */
+#define IGC_TXD_DTYP_ADV_D	0x3  /* Advanced Data Descriptor */
+#define IGC_ADV_TXD_CMD_DEXT	0x20 /* Descriptor extension (0 = legacy) */
+#define IGC_ADV_TUCMD_IPV4	0x2  /* IP Packet Type: 1=IPv4 */
+#define IGC_ADV_TUCMD_IPV6	0x0  /* IP Packet Type: 0=IPv6 */
+#define IGC_ADV_TUCMD_L4T_UDP	0x0  /* L4 Packet TYPE of UDP */
+#define IGC_ADV_TUCMD_L4T_TCP	0x4  /* L4 Packet TYPE of TCP */
+#define IGC_ADV_TUCMD_MKRREQ	0x10 /* Indicates markers are required */
+#define IGC_ADV_DCMD_EOP	0x1  /* End of Packet */
+#define IGC_ADV_DCMD_IFCS	0x2  /* Insert FCS (Ethernet CRC) */
+#define IGC_ADV_DCMD_RS	0x8  /* Report Status */
+#define IGC_ADV_DCMD_VLE	0x40 /* Add VLAN tag */
+#define IGC_ADV_DCMD_TSE	0x80 /* TCP Seg enable */
+/* Extended Device Control */
+#define IGC_CTRL_EXT_NSICR	0x00000001 /* Disable Intr Clear all on read */
+
+struct igc_adv_context_desc {
+	union {
+		u32 ip_config;
+		struct {
+			u32 iplen:9;
+			u32 maclen:7;
+			u32 vlan_tag:16;
+		} fields;
+	} ip_setup;
+	u32 seq_num;
+	union {
+		u64 l4_config;
+		struct {
+			u32 mkrloc:9;
+			u32 tucmd:11;
+			u32 dtyp:4;
+			u32 adv:8;
+			u32 rsvd:4;
+			u32 idx:4;
+			u32 l4len:8;
+			u32 mss:16;
+		} fields;
+	} l4_setup;
+};
+
+/* SRRCTL bit definitions */
+#define IGC_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
+#define IGC_SRRCTL_DESCTYPE_LEGACY		0x00000000
+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
+#define IGC_SRRCTL_DESCTYPE_MASK		0x0E000000
+#define IGC_SRRCTL_TIMESTAMP			0x40000000
+#define IGC_SRRCTL_DROP_EN			0x80000000
+
+#define IGC_SRRCTL_BSIZEPKT_MASK		0x0000007F
+#define IGC_SRRCTL_BSIZEHDR_MASK		0x00003F00
+
+#define IGC_TX_HEAD_WB_ENABLE		0x1
+#define IGC_TX_SEQNUM_WB_ENABLE	0x2
+
+#define IGC_MRQC_ENABLE_RSS_4Q		0x00000002
+#define IGC_MRQC_ENABLE_VMDQ			0x00000003
+#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
+#define IGC_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
+#define IGC_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
+#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
+#define IGC_MRQC_ENABLE_RSS_8Q		0x00000002
+
+#define IGC_VMRCTL_MIRROR_PORT_SHIFT		8
+#define IGC_VMRCTL_MIRROR_DSTPORT_MASK	(7 << \
+						 IGC_VMRCTL_MIRROR_PORT_SHIFT)
+#define IGC_VMRCTL_POOL_MIRROR_ENABLE		(1 << 0)
+#define IGC_VMRCTL_UPLINK_MIRROR_ENABLE	(1 << 1)
+#define IGC_VMRCTL_DOWNLINK_MIRROR_ENABLE	(1 << 2)
+
+#define IGC_EICR_TX_QUEUE ( \
+	IGC_EICR_TX_QUEUE0 |    \
+	IGC_EICR_TX_QUEUE1 |    \
+	IGC_EICR_TX_QUEUE2 |    \
+	IGC_EICR_TX_QUEUE3)
+
+#define IGC_EICR_RX_QUEUE ( \
+	IGC_EICR_RX_QUEUE0 |    \
+	IGC_EICR_RX_QUEUE1 |    \
+	IGC_EICR_RX_QUEUE2 |    \
+	IGC_EICR_RX_QUEUE3)
+
+#define IGC_EIMS_RX_QUEUE	IGC_EICR_RX_QUEUE
+#define IGC_EIMS_TX_QUEUE	IGC_EICR_TX_QUEUE
+
+#define EIMS_ENABLE_MASK ( \
+	IGC_EIMS_RX_QUEUE  | \
+	IGC_EIMS_TX_QUEUE  | \
+	IGC_EIMS_TCP_TIMER | \
+	IGC_EIMS_OTHER)
+
+/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
+#define IGC_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
+#define IGC_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
+#define IGC_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
+#define IGC_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
+#define IGC_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
+#define IGC_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
+#define IGC_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
+#define IGC_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
+
+#define IGC_RXDADV_RSSTYPE_MASK	0x0000000F
+#define IGC_RXDADV_RSSTYPE_SHIFT	12
+#define IGC_RXDADV_HDRBUFLEN_MASK	0x7FE0
+#define IGC_RXDADV_HDRBUFLEN_SHIFT	5
+#define IGC_RXDADV_SPLITHEADER_EN	0x00001000
+#define IGC_RXDADV_SPH		0x8000
+#define IGC_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
+#define IGC_RXDADV_ERR_HBO		0x00800000
+
+/* RSS Hash results */
+#define IGC_RXDADV_RSSTYPE_NONE	0x00000000
+#define IGC_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
+#define IGC_RXDADV_RSSTYPE_IPV4	0x00000002
+#define IGC_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
+#define IGC_RXDADV_RSSTYPE_IPV6_EX	0x00000004
+#define IGC_RXDADV_RSSTYPE_IPV6	0x00000005
+#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
+#define IGC_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
+#define IGC_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
+#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
+
+/* RSS Packet Types as indicated in the receive descriptor */
+#define IGC_RXDADV_PKTTYPE_ILMASK	0x000000F0
+#define IGC_RXDADV_PKTTYPE_TLMASK	0x00000F00
+#define IGC_RXDADV_PKTTYPE_NONE	0x00000000
+#define IGC_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPV4 hdr present */
+#define IGC_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
+#define IGC_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPV6 hdr present */
+#define IGC_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
+#define IGC_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
+#define IGC_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
+#define IGC_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
+#define IGC_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
+
+#define IGC_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
+#define IGC_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
+#define IGC_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
+#define IGC_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
+#define IGC_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
+#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
+
+/* LinkSec results */
+/* Security Processing bit Indication */
+#define IGC_RXDADV_LNKSEC_STATUS_SECP		0x00020000
+#define IGC_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
+#define IGC_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
+#define IGC_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
+#define IGC_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
+
+#define IGC_RXDADV_IPSEC_STATUS_SECP			0x00020000
+#define IGC_RXDADV_IPSEC_ERROR_BIT_MASK		0x18000000
+#define IGC_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL	0x08000000
+#define IGC_RXDADV_IPSEC_ERROR_INVALID_LENGTH		0x10000000
+#define IGC_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED	0x18000000
+
+#define IGC_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wbk flushing */
+/* Tx Queue Arbitration Priority 0=low, 1=high */
+#define IGC_TXDCTL_PRIORITY		0x08000000
+
+#define IGC_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
+
+/* Direct Cache Access (DCA) definitions */
+#define IGC_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
+#define IGC_DCA_CTRL_DCA_DISABLE	0x00000001 /* DCA Disable */
+
+#define IGC_DCA_CTRL_DCA_MODE_CB1	0x00 /* DCA Mode CB1 */
+#define IGC_DCA_CTRL_DCA_MODE_CB2	0x02 /* DCA Mode CB2 */
+
+#define IGC_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
+#define IGC_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
+#define IGC_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
+#define IGC_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
+#define IGC_DCA_RXCTRL_DESC_RRO_EN	(1 << 9) /* DCA Rx Desc Relax Order */
+
+#define IGC_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
+#define IGC_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
+#define IGC_DCA_TXCTRL_DESC_RRO_EN	(1 << 9) /* Tx rd Desc Relax Order */
+#define IGC_DCA_TXCTRL_TX_WB_RO_EN	(1 << 11) /* Tx Desc writeback RO bit */
+#define IGC_DCA_TXCTRL_DATA_RRO_EN	(1 << 13) /* Tx rd data Relax Order */
+
+#define IGC_DCA_TXCTRL_CPUID_MASK_82576	0xFF000000 /* Tx CPUID Mask */
+#define IGC_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
+#define IGC_DCA_TXCTRL_CPUID_SHIFT_82576	24 /* Tx CPUID */
+#define IGC_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
+
+/* Additional interrupt register bit definitions */
+#define IGC_ICR_LSECPNS	0x00000020 /* PN threshold - server */
+#define IGC_IMS_LSECPNS	IGC_ICR_LSECPNS /* PN threshold - server */
+#define IGC_ICS_LSECPNS	IGC_ICR_LSECPNS /* PN threshold - server */
+
+/* ETQF register bit definitions */
+#define IGC_ETQF_FILTER_ENABLE	(1 << 26)
+#define IGC_ETQF_IMM_INT		(1 << 29)
+#define IGC_ETQF_QUEUE_ENABLE		(1 << 31)
+/*
+ * ETQF filter list: one static filter per filter consumer. This is
+ *                   to avoid filter collisions later. Add new filters
+ *                   here!!
+ *
+ * Current filters:
+ *    EAPOL 802.1x (0x888e): Filter 0
+ */
+#define IGC_ETQF_FILTER_EAPOL		0
+
+#define IGC_FTQF_MASK_SOURCE_ADDR_BP	0x20000000
+#define IGC_FTQF_MASK_DEST_ADDR_BP	0x40000000
+#define IGC_FTQF_MASK_SOURCE_PORT_BP	0x80000000
+
+#define IGC_NVM_APME_82575		0x0400
+#define MAX_NUM_VFS			7
+
+#define IGC_DTXSWC_MAC_SPOOF_MASK	0x000000FF /* Per VF MAC spoof cntrl */
+#define IGC_DTXSWC_VLAN_SPOOF_MASK	0x0000FF00 /* Per VF VLAN spoof cntrl */
+#define IGC_DTXSWC_LLE_MASK		0x00FF0000 /* Per VF Local LB enables */
+#define IGC_DTXSWC_VLAN_SPOOF_SHIFT	8
+#define IGC_DTXSWC_LLE_SHIFT		16
+#define IGC_DTXSWC_VMDQ_LOOPBACK_EN	(1 << 31)  /* global VF LB enable */
+
+/* Easy defines for setting default pool, would normally be left a zero */
+#define IGC_VT_CTL_DEFAULT_POOL_SHIFT	7
+#define IGC_VT_CTL_DEFAULT_POOL_MASK	(0x7 << IGC_VT_CTL_DEFAULT_POOL_SHIFT)
+
+/* Other useful VMD_CTL register defines */
+#define IGC_VT_CTL_IGNORE_MAC		(1 << 28)
+#define IGC_VT_CTL_DISABLE_DEF_POOL	(1 << 29)
+#define IGC_VT_CTL_VM_REPL_EN		(1 << 30)
+
+/* Per VM Offload register setup */
+#define IGC_VMOLR_RLPML_MASK	0x00003FFF /* Long Packet Maximum Length mask */
+#define IGC_VMOLR_LPE		0x00010000 /* Accept Long packet */
+#define IGC_VMOLR_RSSE	0x00020000 /* Enable RSS */
+#define IGC_VMOLR_AUPE	0x01000000 /* Accept untagged packets */
+#define IGC_VMOLR_ROMPE	0x02000000 /* Accept overflow multicast */
+#define IGC_VMOLR_ROPE	0x04000000 /* Accept overflow unicast */
+#define IGC_VMOLR_BAM		0x08000000 /* Accept Broadcast packets */
+#define IGC_VMOLR_MPME	0x10000000 /* Multicast promiscuous mode */
+#define IGC_VMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define IGC_VMOLR_STRCRC	0x80000000 /* CRC stripping enable */
+
+#define IGC_VMOLR_VPE		0x00800000 /* VLAN promiscuous enable */
+#define IGC_VMOLR_UPE		0x20000000 /* Unicast promisuous enable */
+#define IGC_DVMOLR_HIDVLAN	0x20000000 /* Vlan hiding enable */
+#define IGC_DVMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define IGC_DVMOLR_STRCRC	0x80000000 /* CRC stripping enable */
+
+#define IGC_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
+#define IGC_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
+
+#define IGC_VLVF_ARRAY_SIZE		32
+#define IGC_VLVF_VLANID_MASK		0x00000FFF
+#define IGC_VLVF_POOLSEL_SHIFT	12
+#define IGC_VLVF_POOLSEL_MASK		(0xFF << IGC_VLVF_POOLSEL_SHIFT)
+#define IGC_VLVF_LVLAN		0x00100000
+#define IGC_VLVF_VLANID_ENABLE	0x80000000
+
+#define IGC_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
+#define IGC_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
+
+#define IGC_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
+
+#define IGC_IOVCTL		0x05BBC
+#define IGC_IOVCTL_REUSE_VFQ	0x00000001
+
+#define IGC_RPLOLR_STRVLAN	0x40000000
+#define IGC_RPLOLR_STRCRC	0x80000000
+
+#define IGC_TCTL_EXT_COLD	0x000FFC00
+#define IGC_TCTL_EXT_COLD_SHIFT	10
+
+#define IGC_DTXCTL_8023LL	0x0004
+#define IGC_DTXCTL_VLAN_ADDED	0x0008
+#define IGC_DTXCTL_OOS_ENABLE	0x0010
+#define IGC_DTXCTL_MDP_EN	0x0020
+#define IGC_DTXCTL_SPOOF_INT	0x0040
+
+#define IGC_EEPROM_PCS_AUTONEG_DISABLE_BIT	(1 << 14)
+
+#define ALL_QUEUES		0xFFFF
+
+s32 igc_reset_init_script_82575(struct igc_hw *hw);
+s32 igc_init_nvm_params_82575(struct igc_hw *hw);
+
+/* Rx packet buffer size defines */
+#define IGC_RXPBS_SIZE_MASK_82576	0x0000007F
+void igc_vmdq_set_loopback_pf(struct igc_hw *hw, bool enable);
+void igc_vmdq_set_anti_spoofing_pf(struct igc_hw *hw, bool enable, int pf);
+void igc_vmdq_set_replication_pf(struct igc_hw *hw, bool enable);
+
+enum igc_promisc_type {
+	igc_promisc_disabled = 0,   /* all promisc modes disabled */
+	igc_promisc_unicast = 1,    /* unicast promiscuous enabled */
+	igc_promisc_multicast = 2,  /* multicast promiscuous enabled */
+	igc_promisc_enabled = 3,    /* both uni and multicast promisc */
+	igc_num_promisc_types
+};
+
+#endif /* _IGC_82575_H_ */
--- a/drivers/net/igc/base/igc_api.c
+++ b/drivers/net/igc/base/igc_api.c
--- a/drivers/net/igc/base/igc_api.h
+++ b/drivers/net/igc/base/igc_api.h
@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_API_H_
+#define _IGC_API_H_
+
+#include "igc_hw.h"
+
+/* I2C SDA and SCL timing parameters for standard mode */
+#define IGC_I2C_T_HD_STA	4
+#define IGC_I2C_T_LOW		5
+#define IGC_I2C_T_HIGH		4
+#define IGC_I2C_T_SU_STA	5
+#define IGC_I2C_T_HD_DATA	5
+#define IGC_I2C_T_SU_DATA	1
+#define IGC_I2C_T_RISE		1
+#define IGC_I2C_T_FALL		1
+#define IGC_I2C_T_SU_STO	4
+#define IGC_I2C_T_BUF		5
+
+s32 igc_set_i2c_bb(struct igc_hw *hw);
+s32 igc_read_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,
+				u8 dev_addr, u8 *data);
+s32 igc_write_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,
+				 u8 dev_addr, u8 data);
+void igc_i2c_bus_clear(struct igc_hw *hw);
+
+void igc_init_function_pointers_82542(struct igc_hw *hw);
+void igc_init_function_pointers_82543(struct igc_hw *hw);
+void igc_init_function_pointers_82540(struct igc_hw *hw);
+void igc_init_function_pointers_82571(struct igc_hw *hw);
+void igc_init_function_pointers_82541(struct igc_hw *hw);
+void igc_init_function_pointers_80003es2lan(struct igc_hw *hw);
+void igc_init_function_pointers_ich8lan(struct igc_hw *hw);
+void igc_init_function_pointers_82575(struct igc_hw *hw);
+void igc_init_function_pointers_vf(struct igc_hw *hw);
+void igc_power_up_fiber_serdes_link(struct igc_hw *hw);
+void igc_shutdown_fiber_serdes_link(struct igc_hw *hw);
+void igc_init_function_pointers_i210(struct igc_hw *hw);
+void igc_init_function_pointers_i225(struct igc_hw *hw);
+
+s32 igc_set_obff_timer(struct igc_hw *hw, u32 itr);
+s32 igc_set_mac_type(struct igc_hw *hw);
+s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device);
+s32 igc_init_mac_params(struct igc_hw *hw);
+s32 igc_init_nvm_params(struct igc_hw *hw);
+s32 igc_init_phy_params(struct igc_hw *hw);
+s32 igc_init_mbx_params(struct igc_hw *hw);
+s32 igc_get_bus_info(struct igc_hw *hw);
+void igc_clear_vfta(struct igc_hw *hw);
+void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value);
+s32 igc_force_mac_fc(struct igc_hw *hw);
+s32 igc_check_for_link(struct igc_hw *hw);
+s32 igc_reset_hw(struct igc_hw *hw);
+s32 igc_init_hw(struct igc_hw *hw);
+s32 igc_setup_link(struct igc_hw *hw);
+s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex);
+s32 igc_disable_pcie_master(struct igc_hw *hw);
+void igc_config_collision_dist(struct igc_hw *hw);
+int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index);
+u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr);
+void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,
+			       u32 mc_addr_count);
+s32 igc_setup_led(struct igc_hw *hw);
+s32 igc_cleanup_led(struct igc_hw *hw);
+s32 igc_check_reset_block(struct igc_hw *hw);
+s32 igc_blink_led(struct igc_hw *hw);
+s32 igc_led_on(struct igc_hw *hw);
+s32 igc_led_off(struct igc_hw *hw);
+s32 igc_id_led_init(struct igc_hw *hw);
+void igc_reset_adaptive(struct igc_hw *hw);
+void igc_update_adaptive(struct igc_hw *hw);
+s32 igc_get_cable_length(struct igc_hw *hw);
+s32 igc_validate_mdi_setting(struct igc_hw *hw);
+s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data);
+s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data);
+s32 igc_write_8bit_ctrl_reg(struct igc_hw *hw, u32 reg, u32 offset,
+			      u8 data);
+s32 igc_get_phy_info(struct igc_hw *hw);
+void igc_release_phy(struct igc_hw *hw);
+s32 igc_acquire_phy(struct igc_hw *hw);
+s32 igc_cfg_on_link_up(struct igc_hw *hw);
+s32 igc_phy_hw_reset(struct igc_hw *hw);
+s32 igc_phy_commit(struct igc_hw *hw);
+void igc_power_up_phy(struct igc_hw *hw);
+void igc_power_down_phy(struct igc_hw *hw);
+s32 igc_read_mac_addr(struct igc_hw *hw);
+s32 igc_read_pba_num(struct igc_hw *hw, u32 *part_num);
+s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size);
+s32 igc_read_pba_length(struct igc_hw *hw, u32 *pba_num_size);
+void igc_reload_nvm(struct igc_hw *hw);
+s32 igc_update_nvm_checksum(struct igc_hw *hw);
+s32 igc_validate_nvm_checksum(struct igc_hw *hw);
+s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
+s32 igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data);
+s32 igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data);
+s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
+s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active);
+s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active);
+bool igc_check_mng_mode(struct igc_hw *hw);
+bool igc_enable_tx_pkt_filtering(struct igc_hw *hw);
+s32 igc_mng_enable_host_if(struct igc_hw *hw);
+s32 igc_mng_host_if_write(struct igc_hw *hw, u8 *buffer, u16 length,
+			    u16 offset, u8 *sum);
+s32 igc_mng_write_cmd_header(struct igc_hw *hw,
+			       struct igc_host_mng_command_header *hdr);
+s32 igc_mng_write_dhcp_info(struct igc_hw *hw, u8 *buffer, u16 length);
+u32  igc_translate_register_82542(u32 reg);
+
+#endif /* _IGC_API_H_ */
--- a/drivers/net/igc/base/igc_base.c
+++ b/drivers/net/igc/base/igc_base.c
@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#include "igc_hw.h"
+#include "igc_i225.h"
+#include "igc_mac.h"
+#include "igc_base.h"
+#include "igc_manage.h"
+
+/**
+ *  igc_acquire_phy_base - Acquire rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire access rights to the correct PHY.
+ **/
+s32 igc_acquire_phy_base(struct igc_hw *hw)
+{
+	u16 mask = IGC_SWFW_PHY0_SM;
+
+	DEBUGFUNC("igc_acquire_phy_base");
+
+	if (hw->bus.func == IGC_FUNC_1)
+		mask = IGC_SWFW_PHY1_SM;
+	else if (hw->bus.func == IGC_FUNC_2)
+		mask = IGC_SWFW_PHY2_SM;
+	else if (hw->bus.func == IGC_FUNC_3)
+		mask = IGC_SWFW_PHY3_SM;
+
+	return hw->mac.ops.acquire_swfw_sync(hw, mask);
+}
+
+/**
+ *  igc_release_phy_base - Release rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  A wrapper to release access rights to the correct PHY.
+ **/
+void igc_release_phy_base(struct igc_hw *hw)
+{
+	u16 mask = IGC_SWFW_PHY0_SM;
+
+	DEBUGFUNC("igc_release_phy_base");
+
+	if (hw->bus.func == IGC_FUNC_1)
+		mask = IGC_SWFW_PHY1_SM;
+	else if (hw->bus.func == IGC_FUNC_2)
+		mask = IGC_SWFW_PHY2_SM;
+	else if (hw->bus.func == IGC_FUNC_3)
+		mask = IGC_SWFW_PHY3_SM;
+
+	hw->mac.ops.release_swfw_sync(hw, mask);
+}
+
+/**
+ *  igc_init_hw_base - Initialize hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  This inits the hardware readying it for operation.
+ **/
+s32 igc_init_hw_base(struct igc_hw *hw)
+{
+	struct igc_mac_info *mac = &hw->mac;
+	s32 ret_val;
+	u16 i, rar_count = mac->rar_entry_count;
+
+	DEBUGFUNC("igc_init_hw_base");
+
+	/* Setup the receive address */
+	igc_init_rx_addrs_generic(hw, rar_count);
+
+	/* Zero out the Multicast HASH table */
+	DEBUGOUT("Zeroing the MTA\n");
+	for (i = 0; i < mac->mta_reg_count; i++)
+		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);
+
+	/* Zero out the Unicast HASH table */
+	DEBUGOUT("Zeroing the UTA\n");
+	for (i = 0; i < mac->uta_reg_count; i++)
+		IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);
+
+	/* Setup link and flow control */
+	ret_val = mac->ops.setup_link(hw);
+	/*
+	 * Clear all of the statistics registers (clear on read).  It is
+	 * important that we do this after we have tried to establish link
+	 * because the symbol error count will increment wildly if there
+	 * is no link.
+	 */
+	igc_clear_hw_cntrs_base_generic(hw);
+
+	return ret_val;
+}
+
+/**
+ * igc_power_down_phy_copper_base - Remove link during PHY power down
+ * @hw: pointer to the HW structure
+ *
+ * In the case of a PHY power down to save power, or to turn off link during a
+ * driver unload, or wake on lan is not enabled, remove the link.
+ **/
+void igc_power_down_phy_copper_base(struct igc_hw *hw)
+{
+	struct igc_phy_info *phy = &hw->phy;
+
+	if (!(phy->ops.check_reset_block))
+		return;
+
+	/* If the management interface is not enabled, then power down */
+	if (!phy->ops.check_reset_block(hw))
+		igc_power_down_phy_copper(hw);
+}
+
+/**
+ *  igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
+ *  @hw: pointer to the HW structure
+ *
+ *  After Rx enable, if manageability is enabled then there is likely some
+ *  bad data at the start of the FIFO and possibly in the DMA FIFO.  This
+ *  function clears the FIFOs and flushes any packets that came in as Rx was
+ *  being enabled.
+ **/
+void igc_rx_fifo_flush_base(struct igc_hw *hw)
+{
+	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
+	int i, ms_wait;
+
+	DEBUGFUNC("igc_rx_fifo_flush_base");
+
+	/* disable IPv6 options as per hardware errata */
+	rfctl = IGC_READ_REG(hw, IGC_RFCTL);
+	rfctl |= IGC_RFCTL_IPV6_EX_DIS;
+	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
+
+	if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))
+		return;
+
+	/* Disable all Rx queues */
+	for (i = 0; i < 4; i++) {
+		rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));
+		IGC_WRITE_REG(hw, IGC_RXDCTL(i),
+				rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
+	}
+	/* Poll all queues to verify they have shut down */
+	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
+		msec_delay(1);
+		rx_enabled = 0;
+		for (i = 0; i < 4; i++)
+			rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));
+		if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
+			break;
+	}
+
+	if (ms_wait == 10)
+		DEBUGOUT("Queue disable timed out after 10ms\n");
+
+	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
+	 * incoming packets are rejected.  Set enable and wait 2ms so that
+	 * any packet that was coming in as RCTL.EN was set is flushed
+	 */
+	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
+
+	rlpml = IGC_READ_REG(hw, IGC_RLPML);
+	IGC_WRITE_REG(hw, IGC_RLPML, 0);
+
+	rctl = IGC_READ_REG(hw, IGC_RCTL);
+	temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
+	temp_rctl |= IGC_RCTL_LPE;
+
+	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);
+	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);
+	IGC_WRITE_FLUSH(hw);
+	msec_delay(2);
+
+	/* Enable Rx queues that were previously enabled and restore our
+	 * previous state
+	 */
+	for (i = 0; i < 4; i++)
+		IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);
+	IGC_WRITE_REG(hw, IGC_RCTL, rctl);
+	IGC_WRITE_FLUSH(hw);
+
+	IGC_WRITE_REG(hw, IGC_RLPML, rlpml);
+	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
+
+	/* Flush receive errors generated by workaround */
+	IGC_READ_REG(hw, IGC_ROC);
+	IGC_READ_REG(hw, IGC_RNBC);
+	IGC_READ_REG(hw, IGC_MPC);
+}
--- a/drivers/net/igc/base/igc_base.h
+++ b/drivers/net/igc/base/igc_base.h
@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_BASE_H_
+#define _IGC_BASE_H_
+
+/* forward declaration */
+s32 igc_init_hw_base(struct igc_hw *hw);
+void igc_power_down_phy_copper_base(struct igc_hw *hw);
+void igc_rx_fifo_flush_base(struct igc_hw *hw);
+s32 igc_acquire_phy_base(struct igc_hw *hw);
+void igc_release_phy_base(struct igc_hw *hw);
+
+/* Transmit Descriptor - Advanced */
+union igc_adv_tx_desc {
+	struct {
+		__le64 buffer_addr;    /* Address of descriptor's data buf */
+		__le32 cmd_type_len;
+		__le32 olinfo_status;
+	} read;
+	struct {
+		__le64 rsvd;       /* Reserved */
+		__le32 nxtseq_seed;
+		__le32 status;
+	} wb;
+};
+
+/* Context descriptors */
+struct igc_adv_tx_context_desc {
+	__le32 vlan_macip_lens;
+	union {
+		__le32 launch_time;
+		__le32 seqnum_seed;
+	} u;
+	__le32 type_tucmd_mlhl;
+	__le32 mss_l4len_idx;
+};
+
+/* Adv Transmit Descriptor Config Masks */
+#define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
+#define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
+#define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
+#define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
+#define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
+#define IGC_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
+#define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
+#define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
+#define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
+#define IGC_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
+#define IGC_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
+#define IGC_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
+#define IGC_ADVTXD_IDX_SHIFT		4  /* Adv desc Index shift */
+#define IGC_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
+#define IGC_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
+#define IGC_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
+/* 1st & Last TSO-full iSCSI PDU*/
+#define IGC_ADVTXD_POPTS_ISCO_FULL	0x00001800
+#define IGC_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
+#define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
+
+/* Advanced Transmit Context Descriptor Config */
+#define IGC_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
+#define IGC_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
+#define IGC_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
+#define IGC_ADVTXD_TUCMD_IPV6		0x00000000  /* IP Packet Type: 0=IPv6 */
+#define IGC_ADVTXD_TUCMD_L4T_UDP	0x00000000  /* L4 Packet TYPE of UDP */
+#define IGC_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
+#define IGC_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
+#define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
+/* IPSec Encrypt Enable for ESP */
+#define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
+/* Req requires Markers and CRC */
+#define IGC_ADVTXD_TUCMD_MKRREQ	0x00002000
+#define IGC_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
+#define IGC_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
+/* Adv ctxt IPSec SA IDX mask */
+#define IGC_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
+/* Adv ctxt IPSec ESP len mask */
+#define IGC_ADVTXD_IPSEC_ESP_LEN_MASK		0x000000FF
+
+#define IGC_RAR_ENTRIES_BASE		16
+
+/* Receive Descriptor - Advanced */
+union igc_adv_rx_desc {
+	struct {
+		__le64 pkt_addr; /* Packet buffer address */
+		__le64 hdr_addr; /* Header buffer address */
+	} read;
+	struct {
+		struct {
+			union {
+				__le32 data;
+				struct {
+					__le16 pkt_info; /*RSS type, Pkt type*/
+					/* Split Header, header buffer len */
+					__le16 hdr_info;
+				} hs_rss;
+			} lo_dword;
+			union {
+				__le32 rss; /* RSS Hash */
+				struct {
+					__le16 ip_id; /* IP id */
+					__le16 csum; /* Packet Checksum */
+				} csum_ip;
+			} hi_dword;
+		} lower;
+		struct {
+			__le32 status_error; /* ext status/error */
+			__le16 length; /* Packet length */
+			__le16 vlan; /* VLAN tag */
+		} upper;
+	} wb;  /* writeback */
+};
+
+/* Additional Transmit Descriptor Control definitions */
+#define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
+
+/* Additional Receive Descriptor Control definitions */
+#define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
+
+/* SRRCTL bit definitions */
+#define IGC_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
+#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
+#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
+
+#endif /* _IGC_BASE_H_ */
--- a/drivers/net/igc/base/igc_defines.h
+++ b/drivers/net/igc/base/igc_defines.h
--- a/drivers/net/igc/base/igc_hw.h
+++ b/drivers/net/igc/base/igc_hw.h
--- a/drivers/net/igc/base/igc_i225.c
+++ b/drivers/net/igc/base/igc_i225.c
--- a/drivers/net/igc/base/igc_i225.h
+++ b/drivers/net/igc/base/igc_i225.h
@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_I225_H_
+#define _IGC_I225_H_
+
+bool igc_get_flash_presence_i225(struct igc_hw *hw);
+s32 igc_update_flash_i225(struct igc_hw *hw);
+s32 igc_update_nvm_checksum_i225(struct igc_hw *hw);
+s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw);
+s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset,
+			      u16 words, u16 *data);
+s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset,
+			     u16 words, u16 *data);
+s32 igc_read_invm_version_i225(struct igc_hw *hw,
+				 struct igc_fw_version *invm_ver);
+s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
+					    u32 burst_counter);
+s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
+					 u32 address);
+s32 igc_check_for_link_i225(struct igc_hw *hw);
+s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);
+void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);
+s32 igc_init_hw_i225(struct igc_hw *hw);
+s32 igc_setup_copper_link_i225(struct igc_hw *hw);
+s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active);
+s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active);
+s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
+		       bool adv100M);
+
+#define ID_LED_DEFAULT_I225		((ID_LED_OFF1_ON2  << 8) | \
+					 (ID_LED_DEF1_DEF2 <<  4) | \
+					 (ID_LED_OFF1_OFF2))
+#define ID_LED_DEFAULT_I225_SERDES	((ID_LED_DEF1_DEF2 << 8) | \
+					 (ID_LED_DEF1_DEF2 <<  4) | \
+					 (ID_LED_OFF1_ON2))
+
+/* NVM offset defaults for I225 devices */
+#define NVM_INIT_CTRL_2_DEFAULT_I225	0X7243
+#define NVM_INIT_CTRL_4_DEFAULT_I225	0x00C1
+#define NVM_LED_1_CFG_DEFAULT_I225	0x0184
+#define NVM_LED_0_2_CFG_DEFAULT_I225	0x200C
+
+#define IGC_MRQC_ENABLE_RSS_4Q		0x00000002
+#define IGC_MRQC_ENABLE_VMDQ			0x00000003
+#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
+#define IGC_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
+#define IGC_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
+#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
+#define IGC_I225_SHADOW_RAM_SIZE		4096
+#define IGC_I225_ERASE_CMD_OPCODE		0x02000000
+#define IGC_I225_WRITE_CMD_OPCODE		0x01000000
+#define IGC_FLSWCTL_DONE			0x40000000
+#define IGC_FLSWCTL_CMDV			0x10000000
+
+/* SRRCTL bit definitions */
+#define IGC_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
+#define IGC_SRRCTL_DESCTYPE_LEGACY		0x00000000
+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
+#define IGC_SRRCTL_DESCTYPE_MASK		0x0E000000
+#define IGC_SRRCTL_DROP_EN			0x80000000
+#define IGC_SRRCTL_BSIZEPKT_MASK		0x0000007F
+#define IGC_SRRCTL_BSIZEHDR_MASK		0x00003F00
+
+#define IGC_RXDADV_RSSTYPE_MASK	0x0000000F
+#define IGC_RXDADV_RSSTYPE_SHIFT	12
+#define IGC_RXDADV_HDRBUFLEN_MASK	0x7FE0
+#define IGC_RXDADV_HDRBUFLEN_SHIFT	5
+#define IGC_RXDADV_SPLITHEADER_EN	0x00001000
+#define IGC_RXDADV_SPH		0x8000
+#define IGC_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
+#define IGC_RXDADV_ERR_HBO		0x00800000
+
+/* RSS Hash results */
+#define IGC_RXDADV_RSSTYPE_NONE	0x00000000
+#define IGC_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
+#define IGC_RXDADV_RSSTYPE_IPV4	0x00000002
+#define IGC_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
+#define IGC_RXDADV_RSSTYPE_IPV6_EX	0x00000004
+#define IGC_RXDADV_RSSTYPE_IPV6	0x00000005
+#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
+#define IGC_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
+#define IGC_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
+#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
+
+/* RSS Packet Types as indicated in the receive descriptor */
+#define IGC_RXDADV_PKTTYPE_ILMASK	0x000000F0
+#define IGC_RXDADV_PKTTYPE_TLMASK	0x00000F00
+#define IGC_RXDADV_PKTTYPE_NONE	0x00000000
+#define IGC_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPV4 hdr present */
+#define IGC_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
+#define IGC_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPV6 hdr present */
+#define IGC_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
+#define IGC_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
+#define IGC_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
+#define IGC_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
+#define IGC_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
+
+#define IGC_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
+#define IGC_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
+#define IGC_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
+#define IGC_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
+#define IGC_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
+#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
+
+#endif
--- a/drivers/net/igc/base/igc_ich8lan.h
+++ b/drivers/net/igc/base/igc_ich8lan.h
@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_ICH8LAN_H_
+#define _IGC_ICH8LAN_H_
+
+#define ICH_FLASH_GFPREG		0x0000
+#define ICH_FLASH_HSFSTS		0x0004
+#define ICH_FLASH_HSFCTL		0x0006
+#define ICH_FLASH_FADDR			0x0008
+#define ICH_FLASH_FDATA0		0x0010
+
+/* Requires up to 10 seconds when MNG might be accessing part. */
+#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
+#define ICH_FLASH_CYCLE_REPEAT_COUNT	10
+
+#define ICH_CYCLE_READ			0
+#define ICH_CYCLE_WRITE			2
+#define ICH_CYCLE_ERASE			3
+
+#define FLASH_GFPREG_BASE_MASK		0x1FFF
+#define FLASH_SECTOR_ADDR_SHIFT		12
+
+#define ICH_FLASH_SEG_SIZE_256		256
+#define ICH_FLASH_SEG_SIZE_4K		4096
+#define ICH_FLASH_SEG_SIZE_8K		8192
+#define ICH_FLASH_SEG_SIZE_64K		65536
+
+#define IGC_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */
+/* FW established a valid mode */
+#define IGC_ICH_FWSM_FW_VALID	0x00008000
+#define IGC_ICH_FWSM_PCIM2PCI	0x01000000 /* ME PCIm-to-PCI active */
+#define IGC_ICH_FWSM_PCIM2PCI_COUNT	2000
+
+#define IGC_ICH_MNG_IAMT_MODE		0x2
+
+#define IGC_FWSM_WLOCK_MAC_MASK	0x0380
+#define IGC_FWSM_WLOCK_MAC_SHIFT	7
+#define IGC_FWSM_ULP_CFG_DONE		0x00000400  /* Low power cfg done */
+
+/* Shared Receive Address Registers */
+#define IGC_SHRAL_PCH_LPT(_i)		(0x05408 + ((_i) * 8))
+#define IGC_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))
+
+#define IGC_H2ME		0x05B50    /* Host to ME */
+#define IGC_H2ME_ULP		0x00000800 /* ULP Indication Bit */
+#define IGC_H2ME_ENFORCE_SETTINGS	0x00001000 /* Enforce Settings */
+
+#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
+				 (ID_LED_OFF1_OFF2 <<  8) | \
+				 (ID_LED_OFF1_ON2  <<  4) | \
+				 (ID_LED_DEF1_DEF2))
+
+#define IGC_ICH_NVM_SIG_WORD		0x13
+#define IGC_ICH_NVM_SIG_MASK		0xC000
+#define IGC_ICH_NVM_VALID_SIG_MASK	0xC0
+#define IGC_ICH_NVM_SIG_VALUE		0x80
+
+#define IGC_ICH8_LAN_INIT_TIMEOUT	1500
+
+/* FEXT register bit definition */
+#define IGC_FEXT_PHY_CABLE_DISCONNECTED	0x00000004
+
+#define IGC_FEXTNVM_SW_CONFIG		1
+#define IGC_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27) /* different on ICH8M */
+
+#define IGC_FEXTNVM3_PHY_CFG_COUNTER_MASK	0x0C000000
+#define IGC_FEXTNVM3_PHY_CFG_COUNTER_50MSEC	0x08000000
+
+#define IGC_FEXTNVM4_BEACON_DURATION_MASK	0x7
+#define IGC_FEXTNVM4_BEACON_DURATION_8USEC	0x7
+#define IGC_FEXTNVM4_BEACON_DURATION_16USEC	0x3
+
+#define IGC_FEXTNVM6_REQ_PLL_CLK	0x00000100
+#define IGC_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
+#define IGC_FEXTNVM6_K1_OFF_ENABLE	0x80000000
+/* bit for disabling packet buffer read */
+#define IGC_FEXTNVM7_DISABLE_PB_READ	0x00040000
+#define IGC_FEXTNVM7_SIDE_CLK_UNGATE	0x00000004
+#define IGC_FEXTNVM7_DISABLE_SMB_PERST	0x00000020
+#define IGC_FEXTNVM9_IOSFSB_CLKGATE_DIS	0x00000800
+#define IGC_FEXTNVM9_IOSFSB_CLKREQ_DIS	0x00001000
+#define IGC_FEXTNVM11_DISABLE_PB_READ		0x00000200
+#define IGC_FEXTNVM11_DISABLE_MULR_FIX	0x00002000
+
+/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
+#define IGC_RXDCTL_THRESH_UNIT_DESC	0x01000000
+
+#define NVM_SIZE_MULTIPLIER 4096  /*multiplier for NVMS field*/
+#define IGC_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
+#define IGC_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
+#define IGC_TARC0_CB_MULTIQ_3_REQ	0x30000000
+#define IGC_TARC0_CB_MULTIQ_2_REQ	0x20000000
+#define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
+
+#define IGC_ICH_RAR_ENTRIES	7
+#define IGC_PCH2_RAR_ENTRIES	5 /* RAR[0], SHRA[0-3] */
+#define IGC_PCH_LPT_RAR_ENTRIES	12 /* RAR[0], SHRA[0-10] */
+
+#define PHY_PAGE_SHIFT		5
+#define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \
+				 ((reg) & MAX_PHY_REG_ADDRESS))
+#define IGP3_KMRN_DIAG	PHY_REG(770, 19) /* KMRN Diagnostic */
+#define IGP3_VR_CTRL	PHY_REG(776, 18) /* Voltage Regulator Control */
+
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300
+#define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200
+
+/* PHY Wakeup Registers and defines */
+#define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)
+#define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)
+#define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)
+#define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)
+#define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)
+#define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
+#define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
+#define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
+#define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
+#define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
+
+#define BM_RCTL_UPE		0x0001 /* Unicast Promiscuous Mode */
+#define BM_RCTL_MPE		0x0002 /* Multicast Promiscuous Mode */
+#define BM_RCTL_MO_SHIFT	3      /* Multicast Offset Shift */
+#define BM_RCTL_MO_MASK		(3 << 3) /* Multicast Offset Mask */
+#define BM_RCTL_BAM		0x0020 /* Broadcast Accept Mode */
+#define BM_RCTL_PMCF		0x0040 /* Pass MAC Control Frames */
+#define BM_RCTL_RFCE		0x0080 /* Rx Flow Control Enable */
+
+#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
+#define HV_MUX_DATA_CTRL	PHY_REG(776, 16)
+#define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400
+#define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004
+#define HV_STATS_PAGE	778
+/* Half-duplex collision counts */
+#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
+#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
+#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
+#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
+#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
+#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
+#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
+#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
+#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision */
+#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
+#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
+#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
+#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
+#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
+
+#define IGC_FCRTV_PCH	0x05F40 /* PCH Flow Control Refresh Timer Value */
+
+#define IGC_NVM_K1_CONFIG	0x1B /* NVM K1 Config Word */
+#define IGC_NVM_K1_ENABLE	0x1  /* NVM Enable K1 bit */
+#define K1_ENTRY_LATENCY	0
+#define K1_MIN_TIME		1
+
+/* SMBus Control Phy Register */
+#define CV_SMB_CTRL		PHY_REG(769, 23)
+#define CV_SMB_CTRL_FORCE_SMBUS	0x0001
+
+/* I218 Ultra Low Power Configuration 1 Register */
+#define I218_ULP_CONFIG1		PHY_REG(779, 16)
+#define I218_ULP_CONFIG1_START		0x0001 /* Start auto ULP config */
+#define I218_ULP_CONFIG1_IND		0x0004 /* Pwr up from ULP indication */
+#define I218_ULP_CONFIG1_STICKY_ULP	0x0010 /* Set sticky ULP mode */
+#define I218_ULP_CONFIG1_INBAND_EXIT	0x0020 /* Inband on ULP exit */
+#define I218_ULP_CONFIG1_WOL_HOST	0x0040 /* WoL Host on ULP exit */
+#define I218_ULP_CONFIG1_RESET_TO_SMBUS	0x0100 /* Reset to SMBus mode */
+/* enable ULP even if when phy powered down via lanphypc */
+#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC	0x0400
+/* disable clear of sticky ULP on PERST */
+#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST	0x0800
+#define I218_ULP_CONFIG1_DISABLE_SMB_PERST	0x1000 /* Disable on PERST# */
+
+
+/* SMBus Address Phy Register */
+#define HV_SMB_ADDR		PHY_REG(768, 26)
+#define HV_SMB_ADDR_MASK	0x007F
+#define HV_SMB_ADDR_PEC_EN	0x0200
+#define HV_SMB_ADDR_VALID	0x0080
+#define HV_SMB_ADDR_FREQ_MASK		0x1100
+#define HV_SMB_ADDR_FREQ_LOW_SHIFT	8
+#define HV_SMB_ADDR_FREQ_HIGH_SHIFT	12
+
+/* Strapping Option Register - RO */
+#define IGC_STRAP			0x0000C
+#define IGC_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000
+#define IGC_STRAP_SMBUS_ADDRESS_SHIFT	17
+#define IGC_STRAP_SMT_FREQ_MASK	0x00003000
+#define IGC_STRAP_SMT_FREQ_SHIFT	12
+
+/* OEM Bits Phy Register */
+#define HV_OEM_BITS		PHY_REG(768, 25)
+#define HV_OEM_BITS_LPLU	0x0004 /* Low Power Link Up */
+#define HV_OEM_BITS_GBE_DIS	0x0040 /* Gigabit Disable */
+#define HV_OEM_BITS_RESTART_AN	0x0400 /* Restart Auto-negotiation */
+
+/* KMRN Mode Control */
+#define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)
+#define HV_KMRN_MDIO_SLOW	0x0400
+
+/* KMRN FIFO Control and Status */
+#define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12
+
+/* PHY Power Management Control */
+#define HV_PM_CTRL		PHY_REG(770, 17)
+#define HV_PM_CTRL_K1_CLK_REQ		0x200
+#define HV_PM_CTRL_K1_ENABLE		0x4000
+
+#define I217_PLL_CLOCK_GATE_REG	PHY_REG(772, 28)
+#define I217_PLL_CLOCK_GATE_MASK	0x07FF
+
+#define SW_FLAG_TIMEOUT		1000 /* SW Semaphore flag timeout in ms */
+
+/* Inband Control */
+#define I217_INBAND_CTRL				PHY_REG(770, 18)
+#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00
+#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8
+
+/* Low Power Idle GPIO Control */
+#define I217_LPI_GPIO_CTRL			PHY_REG(772, 18)
+#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI		0x0800
+
+/* PHY Low Power Idle Control */
+#define I82579_LPI_CTRL				PHY_REG(772, 20)
+#define I82579_LPI_CTRL_100_ENABLE		0x2000
+#define I82579_LPI_CTRL_1000_ENABLE		0x4000
+#define I82579_LPI_CTRL_ENABLE_MASK		0x6000
+
+/* 82579 DFT Control */
+#define I82579_DFT_CTRL			PHY_REG(769, 20)
+#define I82579_DFT_CTRL_GATE_PHY_RESET	0x0040 /* Gate PHY Reset on MAC Reset */
+
+/* Extended Management Interface (EMI) Registers */
+#define I82579_EMI_ADDR		0x10
+#define I82579_EMI_DATA		0x11
+#define I82579_LPI_UPDATE_TIMER	0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_MSE_THRESHOLD	0x084F /* 82579 Mean Square Error Threshold */
+#define I82577_MSE_THRESHOLD	0x0887 /* 82577 Mean Square Error Threshold */
+#define I82579_MSE_LINK_DOWN	0x2411 /* MSE count before dropping link */
+#define I82579_RX_CONFIG		0x3412 /* Receive configuration */
+#define I82579_LPI_PLL_SHUT		0x4412 /* LPI PLL Shut Enable */
+#define I82579_EEE_PCS_STATUS		0x182E	/* IEEE MMD Register 3.1 >> 8 */
+#define I82579_EEE_CAPABILITY		0x0410 /* IEEE MMD Register 3.20 */
+#define I82579_EEE_ADVERTISEMENT	0x040E /* IEEE MMD Register 7.60 */
+#define I82579_EEE_LP_ABILITY		0x040F /* IEEE MMD Register 7.61 */
+#define I82579_EEE_100_SUPPORTED	(1 << 1) /* 100BaseTx EEE */
+#define I82579_EEE_1000_SUPPORTED	(1 << 2) /* 1000BaseTx EEE */
+#define I82579_LPI_100_PLL_SHUT	(1 << 2) /* 100M LPI PLL Shut Enabled */
+#define I217_EEE_PCS_STATUS	0x9401   /* IEEE MMD Register 3.1 */
+#define I217_EEE_CAPABILITY	0x8000   /* IEEE MMD Register 3.20 */
+#define I217_EEE_ADVERTISEMENT	0x8001   /* IEEE MMD Register 7.60 */
+#define I217_EEE_LP_ABILITY	0x8002   /* IEEE MMD Register 7.61 */
+#define I217_RX_CONFIG		0xB20C /* Receive configuration */
+
+#define IGC_EEE_RX_LPI_RCVD	0x0400	/* Tx LP idle received */
+#define IGC_EEE_TX_LPI_RCVD	0x0800	/* Rx LP idle received */
+
+/* Intel Rapid Start Technology Support */
+#define I217_PROXY_CTRL		BM_PHY_REG(BM_WUC_PAGE, 70)
+#define I217_PROXY_CTRL_AUTO_DISABLE	0x0080
+#define I217_CGFREG			PHY_REG(772, 29)
+#define I217_CGFREG_ENABLE_MTA_RESET	0x0002
+#define I217_MEMPWR			PHY_REG(772, 26)
+#define I217_MEMPWR_DISABLE_SMB_RELEASE	0x0010
+
+/* Receive Address Initial CRC Calculation */
+#define IGC_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
+
+#define IGC_PCI_VENDOR_ID_REGISTER	0x00
+
+#define IGC_PCI_REVISION_ID_REG	0x08
+void igc_set_kmrn_lock_loss_workaround_ich8lan(struct igc_hw *hw,
+						 bool state);
+void igc_igp3_phy_powerdown_workaround_ich8lan(struct igc_hw *hw);
+void igc_gig_downshift_workaround_ich8lan(struct igc_hw *hw);
+void igc_suspend_workarounds_ich8lan(struct igc_hw *hw);
+u32 igc_resume_workarounds_pchlan(struct igc_hw *hw);
+s32 igc_configure_k1_ich8lan(struct igc_hw *hw, bool k1_enable);
+s32 igc_configure_k0s_lpt(struct igc_hw *hw, u8 entry_latency, u8 min_time);
+void igc_copy_rx_addrs_to_phy_ich8lan(struct igc_hw *hw);
+s32 igc_lv_jumbo_workaround_ich8lan(struct igc_hw *hw, bool enable);
+s32 igc_read_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 *data);
+s32 igc_write_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 data);
+s32 igc_set_eee_pchlan(struct igc_hw *hw);
+s32 igc_enable_ulp_lpt_lp(struct igc_hw *hw, bool to_sx);
+s32 igc_disable_ulp_lpt_lp(struct igc_hw *hw, bool force);
+#endif /* _IGC_ICH8LAN_H_ */
+void igc_demote_ltr(struct igc_hw *hw, bool demote, bool link);
--- a/drivers/net/igc/base/igc_mac.c
+++ b/drivers/net/igc/base/igc_mac.c
--- a/drivers/net/igc/base/igc_mac.h
+++ b/drivers/net/igc/base/igc_mac.h
@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_MAC_H_
+#define _IGC_MAC_H_
+
+void igc_init_mac_ops_generic(struct igc_hw *hw);
+#define IGC_REMOVED(a) (0)
+void igc_null_mac_generic(struct igc_hw *hw);
+s32  igc_null_ops_generic(struct igc_hw *hw);
+s32  igc_null_link_info(struct igc_hw *hw, u16 *s, u16 *d);
+bool igc_null_mng_mode(struct igc_hw *hw);
+void igc_null_update_mc(struct igc_hw *hw, u8 *h, u32 a);
+void igc_null_write_vfta(struct igc_hw *hw, u32 a, u32 b);
+int  igc_null_rar_set(struct igc_hw *hw, u8 *h, u32 a);
+s32  igc_blink_led_generic(struct igc_hw *hw);
+s32  igc_check_for_copper_link_generic(struct igc_hw *hw);
+s32  igc_check_for_fiber_link_generic(struct igc_hw *hw);
+s32  igc_check_for_serdes_link_generic(struct igc_hw *hw);
+s32  igc_cleanup_led_generic(struct igc_hw *hw);
+s32  igc_commit_fc_settings_generic(struct igc_hw *hw);
+s32  igc_poll_fiber_serdes_link_generic(struct igc_hw *hw);
+s32  igc_config_fc_after_link_up_generic(struct igc_hw *hw);
+s32  igc_disable_pcie_master_generic(struct igc_hw *hw);
+s32  igc_force_mac_fc_generic(struct igc_hw *hw);
+s32  igc_get_auto_rd_done_generic(struct igc_hw *hw);
+s32  igc_get_bus_info_pci_generic(struct igc_hw *hw);
+s32  igc_get_bus_info_pcie_generic(struct igc_hw *hw);
+void igc_set_lan_id_single_port(struct igc_hw *hw);
+void igc_set_lan_id_multi_port_pci(struct igc_hw *hw);
+s32  igc_get_hw_semaphore_generic(struct igc_hw *hw);
+s32  igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
+					       u16 *duplex);
+s32  igc_get_speed_and_duplex_fiber_serdes_generic(struct igc_hw *hw,
+						     u16 *speed, u16 *duplex);
+s32  igc_id_led_init_generic(struct igc_hw *hw);
+s32  igc_led_on_generic(struct igc_hw *hw);
+s32  igc_led_off_generic(struct igc_hw *hw);
+void igc_update_mc_addr_list_generic(struct igc_hw *hw,
+				       u8 *mc_addr_list, u32 mc_addr_count);
+s32  igc_set_default_fc_generic(struct igc_hw *hw);
+s32  igc_set_fc_watermarks_generic(struct igc_hw *hw);
+s32  igc_setup_fiber_serdes_link_generic(struct igc_hw *hw);
+s32  igc_setup_led_generic(struct igc_hw *hw);
+s32  igc_setup_link_generic(struct igc_hw *hw);
+s32  igc_validate_mdi_setting_crossover_generic(struct igc_hw *hw);
+s32  igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,
+				       u32 offset, u8 data);
+
+u32  igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr);
+
+void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw);
+void igc_clear_vfta_generic(struct igc_hw *hw);
+void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count);
+void igc_pcix_mmrbc_workaround_generic(struct igc_hw *hw);
+void igc_put_hw_semaphore_generic(struct igc_hw *hw);
+s32  igc_check_alt_mac_addr_generic(struct igc_hw *hw);
+void igc_reset_adaptive_generic(struct igc_hw *hw);
+void igc_set_pcie_no_snoop_generic(struct igc_hw *hw, u32 no_snoop);
+void igc_update_adaptive_generic(struct igc_hw *hw);
+void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value);
+
+#endif
--- a/drivers/net/igc/base/igc_manage.c
+++ b/drivers/net/igc/base/igc_manage.c
@ -0,0 +1,547 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#include "igc_api.h"
+#include "igc_manage.h"
+
+/**
+ *  igc_calculate_checksum - Calculate checksum for buffer
+ *  @buffer: pointer to EEPROM
+ *  @length: size of EEPROM to calculate a checksum for
+ *
+ *  Calculates the checksum for some buffer on a specified length.  The
+ *  checksum calculated is returned.
+ **/
+u8 igc_calculate_checksum(u8 *buffer, u32 length)
+{
+	u32 i;
+	u8 sum = 0;
+
+	DEBUGFUNC("igc_calculate_checksum");
+
+	if (!buffer)
+		return 0;
+
+	for (i = 0; i < length; i++)
+		sum += buffer[i];
+
+	return (u8)(0 - sum);
+}
+
+/**
+ *  igc_mng_enable_host_if_generic - Checks host interface is enabled
+ *  @hw: pointer to the HW structure
+ *
+ *  Returns IGC_success upon success, else IGC_ERR_HOST_INTERFACE_COMMAND
+ *
+ *  This function checks whether the HOST IF is enabled for command operation
+ *  and also checks whether the previous command is completed.  It busy waits
+ *  in case of previous command is not completed.
+ **/
+s32 igc_mng_enable_host_if_generic(struct igc_hw *hw)
+{
+	u32 hicr;
+	u8 i;
+
+	DEBUGFUNC("igc_mng_enable_host_if_generic");
+
+	if (!hw->mac.arc_subsystem_valid) {
+		DEBUGOUT("ARC subsystem not valid.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	/* Check that the host interface is enabled. */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	if (!(hicr & IGC_HICR_EN)) {
+		DEBUGOUT("IGC_HOST_EN bit disabled.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+	/* check the previous command is completed */
+	for (i = 0; i < IGC_MNG_DHCP_COMMAND_TIMEOUT; i++) {
+		hicr = IGC_READ_REG(hw, IGC_HICR);
+		if (!(hicr & IGC_HICR_C))
+			break;
+		msec_delay_irq(1);
+	}
+
+	if (i == IGC_MNG_DHCP_COMMAND_TIMEOUT) {
+		DEBUGOUT("Previous command timeout failed .\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	return IGC_SUCCESS;
+}
+
+/**
+ *  igc_check_mng_mode_generic - Generic check management mode
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the firmware semaphore register and returns true (>0) if
+ *  manageability is enabled, else false (0).
+ **/
+bool igc_check_mng_mode_generic(struct igc_hw *hw)
+{
+	u32 fwsm = IGC_READ_REG(hw, IGC_FWSM);
+
+	DEBUGFUNC("igc_check_mng_mode_generic");
+
+
+	return (fwsm & IGC_FWSM_MODE_MASK) ==
+		(IGC_MNG_IAMT_MODE << IGC_FWSM_MODE_SHIFT);
+}
+
+/**
+ *  igc_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
+ *  @hw: pointer to the HW structure
+ *
+ *  Enables packet filtering on transmit packets if manageability is enabled
+ *  and host interface is enabled.
+ **/
+bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw)
+{
+	struct igc_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
+	u32 *buffer = (u32 *)&hw->mng_cookie;
+	u32 offset;
+	s32 ret_val, hdr_csum, csum;
+	u8 i, len;
+
+	DEBUGFUNC("igc_enable_tx_pkt_filtering_generic");
+
+	hw->mac.tx_pkt_filtering = true;
+
+	/* No manageability, no filtering */
+	if (!hw->mac.ops.check_mng_mode(hw)) {
+		hw->mac.tx_pkt_filtering = false;
+		return hw->mac.tx_pkt_filtering;
+	}
+
+	/* If we can't read from the host interface for whatever
+	 * reason, disable filtering.
+	 */
+	ret_val = igc_mng_enable_host_if_generic(hw);
+	if (ret_val != IGC_SUCCESS) {
+		hw->mac.tx_pkt_filtering = false;
+		return hw->mac.tx_pkt_filtering;
+	}
+
+	/* Read in the header.  Length and offset are in dwords. */
+	len    = IGC_MNG_DHCP_COOKIE_LENGTH >> 2;
+	offset = IGC_MNG_DHCP_COOKIE_OFFSET >> 2;
+	for (i = 0; i < len; i++)
+		*(buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF,
+							   offset + i);
+	hdr_csum = hdr->checksum;
+	hdr->checksum = 0;
+	csum = igc_calculate_checksum((u8 *)hdr,
+					IGC_MNG_DHCP_COOKIE_LENGTH);
+	/* If either the checksums or signature don't match, then
+	 * the cookie area isn't considered valid, in which case we
+	 * take the safe route of assuming Tx filtering is enabled.
+	 */
+	if (hdr_csum != csum || hdr->signature != IGC_IAMT_SIGNATURE) {
+		hw->mac.tx_pkt_filtering = true;
+		return hw->mac.tx_pkt_filtering;
+	}
+
+	/* Cookie area is valid, make the final check for filtering. */
+	if (!(hdr->status & IGC_MNG_DHCP_COOKIE_STATUS_PARSING))
+		hw->mac.tx_pkt_filtering = false;
+
+	return hw->mac.tx_pkt_filtering;
+}
+
+/**
+ *  igc_mng_write_cmd_header_generic - Writes manageability command header
+ *  @hw: pointer to the HW structure
+ *  @hdr: pointer to the host interface command header
+ *
+ *  Writes the command header after does the checksum calculation.
+ **/
+s32 igc_mng_write_cmd_header_generic(struct igc_hw *hw,
+				      struct igc_host_mng_command_header *hdr)
+{
+	u16 i, length = sizeof(struct igc_host_mng_command_header);
+
+	DEBUGFUNC("igc_mng_write_cmd_header_generic");
+
+	/* Write the whole command header structure with new checksum. */
+
+	hdr->checksum = igc_calculate_checksum((u8 *)hdr, length);
+
+	length >>= 2;
+	/* Write the relevant command block into the ram area. */
+	for (i = 0; i < length; i++) {
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,
+					*((u32 *)hdr + i));
+		IGC_WRITE_FLUSH(hw);
+	}
+
+	return IGC_SUCCESS;
+}
+
+/**
+ *  igc_mng_host_if_write_generic - Write to the manageability host interface
+ *  @hw: pointer to the HW structure
+ *  @buffer: pointer to the host interface buffer
+ *  @length: size of the buffer
+ *  @offset: location in the buffer to write to
+ *  @sum: sum of the data (not checksum)
+ *
+ *  This function writes the buffer content at the offset given on the host if.
+ *  It also does alignment considerations to do the writes in most efficient
+ *  way.  Also fills up the sum of the buffer in *buffer parameter.
+ **/
+s32 igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,
+				    u16 length, u16 offset, u8 *sum)
+{
+	u8 *tmp;
+	u8 *bufptr = buffer;
+	u32 data = 0;
+	u16 remaining, i, j, prev_bytes;
+
+	DEBUGFUNC("igc_mng_host_if_write_generic");
+
+	/* sum = only sum of the data and it is not checksum */
+
+	if (length == 0 || offset + length > IGC_HI_MAX_MNG_DATA_LENGTH)
+		return -IGC_ERR_PARAM;
+
+	tmp = (u8 *)&data;
+	prev_bytes = offset & 0x3;
+	offset >>= 2;
+
+	if (prev_bytes) {
+		data = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset);
+		for (j = prev_bytes; j < sizeof(u32); j++) {
+			*(tmp + j) = *bufptr++;
+			*sum += *(tmp + j);
+		}
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset, data);
+		length -= j - prev_bytes;
+		offset++;
+	}
+
+	remaining = length & 0x3;
+	length -= remaining;
+
+	/* Calculate length in DWORDs */
+	length >>= 2;
+
+	/* The device driver writes the relevant command block into the
+	 * ram area.
+	 */
+	for (i = 0; i < length; i++) {
+		for (j = 0; j < sizeof(u32); j++) {
+			*(tmp + j) = *bufptr++;
+			*sum += *(tmp + j);
+		}
+
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,
+					    data);
+	}
+	if (remaining) {
+		for (j = 0; j < sizeof(u32); j++) {
+			if (j < remaining)
+				*(tmp + j) = *bufptr++;
+			else
+				*(tmp + j) = 0;
+
+			*sum += *(tmp + j);
+		}
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,
+					    data);
+	}
+
+	return IGC_SUCCESS;
+}
+
+/**
+ *  igc_mng_write_dhcp_info_generic - Writes DHCP info to host interface
+ *  @hw: pointer to the HW structure
+ *  @buffer: pointer to the host interface
+ *  @length: size of the buffer
+ *
+ *  Writes the DHCP information to the host interface.
+ **/
+s32 igc_mng_write_dhcp_info_generic(struct igc_hw *hw, u8 *buffer,
+				      u16 length)
+{
+	struct igc_host_mng_command_header hdr;
+	s32 ret_val;
+	u32 hicr;
+
+	DEBUGFUNC("igc_mng_write_dhcp_info_generic");
+
+	hdr.command_id = IGC_MNG_DHCP_TX_PAYLOAD_CMD;
+	hdr.command_length = length;
+	hdr.reserved1 = 0;
+	hdr.reserved2 = 0;
+	hdr.checksum = 0;
+
+	/* Enable the host interface */
+	ret_val = igc_mng_enable_host_if_generic(hw);
+	if (ret_val)
+		return ret_val;
+
+	/* Populate the host interface with the contents of "buffer". */
+	ret_val = igc_mng_host_if_write_generic(hw, buffer, length,
+						sizeof(hdr), &hdr.checksum);
+	if (ret_val)
+		return ret_val;
+
+	/* Write the manageability command header */
+	ret_val = igc_mng_write_cmd_header_generic(hw, &hdr);
+	if (ret_val)
+		return ret_val;
+
+	/* Tell the ARC a new command is pending. */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
+
+	return IGC_SUCCESS;
+}
+
+/**
+ *  igc_enable_mng_pass_thru - Check if management passthrough is needed
+ *  @hw: pointer to the HW structure
+ *
+ *  Verifies the hardware needs to leave interface enabled so that frames can
+ *  be directed to and from the management interface.
+ **/
+bool igc_enable_mng_pass_thru(struct igc_hw *hw)
+{
+	u32 manc;
+	u32 fwsm, factps;
+
+	DEBUGFUNC("igc_enable_mng_pass_thru");
+
+	if (!hw->mac.asf_firmware_present)
+		return false;
+
+	manc = IGC_READ_REG(hw, IGC_MANC);
+
+	if (!(manc & IGC_MANC_RCV_TCO_EN))
+		return false;
+
+	if (hw->mac.has_fwsm) {
+		fwsm = IGC_READ_REG(hw, IGC_FWSM);
+		factps = IGC_READ_REG(hw, IGC_FACTPS);
+
+		if (!(factps & IGC_FACTPS_MNGCG) &&
+		    ((fwsm & IGC_FWSM_MODE_MASK) ==
+		     (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT)))
+			return true;
+	} else if ((hw->mac.type == igc_82574) ||
+		   (hw->mac.type == igc_82583)) {
+		u16 data;
+		s32 ret_val;
+
+		factps = IGC_READ_REG(hw, IGC_FACTPS);
+		ret_val = igc_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
+		if (ret_val)
+			return false;
+
+		if (!(factps & IGC_FACTPS_MNGCG) &&
+		    ((data & IGC_NVM_INIT_CTRL2_MNGM) ==
+		     (igc_mng_mode_pt << 13)))
+			return true;
+	} else if ((manc & IGC_MANC_SMBUS_EN) &&
+		   !(manc & IGC_MANC_ASF_EN)) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ *  igc_host_interface_command - Writes buffer to host interface
+ *  @hw: pointer to the HW structure
+ *  @buffer: contains a command to write
+ *  @length: the byte length of the buffer, must be multiple of 4 bytes
+ *
+ *  Writes a buffer to the Host Interface.  Upon success, returns IGC_SUCCESS
+ *  else returns IGC_ERR_HOST_INTERFACE_COMMAND.
+ **/
+s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length)
+{
+	u32 hicr, i;
+
+	DEBUGFUNC("igc_host_interface_command");
+
+	if (!(hw->mac.arc_subsystem_valid)) {
+		DEBUGOUT("Hardware doesn't support host interface command.\n");
+		return IGC_SUCCESS;
+	}
+
+	if (!hw->mac.asf_firmware_present) {
+		DEBUGOUT("Firmware is not present.\n");
+		return IGC_SUCCESS;
+	}
+
+	if (length == 0 || length & 0x3 ||
+	    length > IGC_HI_MAX_BLOCK_BYTE_LENGTH) {
+		DEBUGOUT("Buffer length failure.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	/* Check that the host interface is enabled. */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	if (!(hicr & IGC_HICR_EN)) {
+		DEBUGOUT("IGC_HOST_EN bit disabled.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	/* Calculate length in DWORDs */
+	length >>= 2;
+
+	/* The device driver writes the relevant command block
+	 * into the ram area.
+	 */
+	for (i = 0; i < length; i++)
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,
+					    *((u32 *)buffer + i));
+
+	/* Setting this bit tells the ARC that a new command is pending. */
+	IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
+
+	for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
+		hicr = IGC_READ_REG(hw, IGC_HICR);
+		if (!(hicr & IGC_HICR_C))
+			break;
+		msec_delay(1);
+	}
+
+	/* Check command successful completion. */
+	if (i == IGC_HI_COMMAND_TIMEOUT ||
+	    (!(IGC_READ_REG(hw, IGC_HICR) & IGC_HICR_SV))) {
+		DEBUGOUT("Command has failed with no status valid.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	for (i = 0; i < length; i++)
+		*((u32 *)buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw,
+								  IGC_HOST_IF,
+								  i);
+
+	return IGC_SUCCESS;
+}
+
+/**
+ *  igc_load_firmware - Writes proxy FW code buffer to host interface
+ *                        and execute.
+ *  @hw: pointer to the HW structure
+ *  @buffer: contains a firmware to write
+ *  @length: the byte length of the buffer, must be multiple of 4 bytes
+ *
+ *  Upon success returns IGC_SUCCESS, returns IGC_ERR_CONFIG if not enabled
+ *  in HW else returns IGC_ERR_HOST_INTERFACE_COMMAND.
+ **/
+s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length)
+{
+	u32 hicr, hibba, fwsm, icr, i;
+
+	DEBUGFUNC("igc_load_firmware");
+
+	if (hw->mac.type < igc_i210) {
+		DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
+		return -IGC_ERR_CONFIG;
+	}
+
+	/* Check that the host interface is enabled. */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	if (!(hicr & IGC_HICR_EN)) {
+		DEBUGOUT("IGC_HOST_EN bit disabled.\n");
+		return -IGC_ERR_CONFIG;
+	}
+	if (!(hicr & IGC_HICR_MEMORY_BASE_EN)) {
+		DEBUGOUT("IGC_HICR_MEMORY_BASE_EN bit disabled.\n");
+		return -IGC_ERR_CONFIG;
+	}
+
+	if (length == 0 || length & 0x3 || length > IGC_HI_FW_MAX_LENGTH) {
+		DEBUGOUT("Buffer length failure.\n");
+		return -IGC_ERR_INVALID_ARGUMENT;
+	}
+
+	/* Clear notification from ROM-FW by reading ICR register */
+	icr = IGC_READ_REG(hw, IGC_ICR_V2);
+
+	/* Reset ROM-FW */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	hicr |= IGC_HICR_FW_RESET_ENABLE;
+	IGC_WRITE_REG(hw, IGC_HICR, hicr);
+	hicr |= IGC_HICR_FW_RESET;
+	IGC_WRITE_REG(hw, IGC_HICR, hicr);
+	IGC_WRITE_FLUSH(hw);
+
+	/* Wait till MAC notifies about its readiness after ROM-FW reset */
+	for (i = 0; i < (IGC_HI_COMMAND_TIMEOUT * 2); i++) {
+		icr = IGC_READ_REG(hw, IGC_ICR_V2);
+		if (icr & IGC_ICR_MNG)
+			break;
+		msec_delay(1);
+	}
+
+	/* Check for timeout */
+	if (i == IGC_HI_COMMAND_TIMEOUT) {
+		DEBUGOUT("FW reset failed.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	/* Wait till MAC is ready to accept new FW code */
+	for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
+		fwsm = IGC_READ_REG(hw, IGC_FWSM);
+		if ((fwsm & IGC_FWSM_FW_VALID) &&
+		    ((fwsm & IGC_FWSM_MODE_MASK) >> IGC_FWSM_MODE_SHIFT ==
+		    IGC_FWSM_HI_EN_ONLY_MODE))
+			break;
+		msec_delay(1);
+	}
+
+	/* Check for timeout */
+	if (i == IGC_HI_COMMAND_TIMEOUT) {
+		DEBUGOUT("FW reset failed.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	/* Calculate length in DWORDs */
+	length >>= 2;
+
+	/* The device driver writes the relevant FW code block
+	 * into the ram area in DWORDs via 1kB ram addressing window.
+	 */
+	for (i = 0; i < length; i++) {
+		if (!(i % IGC_HI_FW_BLOCK_DWORD_LENGTH)) {
+			/* Point to correct 1kB ram window */
+			hibba = IGC_HI_FW_BASE_ADDRESS +
+				((IGC_HI_FW_BLOCK_DWORD_LENGTH << 2) *
+				(i / IGC_HI_FW_BLOCK_DWORD_LENGTH));
+
+			IGC_WRITE_REG(hw, IGC_HIBBA, hibba);
+		}
+
+		IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF,
+					    i % IGC_HI_FW_BLOCK_DWORD_LENGTH,
+					    *((u32 *)buffer + i));
+	}
+
+	/* Setting this bit tells the ARC that a new FW is ready to execute. */
+	hicr = IGC_READ_REG(hw, IGC_HICR);
+	IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
+
+	for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
+		hicr = IGC_READ_REG(hw, IGC_HICR);
+		if (!(hicr & IGC_HICR_C))
+			break;
+		msec_delay(1);
+	}
+
+	/* Check for successful FW start. */
+	if (i == IGC_HI_COMMAND_TIMEOUT) {
+		DEBUGOUT("New FW did not start within timeout period.\n");
+		return -IGC_ERR_HOST_INTERFACE_COMMAND;
+	}
+
+	return IGC_SUCCESS;
+}
--- a/drivers/net/igc/base/igc_manage.h
+++ b/drivers/net/igc/base/igc_manage.h
@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_MANAGE_H_
+#define _IGC_MANAGE_H_
+
+bool igc_check_mng_mode_generic(struct igc_hw *hw);
+bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw);
+s32  igc_mng_enable_host_if_generic(struct igc_hw *hw);
+s32  igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,
+				     u16 length, u16 offset, u8 *sum);
+s32  igc_mng_write_cmd_header_generic(struct igc_hw *hw,
+				     struct igc_host_mng_command_header *hdr);
+s32  igc_mng_write_dhcp_info_generic(struct igc_hw *hw,
+				       u8 *buffer, u16 length);
+bool igc_enable_mng_pass_thru(struct igc_hw *hw);
+u8 igc_calculate_checksum(u8 *buffer, u32 length);
+s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length);
+s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length);
+
+enum igc_mng_mode {
+	igc_mng_mode_none = 0,
+	igc_mng_mode_asf,
+	igc_mng_mode_pt,
+	igc_mng_mode_ipmi,
+	igc_mng_mode_host_if_only
+};
+
+#define IGC_FACTPS_MNGCG			0x20000000
+
+#define IGC_FWSM_MODE_MASK			0xE
+#define IGC_FWSM_MODE_SHIFT			1
+#define IGC_FWSM_FW_VALID			0x00008000
+#define IGC_FWSM_HI_EN_ONLY_MODE		0x4
+
+#define IGC_MNG_IAMT_MODE			0x3
+#define IGC_MNG_DHCP_COOKIE_LENGTH		0x10
+#define IGC_MNG_DHCP_COOKIE_OFFSET		0x6F0
+#define IGC_MNG_DHCP_COMMAND_TIMEOUT		10
+#define IGC_MNG_DHCP_TX_PAYLOAD_CMD		64
+#define IGC_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
+#define IGC_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
+
+#define IGC_VFTA_ENTRY_SHIFT			5
+#define IGC_VFTA_ENTRY_MASK			0x7F
+#define IGC_VFTA_ENTRY_BIT_SHIFT_MASK		0x1F
+
+#define IGC_HI_MAX_BLOCK_BYTE_LENGTH		1792 /* Num of bytes in range */
+#define IGC_HI_MAX_BLOCK_DWORD_LENGTH		448 /* Num of dwords in range */
+#define IGC_HI_COMMAND_TIMEOUT		500 /* Process HI cmd limit */
+#define IGC_HI_FW_BASE_ADDRESS		0x10000
+#define IGC_HI_FW_MAX_LENGTH			(64 * 1024) /* Num of bytes */
+#define IGC_HI_FW_BLOCK_DWORD_LENGTH		256 /* Num of DWORDs per page */
+#define IGC_HICR_MEMORY_BASE_EN		0x200 /* MB Enable bit - RO */
+#define IGC_HICR_EN			0x01  /* Enable bit - RO */
+/* Driver sets this bit when done to put command in RAM */
+#define IGC_HICR_C			0x02
+#define IGC_HICR_SV			0x04  /* Status Validity */
+#define IGC_HICR_FW_RESET_ENABLE	0x40
+#define IGC_HICR_FW_RESET		0x80
+
+/* Intel(R) Active Management Technology signature */
+#define IGC_IAMT_SIGNATURE		0x544D4149
+#endif
--- a/drivers/net/igc/base/igc_nvm.c
+++ b/drivers/net/igc/base/igc_nvm.c
--- a/drivers/net/igc/base/igc_nvm.h
+++ b/drivers/net/igc/base/igc_nvm.h
@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_NVM_H_
+#define _IGC_NVM_H_
+
+struct igc_pba {
+	u16 word[2];
+	u16 *pba_block;
+};
+
+struct igc_fw_version {
+	u32 etrack_id;
+	u16 eep_major;
+	u16 eep_minor;
+	u16 eep_build;
+
+	u8 invm_major;
+	u8 invm_minor;
+	u8 invm_img_type;
+
+	bool or_valid;
+	u16 or_major;
+	u16 or_build;
+	u16 or_patch;
+};
+
+
+void igc_init_nvm_ops_generic(struct igc_hw *hw);
+s32  igc_null_read_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
+void igc_null_nvm_generic(struct igc_hw *hw);
+s32  igc_null_led_default(struct igc_hw *hw, u16 *data);
+s32  igc_null_write_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
+s32  igc_acquire_nvm_generic(struct igc_hw *hw);
+
+s32  igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg);
+s32  igc_read_mac_addr_generic(struct igc_hw *hw);
+s32  igc_read_pba_num_generic(struct igc_hw *hw, u32 *pba_num);
+s32  igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,
+				   u32 pba_num_size);
+s32  igc_read_pba_length_generic(struct igc_hw *hw, u32 *pba_num_size);
+s32 igc_read_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,
+		       u32 eeprom_buf_size, u16 max_pba_block_size,
+		       struct igc_pba *pba);
+s32 igc_write_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,
+			u32 eeprom_buf_size, struct igc_pba *pba);
+s32 igc_get_pba_block_size(struct igc_hw *hw, u16 *eeprom_buf,
+			     u32 eeprom_buf_size, u16 *pba_block_size);
+s32  igc_read_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
+s32  igc_read_nvm_microwire(struct igc_hw *hw, u16 offset,
+			      u16 words, u16 *data);
+s32  igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words,
+			 u16 *data);
+s32  igc_valid_led_default_generic(struct igc_hw *hw, u16 *data);
+s32  igc_validate_nvm_checksum_generic(struct igc_hw *hw);
+s32  igc_write_nvm_microwire(struct igc_hw *hw, u16 offset,
+			       u16 words, u16 *data);
+s32  igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words,
+			 u16 *data);
+s32  igc_update_nvm_checksum_generic(struct igc_hw *hw);
+void igc_stop_nvm(struct igc_hw *hw);
+void igc_release_nvm_generic(struct igc_hw *hw);
+void igc_get_fw_version(struct igc_hw *hw,
+			  struct igc_fw_version *fw_vers);
+
+#define IGC_STM_OPCODE	0xDB00
+
+#endif
--- a/drivers/net/igc/base/igc_osdep.c
+++ b/drivers/net/igc/base/igc_osdep.c
@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2020
+ */
+
+#include "igc_api.h"
+
+/*
+ * NOTE: the following routines using the igc
+ * naming style are provided to the shared
+ * code but are OS specific
+ */
+
+void
+igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
+{
+	(void)hw;
+	(void)reg;
+	(void)value;
+}
+
+void
+igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
+{
+	(void)hw;
+	(void)reg;
+	*value = 0;
+}
+
+void
+igc_pci_set_mwi(struct igc_hw *hw)
+{
+	(void)hw;
+}
+
+void
+igc_pci_clear_mwi(struct igc_hw *hw)
+{
+	(void)hw;
+}
+
+/*
+ * Read the PCI Express capabilities
+ */
+int32_t
+igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
+{
+	(void)hw;
+	(void)reg;
+	(void)value;
+	return IGC_NOT_IMPLEMENTED;
+}
+
+/*
+ * Write the PCI Express capabilities
+ */
+int32_t
+igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
+{
+	(void)hw;
+	(void)reg;
+	(void)value;
+
+	return IGC_NOT_IMPLEMENTED;
+}
--- a/drivers/net/igc/base/igc_osdep.h
+++ b/drivers/net/igc/base/igc_osdep.h
@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2020
+ */
+
+
+#ifndef _IGC_OSDEP_H_
+#define _IGC_OSDEP_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include <stdbool.h>
+#include <rte_common.h>
+#include <rte_cycles.h>
+#include <rte_log.h>
+#include <rte_debug.h>
+#include <rte_byteorder.h>
+#include <rte_io.h>
+
+#include "../igc_logs.h"
+
+#define DELAY(x) rte_delay_us(x)
+#define usec_delay(x) DELAY(x)
+#define usec_delay_irq(x) DELAY(x)
+#define msec_delay(x) DELAY(1000 * (x))
+#define msec_delay_irq(x) DELAY(1000 * (x))
+
+#define DEBUGFUNC(F)            DEBUGOUT(F "\n")
+#define DEBUGOUT(S, args...)    PMD_DRV_LOG_RAW(DEBUG, S, ##args)
+#define DEBUGOUT1(S, args...)   DEBUGOUT(S, ##args)
+#define DEBUGOUT2(S, args...)   DEBUGOUT(S, ##args)
+#define DEBUGOUT3(S, args...)   DEBUGOUT(S, ##args)
+#define DEBUGOUT6(S, args...)   DEBUGOUT(S, ##args)
+#define DEBUGOUT7(S, args...)   DEBUGOUT(S, ##args)
+
+#define UNREFERENCED_PARAMETER(_p)	(void)(_p)
+#define UNREFERENCED_1PARAMETER(_p)	(void)(_p)
+#define UNREFERENCED_2PARAMETER(_p, _q)	\
+	do {				\
+		(void)(_p);		\
+		(void)(_q);		\
+	} while (0)
+#define UNREFERENCED_3PARAMETER(_p, _q, _r)	\
+	do {					\
+		(void)(_p);			\
+		(void)(_q);			\
+		(void)(_r);			\
+	} while (0)
+#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)	\
+	do {					\
+		(void)(_p);			\
+		(void)(_q);			\
+		(void)(_r);			\
+		(void)(_s);			\
+	} while (0)
+
+#define	CMD_MEM_WRT_INVALIDATE	0x0010  /* BIT_4 */
+
+/* Mutex used in the shared code */
+#define IGC_MUTEX                     uintptr_t
+#define IGC_MUTEX_INIT(mutex)         (*(mutex) = 0)
+#define IGC_MUTEX_LOCK(mutex)         (*(mutex) = 1)
+#define IGC_MUTEX_UNLOCK(mutex)       (*(mutex) = 0)
+
+typedef uint64_t	u64;
+typedef uint32_t	u32;
+typedef uint16_t	u16;
+typedef uint8_t		u8;
+typedef int64_t		s64;
+typedef int32_t		s32;
+typedef int16_t		s16;
+typedef int8_t		s8;
+
+#define __le16		u16
+#define __le32		u32
+#define __le64		u64
+
+#define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS)
+
+#define IGC_PCI_REG(reg)	rte_read32(reg)
+
+#define IGC_PCI_REG16(reg)	rte_read16(reg)
+
+#define IGC_PCI_REG_WRITE(reg, value)			\
+	rte_write32((rte_cpu_to_le_32(value)), reg)
+
+#define IGC_PCI_REG_WRITE_RELAXED(reg, value)		\
+	rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
+
+#define IGC_PCI_REG_WRITE16(reg, value)		\
+	rte_write16((rte_cpu_to_le_16(value)), reg)
+
+#define IGC_PCI_REG_ADDR(hw, reg) \
+	((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
+
+#define IGC_PCI_REG_ARRAY_ADDR(hw, reg, index) \
+	IGC_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
+
+#define IGC_PCI_REG_FLASH_ADDR(hw, reg) \
+	((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
+
+static inline uint32_t igc_read_addr(volatile void *addr)
+{
+	return rte_le_to_cpu_32(IGC_PCI_REG(addr));
+}
+
+static inline uint16_t igc_read_addr16(volatile void *addr)
+{
+	return rte_le_to_cpu_16(IGC_PCI_REG16(addr));
+}
+
+/* Register READ/WRITE macros */
+
+#define IGC_READ_REG(hw, reg) \
+	igc_read_addr(IGC_PCI_REG_ADDR((hw), (reg)))
+
+#define IGC_READ_REG_LE_VALUE(hw, reg) \
+	rte_read32(IGC_PCI_REG_ADDR((hw), (reg)))
+
+#define IGC_WRITE_REG(hw, reg, value) \
+	IGC_PCI_REG_WRITE(IGC_PCI_REG_ADDR((hw), (reg)), (value))
+
+#define IGC_WRITE_REG_LE_VALUE(hw, reg, value) \
+	rte_write32(value, IGC_PCI_REG_ADDR((hw), (reg)))
+
+#define IGC_READ_REG_ARRAY(hw, reg, index) \
+	IGC_PCI_REG(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
+
+#define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \
+	IGC_PCI_REG_WRITE(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), \
+			(value))
+
+#define IGC_READ_REG_ARRAY_DWORD IGC_READ_REG_ARRAY
+#define IGC_WRITE_REG_ARRAY_DWORD IGC_WRITE_REG_ARRAY
+
+/*
+ * To be able to do IO write, we need to map IO BAR
+ * (bar 2/4 depending on device).
+ * Right now mapping multiple BARs is not supported by DPDK.
+ * Fortunatelly we need it only for legacy hw support.
+ */
+
+#define IGC_WRITE_REG_IO(hw, reg, value) \
+	IGC_WRITE_REG(hw, reg, value)
+
+/*
+ * Tested on I217/I218 chipset.
+ */
+
+#define IGC_READ_FLASH_REG(hw, reg) \
+	igc_read_addr(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
+
+#define IGC_READ_FLASH_REG16(hw, reg)  \
+	igc_read_addr16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))
+
+#define IGC_WRITE_FLASH_REG(hw, reg, value)  \
+	IGC_PCI_REG_WRITE(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
+
+#define IGC_WRITE_FLASH_REG16(hw, reg, value) \
+	IGC_PCI_REG_WRITE16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
+
+#endif /* _IGC_OSDEP_H_ */
--- a/drivers/net/igc/base/igc_phy.c
+++ b/drivers/net/igc/base/igc_phy.c
--- a/drivers/net/igc/base/igc_phy.h
+++ b/drivers/net/igc/base/igc_phy.h
@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_PHY_H_
+#define _IGC_PHY_H_
+
+void igc_init_phy_ops_generic(struct igc_hw *hw);
+s32  igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
+void igc_null_phy_generic(struct igc_hw *hw);
+s32  igc_null_lplu_state(struct igc_hw *hw, bool active);
+s32  igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_null_set_page(struct igc_hw *hw, u16 data);
+s32 igc_read_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,
+			     u8 dev_addr, u8 *data);
+s32 igc_write_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,
+			      u8 dev_addr, u8 data);
+s32  igc_check_downshift_generic(struct igc_hw *hw);
+s32  igc_check_polarity_m88(struct igc_hw *hw);
+s32  igc_check_polarity_igp(struct igc_hw *hw);
+s32  igc_check_polarity_ife(struct igc_hw *hw);
+s32  igc_check_reset_block_generic(struct igc_hw *hw);
+s32  igc_phy_setup_autoneg(struct igc_hw *hw);
+s32  igc_copper_link_autoneg(struct igc_hw *hw);
+s32  igc_copper_link_setup_igp(struct igc_hw *hw);
+s32  igc_copper_link_setup_m88(struct igc_hw *hw);
+s32  igc_copper_link_setup_m88_gen2(struct igc_hw *hw);
+s32  igc_phy_force_speed_duplex_igp(struct igc_hw *hw);
+s32  igc_phy_force_speed_duplex_m88(struct igc_hw *hw);
+s32  igc_phy_force_speed_duplex_ife(struct igc_hw *hw);
+s32  igc_get_cable_length_m88(struct igc_hw *hw);
+s32  igc_get_cable_length_m88_gen2(struct igc_hw *hw);
+s32  igc_get_cable_length_igp_2(struct igc_hw *hw);
+s32  igc_get_cfg_done_generic(struct igc_hw *hw);
+s32  igc_get_phy_id(struct igc_hw *hw);
+s32  igc_get_phy_info_igp(struct igc_hw *hw);
+s32  igc_get_phy_info_m88(struct igc_hw *hw);
+s32  igc_get_phy_info_ife(struct igc_hw *hw);
+s32  igc_phy_sw_reset_generic(struct igc_hw *hw);
+void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
+s32  igc_phy_hw_reset_generic(struct igc_hw *hw);
+s32  igc_phy_reset_dsp_generic(struct igc_hw *hw);
+s32  igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_set_page_igp(struct igc_hw *hw, u16 page);
+s32  igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
+s32  igc_setup_copper_link_generic(struct igc_hw *hw);
+s32  igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
+				u32 usec_interval, bool *success);
+s32  igc_phy_init_script_igp3(struct igc_hw *hw);
+enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
+s32  igc_determine_phy_address(struct igc_hw *hw);
+s32  igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
+s32  igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
+s32  igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data);
+void igc_power_up_phy_copper(struct igc_hw *hw);
+void igc_power_down_phy_copper(struct igc_hw *hw);
+s32  igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data);
+s32  igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data);
+s32  igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_link_stall_workaround_hv(struct igc_hw *hw);
+s32  igc_copper_link_setup_82577(struct igc_hw *hw);
+s32  igc_check_polarity_82577(struct igc_hw *hw);
+s32  igc_get_phy_info_82577(struct igc_hw *hw);
+s32  igc_phy_force_speed_duplex_82577(struct igc_hw *hw);
+s32  igc_get_cable_length_82577(struct igc_hw *hw);
+s32  igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data);
+s32  igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
+s32  igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
+s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data);
+s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,
+			     bool line_override);
+bool igc_is_mphy_ready(struct igc_hw *hw);
+
+s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
+			 u16 *data);
+s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
+			  u16 data);
+
+#define IGC_MAX_PHY_ADDR		8
+
+/* IGP01E1000 Specific Registers */
+#define IGP01IGC_PHY_PORT_CONFIG	0x10 /* Port Config */
+#define IGP01IGC_PHY_PORT_STATUS	0x11 /* Status */
+#define IGP01IGC_PHY_PORT_CTRL	0x12 /* Control */
+#define IGP01IGC_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
+#define IGP01IGC_GMII_FIFO		0x14 /* GMII FIFO */
+#define IGP02IGC_PHY_POWER_MGMT	0x19 /* Power Management */
+#define IGP01IGC_PHY_PAGE_SELECT	0x1F /* Page Select */
+#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
+#define IGP_PAGE_SHIFT			5
+#define PHY_REG_MASK			0x1F
+
+/* GS40G - I210 PHY defines */
+#define GS40G_PAGE_SELECT		0x16
+#define GS40G_PAGE_SHIFT		16
+#define GS40G_OFFSET_MASK		0xFFFF
+#define GS40G_PAGE_2			0x20000
+#define GS40G_MAC_REG2			0x15
+#define GS40G_MAC_LB			0x4140
+#define GS40G_MAC_SPEED_1G		0X0006
+#define GS40G_COPPER_SPEC		0x0010
+
+#define IGC_I225_PHPM			0x0E14 /* I225 PHY Power Management */
+#define IGC_I225_PHPM_DIS_1000_D3	0x0008 /* Disable 1G in D3 */
+#define IGC_I225_PHPM_LINK_ENERGY	0x0010 /* Link Energy Detect */
+#define IGC_I225_PHPM_GO_LINKD	0x0020 /* Go Link Disconnect */
+#define IGC_I225_PHPM_DIS_1000	0x0040 /* Disable 1G globally */
+#define IGC_I225_PHPM_SPD_B2B_EN	0x0080 /* Smart Power Down Back2Back */
+#define IGC_I225_PHPM_RST_COMPL	0x0100 /* PHY Reset Completed */
+#define IGC_I225_PHPM_DIS_100_D3	0x0200 /* Disable 100M in D3 */
+#define IGC_I225_PHPM_ULP		0x0400 /* Ultra Low-Power Mode */
+#define IGC_I225_PHPM_DIS_2500	0x0800 /* Disable 2.5G globally */
+#define IGC_I225_PHPM_DIS_2500_D3	0x1000 /* Disable 2.5G in D3 */
+/* GPY211 - I225 defines */
+#define GPY_MMD_MASK			0xFFFF0000
+#define GPY_MMD_SHIFT			16
+#define GPY_REG_MASK			0x0000FFFF
+/* BM/HV Specific Registers */
+#define BM_PORT_CTRL_PAGE		769
+#define BM_WUC_PAGE			800
+#define BM_WUC_ADDRESS_OPCODE		0x11
+#define BM_WUC_DATA_OPCODE		0x12
+#define BM_WUC_ENABLE_PAGE		BM_PORT_CTRL_PAGE
+#define BM_WUC_ENABLE_REG		17
+#define BM_WUC_ENABLE_BIT		(1 << 2)
+#define BM_WUC_HOST_WU_BIT		(1 << 4)
+#define BM_WUC_ME_WU_BIT		(1 << 5)
+
+#define PHY_UPPER_SHIFT			21
+
+#define BM_PHY_REG(page, reg)	(	\
+	__extension__ ({		\
+		typeof(page) _page = (page);	\
+		typeof(reg) _reg = (reg);	\
+		(_reg & MAX_PHY_REG_ADDRESS) |	\
+		((_page & 0xFFFF) << PHY_PAGE_SHIFT) |	\
+		((_reg & ~MAX_PHY_REG_ADDRESS) <<	\
+		(PHY_UPPER_SHIFT - PHY_PAGE_SHIFT));	\
+	}))
+
+#define BM_PHY_REG_PAGE(offset) \
+	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
+
+#define BM_PHY_REG_NUM(offset)	(	\
+	__extension__ ({		\
+		typeof(offset) _offset = (offset);	\
+		(u16)((_offset & MAX_PHY_REG_ADDRESS) |	\
+		((_offset >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &	\
+		~MAX_PHY_REG_ADDRESS));			\
+	}))
+
+#define HV_INTC_FC_PAGE_START		768
+#define I82578_ADDR_REG			29
+#define I82577_ADDR_REG			16
+#define I82577_CFG_REG			22
+#define I82577_CFG_ASSERT_CRS_ON_TX	(1 << 15)
+#define I82577_CFG_ENABLE_DOWNSHIFT	(3 << 10) /* auto downshift */
+#define I82577_CTRL_REG			23
+
+/* 82577 specific PHY registers */
+#define I82577_PHY_CTRL_2		18
+#define I82577_PHY_LBK_CTRL		19
+#define I82577_PHY_STATUS_2		26
+#define I82577_PHY_DIAG_STATUS		31
+
+/* I82577 PHY Status 2 */
+#define I82577_PHY_STATUS2_REV_POLARITY		0x0400
+#define I82577_PHY_STATUS2_MDIX			0x0800
+#define I82577_PHY_STATUS2_SPEED_MASK		0x0300
+#define I82577_PHY_STATUS2_SPEED_1000MBPS	0x0200
+
+/* I82577 PHY Control 2 */
+#define I82577_PHY_CTRL2_MANUAL_MDIX		0x0200
+#define I82577_PHY_CTRL2_AUTO_MDI_MDIX		0x0400
+#define I82577_PHY_CTRL2_MDIX_CFG_MASK		0x0600
+
+/* I82577 PHY Diagnostics Status */
+#define I82577_DSTATUS_CABLE_LENGTH		0x03FC
+#define I82577_DSTATUS_CABLE_LENGTH_SHIFT	2
+
+/* 82580 PHY Power Management */
+#define IGC_82580_PHY_POWER_MGMT	0xE14
+#define IGC_82580_PM_SPD		0x0001 /* Smart Power Down */
+#define IGC_82580_PM_D0_LPLU		0x0002 /* For D0a states */
+#define IGC_82580_PM_D3_LPLU		0x0004 /* For all other states */
+#define IGC_82580_PM_GO_LINKD		0x0020 /* Go Link Disconnect */
+
+#define IGC_MPHY_DIS_ACCESS		0x80000000 /* disable_access bit */
+#define IGC_MPHY_ENA_ACCESS		0x40000000 /* enable_access bit */
+#define IGC_MPHY_BUSY			0x00010000 /* busy bit */
+#define IGC_MPHY_ADDRESS_FNC_OVERRIDE	0x20000000 /* fnc_override bit */
+#define IGC_MPHY_ADDRESS_MASK		0x0000FFFF /* address mask */
+
+/* BM PHY Copper Specific Control 1 */
+#define BM_CS_CTRL1			16
+
+/* BM PHY Copper Specific Status */
+#define BM_CS_STATUS			17
+#define BM_CS_STATUS_LINK_UP		0x0400
+#define BM_CS_STATUS_RESOLVED		0x0800
+#define BM_CS_STATUS_SPEED_MASK		0xC000
+#define BM_CS_STATUS_SPEED_1000		0x8000
+
+/* 82577 Mobile Phy Status Register */
+#define HV_M_STATUS			26
+#define HV_M_STATUS_AUTONEG_COMPLETE	0x1000
+#define HV_M_STATUS_SPEED_MASK		0x0300
+#define HV_M_STATUS_SPEED_1000		0x0200
+#define HV_M_STATUS_SPEED_100		0x0100
+#define HV_M_STATUS_LINK_UP		0x0040
+
+#define IGP01IGC_PHY_PCS_INIT_REG	0x00B4
+#define IGP01IGC_PHY_POLARITY_MASK	0x0078
+
+#define IGP01IGC_PSCR_AUTO_MDIX	0x1000
+#define IGP01IGC_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
+
+#define IGP01IGC_PSCFR_SMART_SPEED	0x0080
+
+/* Enable flexible speed on link-up */
+#define IGP01IGC_GMII_FLEX_SPD	0x0010
+#define IGP01IGC_GMII_SPD		0x0020 /* Enable SPD */
+
+#define IGP02IGC_PM_SPD		0x0001 /* Smart Power Down */
+#define IGP02IGC_PM_D0_LPLU		0x0002 /* For D0a states */
+#define IGP02IGC_PM_D3_LPLU		0x0004 /* For all other states */
+
+#define IGP01IGC_PLHR_SS_DOWNGRADE	0x8000
+
+#define IGP01IGC_PSSR_POLARITY_REVERSED	0x0002
+#define IGP01IGC_PSSR_MDIX		0x0800
+#define IGP01IGC_PSSR_SPEED_MASK	0xC000
+#define IGP01IGC_PSSR_SPEED_1000MBPS	0xC000
+
+#define IGP02IGC_PHY_CHANNEL_NUM	4
+#define IGP02IGC_PHY_AGC_A		0x11B1
+#define IGP02IGC_PHY_AGC_B		0x12B1
+#define IGP02IGC_PHY_AGC_C		0x14B1
+#define IGP02IGC_PHY_AGC_D		0x18B1
+
+#define IGP02IGC_AGC_LENGTH_SHIFT	9   /* Course=15:13, Fine=12:9 */
+#define IGP02IGC_AGC_LENGTH_MASK	0x7F
+#define IGP02IGC_AGC_RANGE		15
+
+#define IGC_CABLE_LENGTH_UNDEFINED	0xFF
+
+#define IGC_KMRNCTRLSTA_OFFSET	0x001F0000
+#define IGC_KMRNCTRLSTA_OFFSET_SHIFT	16
+#define IGC_KMRNCTRLSTA_REN		0x00200000
+#define IGC_KMRNCTRLSTA_CTRL_OFFSET	0x1    /* Kumeran Control */
+#define IGC_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
+#define IGC_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
+#define IGC_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
+#define IGC_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
+#define IGC_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
+#define IGC_KMRNCTRLSTA_K1_CONFIG	0x7
+#define IGC_KMRNCTRLSTA_K1_ENABLE	0x0002 /* enable K1 */
+#define IGC_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
+#define IGC_KMRNCTRLSTA_K0S_CTRL	0x1E	/* Kumeran K0s Control */
+#define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT	0
+#define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT	4
+#define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK	\
+	(3 << IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
+#define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
+	(7 << IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
+#define IGC_KMRNCTRLSTA_OP_MODES	0x1F   /* Kumeran Modes of Operation */
+#define IGC_KMRNCTRLSTA_OP_MODES_LSC2CSC	0x0002 /* change LSC to CSC */
+
+#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
+#define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Ctrl */
+#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Ctrl */
+#define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
+
+/* IFE PHY Extended Status Control */
+#define IFE_PESC_POLARITY_REVERSED	0x0100
+
+/* IFE PHY Special Control */
+#define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
+#define IFE_PSC_FORCE_POLARITY		0x0020
+
+/* IFE PHY Special Control and LED Control */
+#define IFE_PSCL_PROBE_MODE		0x0020
+#define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
+#define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
+
+/* IFE PHY MDIX Control */
+#define IFE_PMC_MDIX_STATUS		0x0020 /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_FORCE_MDIX		0x0040 /* 1=force MDI-X, 0=force MDI */
+#define IFE_PMC_AUTO_MDIX		0x0080 /* 1=enable auto, 0=disable */
+
+/* SFP modules ID memory locations */
+#define IGC_SFF_IDENTIFIER_OFFSET	0x00
+#define IGC_SFF_IDENTIFIER_SFF	0x02
+#define IGC_SFF_IDENTIFIER_SFP	0x03
+
+#define IGC_SFF_ETH_FLAGS_OFFSET	0x06
+/* Flags for SFP modules compatible with ETH up to 1Gb */
+struct sfp_igc_flags {
+	u8 igc_base_sx:1;
+	u8 igc_base_lx:1;
+	u8 igc_base_cx:1;
+	u8 igc_base_t:1;
+	u8 e100_base_lx:1;
+	u8 e100_base_fx:1;
+	u8 e10_base_bx10:1;
+	u8 e10_base_px:1;
+};
+
+/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
+#define IGC_SFF_VENDOR_OUI_TYCO	0x00407600
+#define IGC_SFF_VENDOR_OUI_FTL	0x00906500
+#define IGC_SFF_VENDOR_OUI_AVAGO	0x00176A00
+#define IGC_SFF_VENDOR_OUI_INTEL	0x001B2100
+
+#endif
--- a/drivers/net/igc/base/igc_regs.h
+++ b/drivers/net/igc/base/igc_regs.h
@ -0,0 +1,724 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _IGC_REGS_H_
+#define _IGC_REGS_H_
+
+/* General Register Descriptions */
+#define IGC_CTRL	0x00000  /* Device Control - RW */
+#define IGC_CTRL_DUP	0x00004  /* Device Control Duplicate (Shadow) - RW */
+#define IGC_STATUS	0x00008  /* Device Status - RO */
+#define IGC_EECD	0x00010  /* EEPROM/Flash Control - RW */
+/* NVM  Register Descriptions */
+#define IGC_EERD		0x12014  /* EEprom mode read - RW */
+#define IGC_EEWR		0x12018  /* EEprom mode write - RW */
+#define IGC_CTRL_EXT	0x00018  /* Extended Device Control - RW */
+#define IGC_MDIC	0x00020  /* MDI Control - RW */
+#define IGC_MDICNFG	0x00E04  /* MDI Config - RW */
+#define IGC_REGISTER_SET_SIZE		0x20000 /* CSR Size */
+#define IGC_EEPROM_INIT_CTRL_WORD_2	0x0F /* EEPROM Init Ctrl Word 2 */
+#define IGC_EEPROM_PCIE_CTRL_WORD_2	0x28 /* EEPROM PCIe Ctrl Word 2 */
+#define IGC_BARCTRL			0x5BBC /* BAR ctrl reg */
+#define IGC_BARCTRL_FLSIZE		0x0700 /* BAR ctrl Flsize */
+#define IGC_BARCTRL_CSRSIZE		0x2000 /* BAR ctrl CSR size */
+#define IGC_MPHY_ADDR_CTRL	0x0024 /* GbE MPHY Address Control */
+#define IGC_MPHY_DATA		0x0E10 /* GBE MPHY Data */
+#define IGC_MPHY_STAT		0x0E0C /* GBE MPHY Statistics */
+#define IGC_PPHY_CTRL		0x5b48 /* PCIe PHY Control */
+#define IGC_I350_BARCTRL		0x5BFC /* BAR ctrl reg */
+#define IGC_I350_DTXMXPKTSZ		0x355C /* Maximum sent packet size reg*/
+#define IGC_SCTL	0x00024  /* SerDes Control - RW */
+#define IGC_FCAL	0x00028  /* Flow Control Address Low - RW */
+#define IGC_FCAH	0x0002C  /* Flow Control Address High -RW */
+#define IGC_FEXT	0x0002C  /* Future Extended - RW */
+#define IGC_I225_FLSWCTL	0x12048 /* FLASH control register */
+#define IGC_I225_FLSWDATA	0x1204C /* FLASH data register */
+#define IGC_I225_FLSWCNT	0x12050 /* FLASH Access Counter */
+#define IGC_I225_FLSECU	0x12114 /* FLASH Security */
+#define IGC_FEXTNVM	0x00028  /* Future Extended NVM - RW */
+#define IGC_FEXTNVM3	0x0003C  /* Future Extended NVM 3 - RW */
+#define IGC_FEXTNVM4	0x00024  /* Future Extended NVM 4 - RW */
+#define IGC_FEXTNVM5	0x00014  /* Future Extended NVM 5 - RW */
+#define IGC_FEXTNVM6	0x00010  /* Future Extended NVM 6 - RW */
+#define IGC_FEXTNVM7	0x000E4  /* Future Extended NVM 7 - RW */
+#define IGC_FEXTNVM9	0x5BB4  /* Future Extended NVM 9 - RW */
+#define IGC_FEXTNVM11	0x5BBC  /* Future Extended NVM 11 - RW */
+#define IGC_PCIEANACFG	0x00F18 /* PCIE Analog Config */
+#define IGC_FCT	0x00030  /* Flow Control Type - RW */
+#define IGC_CONNSW	0x00034  /* Copper/Fiber switch control - RW */
+#define IGC_VET	0x00038  /* VLAN Ether Type - RW */
+#define IGC_ICR			0x01500  /* Intr Cause Read - RC/W1C */
+#define IGC_ITR	0x000C4  /* Interrupt Throttling Rate - RW */
+#define IGC_ICS			0x01504  /* Intr Cause Set - WO */
+#define IGC_IMS			0x01508  /* Intr Mask Set/Read - RW */
+#define IGC_IMC			0x0150C  /* Intr Mask Clear - WO */
+#define IGC_IAM			0x01510  /* Intr Ack Auto Mask- RW */
+#define IGC_IVAR	0x000E4  /* Interrupt Vector Allocation Register - RW */
+#define IGC_SVCR	0x000F0
+#define IGC_SVT	0x000F4
+#define IGC_LPIC	0x000FC  /* Low Power IDLE control */
+#define IGC_RCTL	0x00100  /* Rx Control - RW */
+#define IGC_FCTTV	0x00170  /* Flow Control Transmit Timer Value - RW */
+#define IGC_TXCW	0x00178  /* Tx Configuration Word - RW */
+#define IGC_RXCW	0x00180  /* Rx Configuration Word - RO */
+#define IGC_PBA_ECC	0x01100  /* PBA ECC Register */
+#define IGC_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
+#define IGC_EITR(_n)	(0x01680 + (0x4 * (_n)))
+#define IGC_EICS	0x01520  /* Ext. Interrupt Cause Set - W0 */
+#define IGC_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
+#define IGC_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
+#define IGC_EIAC	0x0152C  /* Ext. Interrupt Auto Clear - RW */
+#define IGC_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
+#define IGC_GPIE	0x01514  /* General Purpose Interrupt Enable - RW */
+#define IGC_IVAR0	0x01700  /* Interrupt Vector Allocation (array) - RW */
+#define IGC_IVAR_MISC	0x01740 /* IVAR for "other" causes - RW */
+#define IGC_TCTL	0x00400  /* Tx Control - RW */
+#define IGC_TCTL_EXT	0x00404  /* Extended Tx Control - RW */
+#define IGC_TIPG	0x00410  /* Tx Inter-packet gap -RW */
+#define IGC_TBT	0x00448  /* Tx Burst Timer - RW */
+#define IGC_AIT	0x00458  /* Adaptive Interframe Spacing Throttle - RW */
+#define IGC_LEDCTL	0x00E00  /* LED Control - RW */
+#define IGC_LEDMUX	0x08130  /* LED MUX Control */
+#define IGC_EXTCNF_CTRL	0x00F00  /* Extended Configuration Control */
+#define IGC_EXTCNF_SIZE	0x00F08  /* Extended Configuration Size */
+#define IGC_PHY_CTRL	0x00F10  /* PHY Control Register in CSR */
+#define IGC_POEMB	IGC_PHY_CTRL /* PHY OEM Bits */
+#define IGC_PBA	0x01000  /* Packet Buffer Allocation - RW */
+#define IGC_PBS	0x01008  /* Packet Buffer Size */
+#define IGC_PBECCSTS	0x0100C  /* Packet Buffer ECC Status - RW */
+#define IGC_IOSFPC	0x00F28  /* TX corrupted data  */
+#define IGC_EEMNGCTL	0x01010  /* MNG EEprom Control */
+#define IGC_EEMNGCTL_I210	0x01010  /* i210 MNG EEprom Mode Control */
+#define IGC_EEMNGCTL_I225	0x01010  /* i225 MNG EEprom Mode Control */
+#define IGC_EEARBC	0x01024  /* EEPROM Auto Read Bus Control */
+#define IGC_EEARBC_I210	0x12024 /* EEPROM Auto Read Bus Control */
+#define IGC_EEARBC_I225	0x12024 /* EEPROM Auto Read Bus Control */
+#define IGC_FLASHT	0x01028  /* FLASH Timer Register */
+#define IGC_FLSWCTL	0x01030  /* FLASH control register */
+#define IGC_FLSWDATA	0x01034  /* FLASH data register */
+#define IGC_FLSWCNT	0x01038  /* FLASH Access Counter */
+#define IGC_FLOP	0x0103C  /* FLASH Opcode Register */
+#define IGC_I2CCMD	0x01028  /* SFPI2C Command Register - RW */
+#define IGC_I2CPARAMS	0x0102C /* SFPI2C Parameters Register - RW */
+#define IGC_I2CBB_EN	0x00000100  /* I2C - Bit Bang Enable */
+#define IGC_I2C_CLK_OUT	0x00000200  /* I2C- Clock */
+#define IGC_I2C_DATA_OUT	0x00000400  /* I2C- Data Out */
+#define IGC_I2C_DATA_OE_N	0x00000800  /* I2C- Data Output Enable */
+#define IGC_I2C_DATA_IN	0x00001000  /* I2C- Data In */
+#define IGC_I2C_CLK_OE_N	0x00002000  /* I2C- Clock Output Enable */
+#define IGC_I2C_CLK_IN	0x00004000  /* I2C- Clock In */
+#define IGC_I2C_CLK_STRETCH_DIS	0x00008000 /* I2C- Dis Clk Stretching */
+#define IGC_WDSTP	0x01040  /* Watchdog Setup - RW */
+#define IGC_SWDSTS	0x01044  /* SW Device Status - RW */
+#define IGC_FRTIMER	0x01048  /* Free Running Timer - RW */
+#define IGC_TCPTIMER	0x0104C  /* TCP Timer - RW */
+#define IGC_VPDDIAG	0x01060  /* VPD Diagnostic - RO */
+#define IGC_ICR_V2	0x01500  /* Intr Cause - new location - RC */
+#define IGC_ICS_V2	0x01504  /* Intr Cause Set - new location - WO */
+#define IGC_IMS_V2	0x01508  /* Intr Mask Set/Read - new location - RW */
+#define IGC_IMC_V2	0x0150C  /* Intr Mask Clear - new location - WO */
+#define IGC_IAM_V2	0x01510  /* Intr Ack Auto Mask - new location - RW */
+#define IGC_ERT	0x02008  /* Early Rx Threshold - RW */
+#define IGC_FCRTL	0x02160  /* Flow Control Receive Threshold Low - RW */
+#define IGC_FCRTH	0x02168  /* Flow Control Receive Threshold High - RW */
+#define IGC_PSRCTL	0x02170  /* Packet Split Receive Control - RW */
+#define IGC_RDFH	0x02410  /* Rx Data FIFO Head - RW */
+#define IGC_RDFT	0x02418  /* Rx Data FIFO Tail - RW */
+#define IGC_RDFHS	0x02420  /* Rx Data FIFO Head Saved - RW */
+#define IGC_RDFTS	0x02428  /* Rx Data FIFO Tail Saved - RW */
+#define IGC_RDFPC	0x02430  /* Rx Data FIFO Packet Count - RW */
+#define IGC_PBRTH	0x02458  /* PB Rx Arbitration Threshold - RW */
+#define IGC_FCRTV	0x02460  /* Flow Control Refresh Timer Value - RW */
+/* Split and Replication Rx Control - RW */
+#define IGC_RDPUMB	0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
+#define IGC_RDPUAD	0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
+#define IGC_RDPUWD	0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
+#define IGC_RDPURD	0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
+#define IGC_RDPUCTL	0x025DC  /* DMA Rx Descriptor uC Control - RW */
+#define IGC_PBDIAG	0x02458  /* Packet Buffer Diagnostic - RW */
+#define IGC_RXPBS	0x02404  /* Rx Packet Buffer Size - RW */
+#define IGC_IRPBS	0x02404 /* Same as RXPBS, renamed for newer Si - RW */
+#define IGC_PBRWAC	0x024E8 /* Rx packet buffer wrap around counter - RO */
+#define IGC_RDTR	0x02820  /* Rx Delay Timer - RW */
+#define IGC_RADV	0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
+#define IGC_EMIADD	0x10     /* Extended Memory Indirect Address */
+#define IGC_EMIDATA	0x11     /* Extended Memory Indirect Data */
+/* Shadow Ram Write Register - RW */
+#define IGC_SRWR		0x12018
+#define IGC_EEC_REG		0x12010
+
+#define IGC_I210_FLMNGCTL	0x12038
+#define IGC_I210_FLMNGDATA	0x1203C
+#define IGC_I210_FLMNGCNT	0x12040
+
+#define IGC_I210_FLSWCTL	0x12048
+#define IGC_I210_FLSWDATA	0x1204C
+#define IGC_I210_FLSWCNT	0x12050
+
+#define IGC_I210_FLA		0x1201C
+
+#define IGC_SHADOWINF		0x12068
+#define IGC_FLFWUPDATE	0x12108
+
+#define IGC_INVM_DATA_REG(_n)	(0x12120 + 4 * (_n))
+#define IGC_INVM_SIZE		64 /* Number of INVM Data Registers */
+
+/* QAV Tx mode control register */
+#define IGC_I210_TQAVCTRL	0x3570
+
+/* QAV Tx mode control register bitfields masks */
+/* QAV enable */
+#define IGC_TQAVCTRL_MODE			(1 << 0)
+/* Fetching arbitration type */
+#define IGC_TQAVCTRL_FETCH_ARB		(1 << 4)
+/* Fetching timer enable */
+#define IGC_TQAVCTRL_FETCH_TIMER_ENABLE	(1 << 5)
+/* Launch arbitration type */
+#define IGC_TQAVCTRL_LAUNCH_ARB		(1 << 8)
+/* Launch timer enable */
+#define IGC_TQAVCTRL_LAUNCH_TIMER_ENABLE	(1 << 9)
+/* SP waits for SR enable */
+#define IGC_TQAVCTRL_SP_WAIT_SR		(1 << 10)
+/* Fetching timer correction */
+#define IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET	16
+#define IGC_TQAVCTRL_FETCH_TIMER_DELTA	\
+			(0xFFFF << IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)
+
+/* High credit registers where _n can be 0 or 1. */
+#define IGC_I210_TQAVHC(_n)			(0x300C + 0x40 * (_n))
+
+/* Queues fetch arbitration priority control register */
+#define IGC_I210_TQAVARBCTRL			0x3574
+/* Queues priority masks where _n and _p can be 0-3. */
+#define IGC_TQAVARBCTRL_QUEUE_PRI(_n, _p)	((_p) << (2 * (_n)))
+/* QAV Tx mode control registers where _n can be 0 or 1. */
+#define IGC_I210_TQAVCC(_n)			(0x3004 + 0x40 * (_n))
+
+/* QAV Tx mode control register bitfields masks */
+#define IGC_TQAVCC_IDLE_SLOPE		0xFFFF /* Idle slope */
+#define IGC_TQAVCC_KEEP_CREDITS	(1 << 30) /* Keep credits opt enable */
+#define IGC_TQAVCC_QUEUE_MODE		(1 << 31) /* SP vs. SR Tx mode */
+
+/* Good transmitted packets counter registers */
+#define IGC_PQGPTC(_n)		(0x010014 + (0x100 * (_n)))
+
+/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
+#define IGC_I210_TXPBS_SIZE(_n, _s)	((_s) << (6 * (_n)))
+
+#define IGC_MMDAC			13 /* MMD Access Control */
+#define IGC_MMDAAD			14 /* MMD Access Address/Data */
+
+/* Convenience macros
+ *
+ * Note: "_n" is the queue number of the register
+ *
+ * Example usage:
+ * IGC_RDBAL_REG(current_rx_queue)
+ */
+#define IGC_QUEUE_REG(n, low, high) (	\
+	__extension__ ({			\
+		typeof(n) _n = (n);		\
+		_n < 4 ? ((low) + _n * 0x100) : ((high) + _n * 0x40);	\
+	}))
+
+#define IGC_RDBAL(_n)		IGC_QUEUE_REG(_n, 0x02800, 0x0C000)
+#define IGC_RDBAH(_n)		IGC_QUEUE_REG(_n, 0x02804, 0x0C004)
+#define IGC_RDLEN(_n)		IGC_QUEUE_REG(_n, 0x02808, 0x0C008)
+#define IGC_SRRCTL(_n)		IGC_QUEUE_REG(_n, 0x0280C, 0x0C00C)
+#define IGC_RDH(_n)		IGC_QUEUE_REG(_n, 0x02810, 0x0C010)
+#define IGC_RXCTL(_n)		IGC_QUEUE_REG(_n, 0x02814, 0x0C014)
+#define IGC_DCA_RXCTRL(_n)	IGC_RXCTL(_n)
+#define IGC_RDT(_n)		IGC_QUEUE_REG(_n, 0x02818, 0x0C018)
+#define IGC_RXDCTL(_n)		IGC_QUEUE_REG(_n, 0x02828, 0x0C028)
+#define IGC_RQDPC(_n)		IGC_QUEUE_REG(_n, 0x02830, 0x0C030)
+#define IGC_TDBAL(_n)		IGC_QUEUE_REG(_n, 0x03800, 0x0E000)
+#define IGC_TDBAH(_n)		IGC_QUEUE_REG(_n, 0x03804, 0x0E004)
+#define IGC_TDLEN(_n)		IGC_QUEUE_REG(_n, 0x03808, 0x0E008)
+#define IGC_TDH(_n)		IGC_QUEUE_REG(_n, 0x03810, 0x0E010)
+#define IGC_TXCTL(_n)		IGC_QUEUE_REG(_n, 0x03814, 0x0E014)
+#define IGC_DCA_TXCTRL(_n)	IGC_TXCTL(_n)
+#define IGC_TDT(_n)		IGC_QUEUE_REG(_n, 0x03818, 0x0E018)
+#define IGC_TXDCTL(_n)		IGC_QUEUE_REG(_n, 0x03828, 0x0E028)
+#define IGC_TDWBAL(_n)		IGC_QUEUE_REG(_n, 0x03838, 0x0E038)
+#define IGC_TDWBAH(_n)		IGC_QUEUE_REG(_n, 0x0383C, 0x0E03C)
+#define IGC_TARC(_n)		(0x03840 + (_n) * 0x100)
+#define IGC_RSRPD		0x02C00  /* Rx Small Packet Detect - RW */
+#define IGC_RAID		0x02C08  /* Receive Ack Interrupt Delay - RW */
+#define IGC_TXDMAC		0x03000  /* Tx DMA Control - RW */
+#define IGC_KABGTXD		0x03004  /* AFE Band Gap Transmit Ref Data */
+#define IGC_PSRTYPE(_i)	(0x05480 + ((_i) * 4))
+
+#define IGC_RAL(n)		(	\
+	__extension__ ({		\
+		typeof(n) _n = (n);	\
+		_n < 16 ? (0x05400 + _n * 8) : (0x054E0 + (_n - 16) * 8); \
+	}))
+
+#define IGC_RAH(_n)		(IGC_RAL(_n) + 4)
+
+#define IGC_VLAPQF		0x055B0  /* VLAN Priority Queue Filter VLAPQF */
+
+#define IGC_SHRAL(_i)		(0x05438 + ((_i) * 8))
+#define IGC_SHRAH(_i)		(0x0543C + ((_i) * 8))
+#define IGC_IP4AT_REG(_i)	(0x05840 + ((_i) * 8))
+#define IGC_IP6AT_REG(_i)	(0x05880 + ((_i) * 4))
+#define IGC_WUPM_REG(_i)	(0x05A00 + ((_i) * 4))
+#define IGC_FFMT_REG(_i)	(0x09000 + ((_i) * 8))
+#define IGC_FFVT_REG(_i)	(0x09800 + ((_i) * 8))
+#define IGC_FFLT_REG(_i)	(0x05F00 + ((_i) * 8))
+#define IGC_PBSLAC		0x03100  /* Pkt Buffer Slave Access Control */
+#define IGC_PBSLAD(_n)	(0x03110 + (0x4 * (_n)))  /* Pkt Buffer DWORD */
+#define IGC_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
+/* Same as TXPBS, renamed for newer Si - RW */
+#define IGC_ITPBS		0x03404
+#define IGC_TDFH		0x03410  /* Tx Data FIFO Head - RW */
+#define IGC_TDFT		0x03418  /* Tx Data FIFO Tail - RW */
+#define IGC_TDFHS		0x03420  /* Tx Data FIFO Head Saved - RW */
+#define IGC_TDFTS		0x03428  /* Tx Data FIFO Tail Saved - RW */
+#define IGC_TDFPC		0x03430  /* Tx Data FIFO Packet Count - RW */
+#define IGC_TDPUMB		0x0357C  /* DMA Tx Desc uC Mail Box - RW */
+#define IGC_TDPUAD		0x03580  /* DMA Tx Desc uC Addr Command - RW */
+#define IGC_TDPUWD		0x03584  /* DMA Tx Desc uC Data Write - RW */
+#define IGC_TDPURD		0x03588  /* DMA Tx Desc uC Data  Read  - RW */
+#define IGC_TDPUCTL		0x0358C  /* DMA Tx Desc uC Control - RW */
+#define IGC_DTXCTL		0x03590  /* DMA Tx Control - RW */
+#define IGC_DTXTCPFLGL	0x0359C /* DMA Tx Control flag low - RW */
+#define IGC_DTXTCPFLGH	0x035A0 /* DMA Tx Control flag high - RW */
+/* DMA Tx Max Total Allow Size Reqs - RW */
+#define IGC_DTXMXSZRQ		0x03540
+#define IGC_TIDV	0x03820  /* Tx Interrupt Delay Value - RW */
+#define IGC_TADV	0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
+#define IGC_TSPMT	0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+/* Statistics Register Descriptions */
+#define IGC_CRCERRS	0x04000  /* CRC Error Count - R/clr */
+#define IGC_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
+#define IGC_SYMERRS	0x04008  /* Symbol Error Count - R/clr */
+#define IGC_RXERRC	0x0400C  /* Receive Error Count - R/clr */
+#define IGC_MPC	0x04010  /* Missed Packet Count - R/clr */
+#define IGC_SCC	0x04014  /* Single Collision Count - R/clr */
+#define IGC_ECOL	0x04018  /* Excessive Collision Count - R/clr */
+#define IGC_MCC	0x0401C  /* Multiple Collision Count - R/clr */
+#define IGC_LATECOL	0x04020  /* Late Collision Count - R/clr */
+#define IGC_COLC	0x04028  /* Collision Count - R/clr */
+#define IGC_DC	0x04030  /* Defer Count - R/clr */
+#define IGC_TNCRS	0x04034  /* Tx-No CRS - R/clr */
+#define IGC_SEC	0x04038  /* Sequence Error Count - R/clr */
+#define IGC_CEXTERR	0x0403C  /* Carrier Extension Error Count - R/clr */
+#define IGC_RLEC	0x04040  /* Receive Length Error Count - R/clr */
+#define IGC_XONRXC	0x04048  /* XON Rx Count - R/clr */
+#define IGC_XONTXC	0x0404C  /* XON Tx Count - R/clr */
+#define IGC_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
+#define IGC_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
+#define IGC_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
+#define IGC_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
+#define IGC_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
+#define IGC_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
+#define IGC_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
+#define IGC_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
+#define IGC_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
+#define IGC_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
+#define IGC_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
+#define IGC_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
+#define IGC_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
+#define IGC_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
+#define IGC_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
+#define IGC_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
+#define IGC_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
+#define IGC_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
+#define IGC_RUC	0x040A4  /* Rx Undersize Count - R/clr */
+#define IGC_RFC	0x040A8  /* Rx Fragment Count - R/clr */
+#define IGC_ROC	0x040AC  /* Rx Oversize Count - R/clr */
+#define IGC_RJC	0x040B0  /* Rx Jabber Count - R/clr */
+#define IGC_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
+#define IGC_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
+#define IGC_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
+#define IGC_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
+#define IGC_TORH	0x040C4  /* Total Octets Rx High - R/clr */
+#define IGC_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
+#define IGC_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
+#define IGC_TPR	0x040D0  /* Total Packets Rx - R/clr */
+#define IGC_TPT	0x040D4  /* Total Packets Tx - R/clr */
+#define IGC_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
+#define IGC_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
+#define IGC_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
+#define IGC_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
+#define IGC_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
+#define IGC_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
+#define IGC_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
+#define IGC_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
+#define IGC_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
+#define IGC_TSCTFC	0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
+#define IGC_IAC	0x04100  /* Interrupt Assertion Count */
+/* Interrupt Cause */
+#define IGC_ICRXPTC	0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
+#define IGC_ICRXATC	0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
+#define IGC_ICTXPTC	0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
+#define IGC_ICTXATC	0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
+#define IGC_ICTXQEC	0x04118  /* Interrupt Cause Tx Queue Empty Count */
+#define IGC_ICTXQMTC	0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
+#define IGC_ICRXDMTC	0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
+#define IGC_ICRXOC	0x04124  /* Interrupt Cause Receiver Overrun Count */
+#define IGC_CRC_OFFSET	0x05F50  /* CRC Offset register */
+
+#define IGC_VFGPRC	0x00F10
+#define IGC_VFGORC	0x00F18
+#define IGC_VFMPRC	0x00F3C
+#define IGC_VFGPTC	0x00F14
+#define IGC_VFGOTC	0x00F34
+#define IGC_VFGOTLBC	0x00F50
+#define IGC_VFGPTLBC	0x00F44
+#define IGC_VFGORLBC	0x00F48
+#define IGC_VFGPRLBC	0x00F40
+/* Virtualization statistical counters */
+#define IGC_PFVFGPRC(_n)	(0x010010 + (0x100 * (_n)))
+#define IGC_PFVFGPTC(_n)	(0x010014 + (0x100 * (_n)))
+#define IGC_PFVFGORC(_n)	(0x010018 + (0x100 * (_n)))
+#define IGC_PFVFGOTC(_n)	(0x010034 + (0x100 * (_n)))
+#define IGC_PFVFMPRC(_n)	(0x010038 + (0x100 * (_n)))
+#define IGC_PFVFGPRLBC(_n)	(0x010040 + (0x100 * (_n)))
+#define IGC_PFVFGPTLBC(_n)	(0x010044 + (0x100 * (_n)))
+#define IGC_PFVFGORLBC(_n)	(0x010048 + (0x100 * (_n)))
+#define IGC_PFVFGOTLBC(_n)	(0x010050 + (0x100 * (_n)))
+
+/* LinkSec */
+#define IGC_LSECTXUT		0x04300  /* Tx Untagged Pkt Cnt */
+#define IGC_LSECTXPKTE	0x04304  /* Encrypted Tx Pkts Cnt */
+#define IGC_LSECTXPKTP	0x04308  /* Protected Tx Pkt Cnt */
+#define IGC_LSECTXOCTE	0x0430C  /* Encrypted Tx Octets Cnt */
+#define IGC_LSECTXOCTP	0x04310  /* Protected Tx Octets Cnt */
+#define IGC_LSECRXUT		0x04314  /* Untagged non-Strict Rx Pkt Cnt */
+#define IGC_LSECRXOCTD	0x0431C  /* Rx Octets Decrypted Count */
+#define IGC_LSECRXOCTV	0x04320  /* Rx Octets Validated */
+#define IGC_LSECRXBAD		0x04324  /* Rx Bad Tag */
+#define IGC_LSECRXNOSCI	0x04328  /* Rx Packet No SCI Count */
+#define IGC_LSECRXUNSCI	0x0432C  /* Rx Packet Unknown SCI Count */
+#define IGC_LSECRXUNCH	0x04330  /* Rx Unchecked Packets Count */
+#define IGC_LSECRXDELAY	0x04340  /* Rx Delayed Packet Count */
+#define IGC_LSECRXLATE	0x04350  /* Rx Late Packets Count */
+#define IGC_LSECRXOK(_n)	(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
+#define IGC_LSECRXINV(_n)	(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
+#define IGC_LSECRXNV(_n)	(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
+#define IGC_LSECRXUNSA	0x043C0  /* Rx Unused SA Count */
+#define IGC_LSECRXNUSA	0x043D0  /* Rx Not Using SA Count */
+#define IGC_LSECTXCAP		0x0B000  /* Tx Capabilities Register - RO */
+#define IGC_LSECRXCAP		0x0B300  /* Rx Capabilities Register - RO */
+#define IGC_LSECTXCTRL	0x0B004  /* Tx Control - RW */
+#define IGC_LSECRXCTRL	0x0B304  /* Rx Control - RW */
+#define IGC_LSECTXSCL		0x0B008  /* Tx SCI Low - RW */
+#define IGC_LSECTXSCH		0x0B00C  /* Tx SCI High - RW */
+#define IGC_LSECTXSA		0x0B010  /* Tx SA0 - RW */
+#define IGC_LSECTXPN0		0x0B018  /* Tx SA PN 0 - RW */
+#define IGC_LSECTXPN1		0x0B01C  /* Tx SA PN 1 - RW */
+#define IGC_LSECRXSCL		0x0B3D0  /* Rx SCI Low - RW */
+#define IGC_LSECRXSCH		0x0B3E0  /* Rx SCI High - RW */
+/* LinkSec Tx 128-bit Key 0 - WO */
+#define IGC_LSECTXKEY0(_n)	(0x0B020 + (0x04 * (_n)))
+/* LinkSec Tx 128-bit Key 1 - WO */
+#define IGC_LSECTXKEY1(_n)	(0x0B030 + (0x04 * (_n)))
+#define IGC_LSECRXSA(_n)	(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
+#define IGC_LSECRXPN(_n)	(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
+/* LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
+ * key - RW.
+ */
+#define IGC_LSECRXKEY(_n, _m)	(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
+
+#define IGC_SSVPC		0x041A0 /* Switch Security Violation Pkt Cnt */
+#define IGC_IPSCTRL		0xB430  /* IpSec Control Register */
+#define IGC_IPSRXCMD		0x0B408 /* IPSec Rx Command Register - RW */
+#define IGC_IPSRXIDX		0x0B400 /* IPSec Rx Index - RW */
+/* IPSec Rx IPv4/v6 Address - RW */
+#define IGC_IPSRXIPADDR(_n)	(0x0B420 + (0x04 * (_n)))
+/* IPSec Rx 128-bit Key - RW */
+#define IGC_IPSRXKEY(_n)	(0x0B410 + (0x04 * (_n)))
+#define IGC_IPSRXSALT		0x0B404  /* IPSec Rx Salt - RW */
+#define IGC_IPSRXSPI		0x0B40C  /* IPSec Rx SPI - RW */
+/* IPSec Tx 128-bit Key - RW */
+#define IGC_IPSTXKEY(_n)	(0x0B460 + (0x04 * (_n)))
+#define IGC_IPSTXSALT		0x0B454  /* IPSec Tx Salt - RW */
+#define IGC_IPSTXIDX		0x0B450  /* IPSec Tx SA IDX - RW */
+#define IGC_PCS_CFG0	0x04200  /* PCS Configuration 0 - RW */
+#define IGC_PCS_LCTL	0x04208  /* PCS Link Control - RW */
+#define IGC_PCS_LSTAT	0x0420C  /* PCS Link Status - RO */
+#define IGC_CBTMPC	0x0402C  /* Circuit Breaker Tx Packet Count */
+#define IGC_HTDPMC	0x0403C  /* Host Transmit Discarded Packets */
+#define IGC_CBRDPC	0x04044  /* Circuit Breaker Rx Dropped Count */
+#define IGC_CBRMPC	0x040FC  /* Circuit Breaker Rx Packet Count */
+#define IGC_RPTHC	0x04104  /* Rx Packets To Host */
+#define IGC_HGPTC	0x04118  /* Host Good Packets Tx Count */
+#define IGC_HTCBDPC	0x04124  /* Host Tx Circuit Breaker Dropped Count */
+#define IGC_HGORCL	0x04128  /* Host Good Octets Received Count Low */
+#define IGC_HGORCH	0x0412C  /* Host Good Octets Received Count High */
+#define IGC_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
+#define IGC_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
+#define IGC_LENERRS	0x04138  /* Length Errors Count */
+#define IGC_SCVPC	0x04228  /* SerDes/SGMII Code Violation Pkt Count */
+#define IGC_HRMPC	0x0A018  /* Header Redirection Missed Packet Count */
+#define IGC_PCS_ANADV	0x04218  /* AN advertisement - RW */
+#define IGC_PCS_LPAB	0x0421C  /* Link Partner Ability - RW */
+#define IGC_PCS_NPTX	0x04220  /* AN Next Page Transmit - RW */
+#define IGC_PCS_LPABNP	0x04224 /* Link Partner Ability Next Pg - RW */
+#define IGC_RXCSUM	0x05000  /* Rx Checksum Control - RW */
+#define IGC_RLPML	0x05004  /* Rx Long Packet Max Length */
+#define IGC_RFCTL	0x05008  /* Receive Filter Control*/
+#define IGC_MTA	0x05200  /* Multicast Table Array - RW Array */
+#define IGC_RA	0x05400  /* Receive Address - RW Array */
+#define IGC_RA2	0x054E0  /* 2nd half of Rx address array - RW Array */
+#define IGC_VFTA	0x05600  /* VLAN Filter Table Array - RW Array */
+#define IGC_VT_CTL	0x0581C  /* VMDq Control - RW */
+#define IGC_CIAA	0x05B88  /* Config Indirect Access Address - RW */
+#define IGC_CIAD	0x05B8C  /* Config Indirect Access Data - RW */
+#define IGC_VFQA0	0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
+#define IGC_VFQA1	0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
+#define IGC_WUC	0x05800  /* Wakeup Control - RW */
+#define IGC_WUFC	0x05808  /* Wakeup Filter Control - RW */
+#define IGC_WUS	0x05810  /* Wakeup Status - RO */
+/* Management registers */
+#define IGC_MANC	0x05820  /* Management Control - RW */
+#define IGC_IPAV	0x05838  /* IP Address Valid - RW */
+#define IGC_IP4AT	0x05840  /* IPv4 Address Table - RW Array */
+#define IGC_IP6AT	0x05880  /* IPv6 Address Table - RW Array */
+#define IGC_WUPL	0x05900  /* Wakeup Packet Length - RW */
+#define IGC_WUPM	0x05A00  /* Wakeup Packet Memory - RO A */
+#define IGC_WUPM_EXT	0x0B800  /* Wakeup Packet Memory Extended - RO Array */
+#define IGC_WUFC_EXT	0x0580C  /* Wakeup Filter Control Extended - RW */
+#define IGC_WUS_EXT	0x05814  /* Wakeup Status Extended - RW1C */
+#define IGC_FHFTSL	0x05804  /* Flex Filter Indirect Table Select - RW */
+#define IGC_PROXYFCEX	0x05590  /* Proxy Filter Control Extended - RW1C */
+#define IGC_PROXYEXS	0x05594  /* Proxy Extended Status - RO */
+#define IGC_WFUTPF	0x05500  /* Wake Flex UDP TCP Port Filter - RW Array */
+#define IGC_RFUTPF	0x05580  /* Range Flex UDP TCP Port Filter - RW */
+#define IGC_RWPFC	0x05584  /* Range Wake Port Filter Control - RW */
+#define IGC_WFUTPS	0x05588  /* Wake Filter UDP TCP Status - RW1C */
+#define IGC_WCS	0x0558C  /* Wake Control Status - RW1C */
+/* MSI-X Table Register Descriptions */
+#define IGC_PBACL	0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
+#define IGC_FFLT	0x05F00  /* Flexible Filter Length Table - RW Array */
+#define IGC_HOST_IF	0x08800  /* Host Interface */
+#define IGC_HIBBA	0x8F40   /* Host Interface Buffer Base Address */
+/* Flexible Host Filter Table */
+#define IGC_FHFT(_n)	(0x09000 + ((_n) * 0x100))
+/* Ext Flexible Host Filter Table */
+#define IGC_FHFT_EXT(_n)	(0x09A00 + ((_n) * 0x100))
+
+
+#define IGC_KMRNCTRLSTA	0x00034 /* MAC-PHY interface - RW */
+#define IGC_MANC2H		0x05860 /* Management Control To Host - RW */
+/* Management Decision Filters */
+#define IGC_MDEF(_n)		(0x05890 + (4 * (_n)))
+/* Semaphore registers */
+#define IGC_SW_FW_SYNC	0x05B5C /* SW-FW Synchronization - RW */
+#define IGC_CCMCTL	0x05B48 /* CCM Control Register */
+#define IGC_GIOCTL	0x05B44 /* GIO Analog Control Register */
+#define IGC_SCCTL	0x05B4C /* PCIc PLL Configuration Register */
+/* PCIe Register Description */
+#define IGC_GCR	0x05B00 /* PCI-Ex Control */
+#define IGC_GCR2	0x05B64 /* PCI-Ex Control #2 */
+#define IGC_GSCL_1	0x05B10 /* PCI-Ex Statistic Control #1 */
+#define IGC_GSCL_2	0x05B14 /* PCI-Ex Statistic Control #2 */
+#define IGC_GSCL_3	0x05B18 /* PCI-Ex Statistic Control #3 */
+#define IGC_GSCL_4	0x05B1C /* PCI-Ex Statistic Control #4 */
+/* Function Active and Power State to MNG */
+#define IGC_FACTPS	0x05B30
+#define IGC_SWSM	0x05B50 /* SW Semaphore */
+#define IGC_FWSM	0x05B54 /* FW Semaphore */
+/* Driver-only SW semaphore (not used by BOOT agents) */
+#define IGC_SWSM2	0x05B58
+#define IGC_DCA_ID	0x05B70 /* DCA Requester ID Information - RO */
+#define IGC_DCA_CTRL	0x05B74 /* DCA Control - RW */
+#define IGC_UFUSE	0x05B78 /* UFUSE - RO */
+#define IGC_FFLT_DBG	0x05F04 /* Debug Register */
+#define IGC_HICR	0x08F00 /* Host Interface Control */
+#define IGC_FWSTS	0x08F0C /* FW Status */
+
+/* RSS registers */
+#define IGC_CPUVEC	0x02C10 /* CPU Vector Register - RW */
+#define IGC_MRQC	0x05818 /* Multiple Receive Control - RW */
+#define IGC_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
+#define IGC_IMIREXT(_i)	(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
+#define IGC_IMIRVP		0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
+#define IGC_MSIXBM(_i)	(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
+/* Redirection Table - RW Array */
+#define IGC_RETA(_i)	(0x05C00 + ((_i) * 4))
+/* RSS Random Key - RW Array */
+#define IGC_RSSRK(_i)	(0x05C80 + ((_i) * 4))
+#define IGC_RSSIM	0x05864 /* RSS Interrupt Mask */
+#define IGC_RSSIR	0x05868 /* RSS Interrupt Request */
+#define IGC_UTA	0x0A000 /* Unicast Table Array - RW */
+/* VT Registers */
+#define IGC_SWPBS	0x03004 /* Switch Packet Buffer Size - RW */
+#define IGC_MBVFICR	0x00C80 /* Mailbox VF Cause - RWC */
+#define IGC_MBVFIMR	0x00C84 /* Mailbox VF int Mask - RW */
+#define IGC_VFLRE	0x00C88 /* VF Register Events - RWC */
+#define IGC_VFRE	0x00C8C /* VF Receive Enables */
+#define IGC_VFTE	0x00C90 /* VF Transmit Enables */
+#define IGC_QDE	0x02408 /* Queue Drop Enable - RW */
+#define IGC_DTXSWC	0x03500 /* DMA Tx Switch Control - RW */
+#define IGC_WVBR	0x03554 /* VM Wrong Behavior - RWS */
+#define IGC_RPLOLR	0x05AF0 /* Replication Offload - RW */
+#define IGC_IOVTCL	0x05BBC /* IOV Control Register */
+#define IGC_VMRCTL	0X05D80 /* Virtual Mirror Rule Control */
+#define IGC_VMRVLAN	0x05D90 /* Virtual Mirror Rule VLAN */
+#define IGC_VMRVM	0x05DA0 /* Virtual Mirror Rule VM */
+#define IGC_MDFB	0x03558 /* Malicious Driver free block */
+#define IGC_LVMMC	0x03548 /* Last VM Misbehavior cause */
+#define IGC_TXSWC	0x05ACC /* Tx Switch Control */
+#define IGC_SCCRL	0x05DB0 /* Storm Control Control */
+#define IGC_BSCTRH	0x05DB8 /* Broadcast Storm Control Threshold */
+#define IGC_MSCTRH	0x05DBC /* Multicast Storm Control Threshold */
+/* These act per VF so an array friendly macro is used */
+#define IGC_V2PMAILBOX(_n)	(0x00C40 + (4 * (_n)))
+#define IGC_P2VMAILBOX(_n)	(0x00C00 + (4 * (_n)))
+#define IGC_VMBMEM(_n)	(0x00800 + (64 * (_n)))
+#define IGC_VFVMBMEM(_n)	(0x00800 + (_n))
+#define IGC_VMOLR(_n)		(0x05AD0 + (4 * (_n)))
+/* VLAN Virtual Machine Filter - RW */
+#define IGC_VLVF(_n)		(0x05D00 + (4 * (_n)))
+#define IGC_VMVIR(_n)		(0x03700 + (4 * (_n)))
+#define IGC_DVMOLR(_n)	(0x0C038 + (0x40 * (_n))) /* DMA VM offload */
+#define IGC_VTCTRL(_n)	(0x10000 + (0x100 * (_n))) /* VT Control */
+#define IGC_TSYNCRXCTL	0x0B620 /* Rx Time Sync Control register - RW */
+#define IGC_TSYNCTXCTL	0x0B614 /* Tx Time Sync Control register - RW */
+#define IGC_TSYNCRXCFG	0x05F50 /* Time Sync Rx Configuration - RW */
+#define IGC_RXSTMPL	0x0B624 /* Rx timestamp Low - RO */
+#define IGC_RXSTMPH	0x0B628 /* Rx timestamp High - RO */
+#define IGC_RXSATRL	0x0B62C /* Rx timestamp attribute low - RO */
+#define IGC_RXSATRH	0x0B630 /* Rx timestamp attribute high - RO */
+#define IGC_TXSTMPL	0x0B618 /* Tx timestamp value Low - RO */
+#define IGC_TXSTMPH	0x0B61C /* Tx timestamp value High - RO */
+#define IGC_SYSTIML	0x0B600 /* System time register Low - RO */
+#define IGC_SYSTIMH	0x0B604 /* System time register High - RO */
+#define IGC_TIMINCA	0x0B608 /* Increment attributes register - RW */
+#define IGC_TIMADJL	0x0B60C /* Time sync time adjustment offset Low - RW */
+#define IGC_TIMADJH	0x0B610 /* Time sync time adjustment offset High - RW */
+#define IGC_TSAUXC	0x0B640 /* Timesync Auxiliary Control register */
+#define	IGC_SYSSTMPL	0x0B648 /* HH Timesync system stamp low register */
+#define	IGC_SYSSTMPH	0x0B64C /* HH Timesync system stamp hi register */
+#define	IGC_PLTSTMPL	0x0B640 /* HH Timesync platform stamp low register */
+#define	IGC_PLTSTMPH	0x0B644 /* HH Timesync platform stamp hi register */
+#define IGC_SYSTIMR	0x0B6F8 /* System time register Residue */
+#define IGC_TSICR	0x0B66C /* Interrupt Cause Register */
+#define IGC_TSIM	0x0B674 /* Interrupt Mask Register */
+#define IGC_RXMTRL	0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
+#define IGC_RXUDP	0x0B638 /* Time Sync Rx UDP Port - RW */
+
+/* Filtering Registers */
+#define IGC_SAQF(_n)	(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
+#define IGC_DAQF(_n)	(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
+#define IGC_SPQF(_n)	(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
+#define IGC_FTQF(_n)	(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
+#define IGC_TTQF(_n)	(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
+#define IGC_SYNQF(_n)	(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
+#define IGC_ETQF(_n)	(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
+
+#define IGC_RTTDCS	0x3600 /* Reedtown Tx Desc plane control and status */
+#define IGC_RTTPCS	0x3474 /* Reedtown Tx Packet Plane control and status */
+#define IGC_RTRPCS	0x2474 /* Rx packet plane control and status */
+#define IGC_RTRUP2TC	0x05AC4 /* Rx User Priority to Traffic Class */
+#define IGC_RTTUP2TC	0x0418 /* Transmit User Priority to Traffic Class */
+/* Tx Desc plane TC Rate-scheduler config */
+#define IGC_RTTDTCRC(_n)	(0x3610 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Config */
+#define IGC_RTTPTCRC(_n)	(0x3480 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Config */
+#define IGC_RTRPTCRC(_n)	(0x2480 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler Status */
+#define IGC_RTTDTCRS(_n)	(0x3630 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler MMW */
+#define IGC_RTTDTCRM(_n)	(0x3650 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Status */
+#define IGC_RTTPTCRS(_n)	(0x34A0 + ((_n) * 4))
+/* Tx Packet plane TC Rate-scheduler MMW */
+#define IGC_RTTPTCRM(_n)	(0x34C0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Status */
+#define IGC_RTRPTCRS(_n)	(0x24A0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler MMW */
+#define IGC_RTRPTCRM(_n)	(0x24C0 + ((_n) * 4))
+/* Tx Desc plane VM Rate-Scheduler MMW*/
+#define IGC_RTTDVMRM(_n)	(0x3670 + ((_n) * 4))
+/* Tx BCN Rate-Scheduler MMW */
+#define IGC_RTTBCNRM(_n)	(0x3690 + ((_n) * 4))
+#define IGC_RTTDQSEL	0x3604  /* Tx Desc Plane Queue Select */
+#define IGC_RTTDVMRC	0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
+#define IGC_RTTDVMRS	0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
+#define IGC_RTTBCNRC	0x36B0  /* Tx BCN Rate-Scheduler Config */
+#define IGC_RTTBCNRS	0x36B4  /* Tx BCN Rate-Scheduler Status */
+#define IGC_RTTBCNCR	0xB200  /* Tx BCN Control Register */
+#define IGC_RTTBCNTG	0x35A4  /* Tx BCN Tagging */
+#define IGC_RTTBCNCP	0xB208  /* Tx BCN Congestion point */
+#define IGC_RTRBCNCR	0xB20C  /* Rx BCN Control Register */
+#define IGC_RTTBCNRD	0x36B8  /* Tx BCN Rate Drift */
+#define IGC_PFCTOP	0x1080  /* Priority Flow Control Type and Opcode */
+#define IGC_RTTBCNIDX	0xB204  /* Tx BCN Congestion Point */
+#define IGC_RTTBCNACH	0x0B214 /* Tx BCN Control High */
+#define IGC_RTTBCNACL	0x0B210 /* Tx BCN Control Low */
+
+/* DMA Coalescing registers */
+#define IGC_DMACR	0x02508 /* Control Register */
+#define IGC_DMCTXTH	0x03550 /* Transmit Threshold */
+#define IGC_DMCTLX	0x02514 /* Time to Lx Request */
+#define IGC_DMCRTRH	0x05DD0 /* Receive Packet Rate Threshold */
+#define IGC_DMCCNT	0x05DD4 /* Current Rx Count */
+#define IGC_FCRTC	0x02170 /* Flow Control Rx high watermark */
+#define IGC_PCIEMISC	0x05BB8 /* PCIE misc config register */
+
+/* PCIe Parity Status Register */
+#define IGC_PCIEERRSTS	0x05BA8
+
+#define IGC_PROXYS	0x5F64 /* Proxying Status */
+#define IGC_PROXYFC	0x5F60 /* Proxying Filter Control */
+/* Thermal sensor configuration and status registers */
+#define IGC_THMJT	0x08100 /* Junction Temperature */
+#define IGC_THLOWTC	0x08104 /* Low Threshold Control */
+#define IGC_THMIDTC	0x08108 /* Mid Threshold Control */
+#define IGC_THHIGHTC	0x0810C /* High Threshold Control */
+#define IGC_THSTAT	0x08110 /* Thermal Sensor Status */
+
+/* Energy Efficient Ethernet "EEE" registers */
+#define IGC_IPCNFG	0x0E38 /* Internal PHY Configuration */
+#define IGC_LTRC	0x01A0 /* Latency Tolerance Reporting Control */
+#define IGC_EEER	0x0E30 /* Energy Efficient Ethernet "EEE"*/
+#define IGC_EEE_SU	0x0E34 /* EEE Setup */
+#define IGC_EEE_SU_2P5	0x0E3C /* EEE 2.5G Setup */
+#define IGC_TLPIC	0x4148 /* EEE Tx LPI Count - TLPIC */
+#define IGC_RLPIC	0x414C /* EEE Rx LPI Count - RLPIC */
+
+/* OS2BMC Registers */
+#define IGC_B2OSPC	0x08FE0 /* BMC2OS packets sent by BMC */
+#define IGC_B2OGPRC	0x04158 /* BMC2OS packets received by host */
+#define IGC_O2BGPTC	0x08FE4 /* OS2BMC packets received by BMC */
+#define IGC_O2BSPC	0x0415C /* OS2BMC packets transmitted by host */
+
+#define IGC_LTRMINV	0x5BB0 /* LTR Minimum Value */
+#define IGC_LTRMAXV	0x5BB4 /* LTR Maximum Value */
+
+
+/* IEEE 1588 TIMESYNCH */
+#define IGC_TRGTTIML0	0x0B644 /* Target Time Register 0 Low  - RW */
+#define IGC_TRGTTIMH0	0x0B648 /* Target Time Register 0 High - RW */
+#define IGC_TRGTTIML1	0x0B64C /* Target Time Register 1 Low  - RW */
+#define IGC_TRGTTIMH1	0x0B650 /* Target Time Register 1 High - RW */
+#define IGC_FREQOUT0	0x0B654 /* Frequency Out 0 Control Register - RW */
+#define IGC_FREQOUT1	0x0B658 /* Frequency Out 1 Control Register - RW */
+#define IGC_TSSDP	0x0003C  /* Time Sync SDP Configuration Register - RW */
+
+#define IGC_LTRC_EEEMS_EN			(1 << 5)
+#define IGC_TW_SYSTEM_100_MASK		0xff00
+#define IGC_TW_SYSTEM_100_SHIFT	8
+#define IGC_TW_SYSTEM_1000_MASK	0xff
+#define IGC_LTRMINV_SCALE_1024		0x02
+#define IGC_LTRMINV_SCALE_32768	0x03
+#define IGC_LTRMAXV_SCALE_1024		0x02
+#define IGC_LTRMAXV_SCALE_32768	0x03
+#define IGC_LTRMINV_LTRV_MASK		0x1ff
+#define IGC_LTRMINV_LSNP_REQ		0x80
+#define IGC_LTRMINV_SCALE_SHIFT	10
+#define IGC_LTRMAXV_LTRV_MASK		0x1ff
+#define IGC_LTRMAXV_LSNP_REQ		0x80
+#define IGC_LTRMAXV_SCALE_SHIFT	10
+
+#define IGC_MRQC_ENABLE_MASK		0x00000007
+#define IGC_MRQC_RSS_FIELD_IPV6_EX	0x00080000
+#define IGC_RCTL_DTYP_MASK		0x00000C00 /* Descriptor type mask */
+
+#endif
--- a/drivers/net/igc/base/meson.build
+++ b/drivers/net/igc/base/meson.build
@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019-2020 Intel Corporation
+
+sources = [
+	'igc_api.c',
+	'igc_base.c',
+	'igc_i225.c',
+	'igc_mac.c',
+	'igc_manage.c',
+	'igc_nvm.c',
+	'igc_osdep.c',
+	'igc_phy.c',
+]
+
+base_lib = static_library('igc_base', sources,
+	dependencies: static_rte_eal)
+
+base_objs = base_lib.extract_all_objects()
--- a/drivers/net/igc/igc_ethdev.c
+++ b/drivers/net/igc/igc_ethdev.c
@ -14,11 +14,8 @@
 #include "igc_ethdev.h"

 #define IGC_INTEL_VENDOR_ID		0x8086
-#define IGC_DEV_ID_I225_LM		0x15F2
-#define IGC_DEV_ID_I225_V		0x15F3
-#define IGC_DEV_ID_I225_K		0x3100
-#define IGC_DEV_ID_I225_I		0x15F8
-#define IGC_DEV_ID_I220_V		0x15F7
+
+#define IGC_FC_PAUSE_TIME		0x0680

 static const struct rte_pci_id pci_id_igc_map[] = {
 	{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) },
@ -86,6 +83,90 @@ eth_igc_stop(struct rte_eth_dev *dev)
 	RTE_SET_USED(dev);
 }

+/*
+ *  Get hardware rx-buffer size.
+ */
+static inline int
+igc_get_rx_buffer_size(struct igc_hw *hw)
+{
+	return (IGC_READ_REG(hw, IGC_RXPBS) & 0x3f) << 10;
+}
+
+/*
+ * igc_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
+ * For ASF and Pass Through versions of f/w this means
+ * that the driver is loaded.
+ */
+static void
+igc_hw_control_acquire(struct igc_hw *hw)
+{
+	uint32_t ctrl_ext;
+
+	/* Let firmware know the driver has taken over */
+	ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
+	IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
+}
+
+/*
+ * igc_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
+ * For ASF and Pass Through versions of f/w this means that the
+ * driver is no longer loaded.
+ */
+static void
+igc_hw_control_release(struct igc_hw *hw)
+{
+	uint32_t ctrl_ext;
+
+	/* Let firmware taken over control of h/w */
+	ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
+	IGC_WRITE_REG(hw, IGC_CTRL_EXT,
+			ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
+}
+
+static int
+igc_hardware_init(struct igc_hw *hw)
+{
+	uint32_t rx_buf_size;
+	int diag;
+
+	/* Let the firmware know the OS is in control */
+	igc_hw_control_acquire(hw);
+
+	/* Issue a global reset */
+	igc_reset_hw(hw);
+
+	/* disable all wake up */
+	IGC_WRITE_REG(hw, IGC_WUC, 0);
+
+	/*
+	 * Hardware flow control
+	 * - High water mark should allow for at least two standard size (1518)
+	 *   frames to be received after sending an XOFF.
+	 * - Low water mark works best when it is very near the high water mark.
+	 *   This allows the receiver to restart by sending XON when it has
+	 *   drained a bit. Here we use an arbitrary value of 1500 which will
+	 *   restart after one full frame is pulled from the buffer. There
+	 *   could be several smaller frames in the buffer and if so they will
+	 *   not trigger the XON until their total number reduces the buffer
+	 *   by 1500.
+	 */
+	rx_buf_size = igc_get_rx_buffer_size(hw);
+	hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
+	hw->fc.low_water = hw->fc.high_water - 1500;
+	hw->fc.pause_time = IGC_FC_PAUSE_TIME;
+	hw->fc.send_xon = 1;
+	hw->fc.requested_mode = igc_fc_full;
+
+	diag = igc_init_hw(hw);
+	if (diag < 0)
+		return diag;
+
+	igc_get_phy_info(hw);
+	igc_check_for_link(hw);
+
+	return 0;
+}
+
 static int
 eth_igc_start(struct rte_eth_dev *dev)
 {
@ -94,17 +175,91 @@ eth_igc_start(struct rte_eth_dev *dev)
 	return 0;
 }

+static int
+igc_reset_swfw_lock(struct igc_hw *hw)
+{
+	int ret_val;
+
+	/*
+	 * Do mac ops initialization manually here, since we will need
+	 * some function pointers set by this call.
+	 */
+	ret_val = igc_init_mac_params(hw);
+	if (ret_val)
+		return ret_val;
+
+	/*
+	 * SMBI lock should not fail in this early stage. If this is the case,
+	 * it is due to an improper exit of the application.
+	 * So force the release of the faulty lock.
+	 */
+	if (igc_get_hw_semaphore_generic(hw) < 0)
+		PMD_DRV_LOG(DEBUG, "SMBI lock released");
+
+	igc_put_hw_semaphore_generic(hw);
+
+	if (hw->mac.ops.acquire_swfw_sync != NULL) {
+		uint16_t mask;
+
+		/*
+		 * Phy lock should not fail in this early stage.
+		 * If this is the case, it is due to an improper exit of the
+		 * application. So force the release of the faulty lock.
+		 */
+		mask = IGC_SWFW_PHY0_SM;
+		if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
+			PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
+				    hw->bus.func);
+		}
+		hw->mac.ops.release_swfw_sync(hw, mask);
+
+		/*
+		 * This one is more tricky since it is common to all ports; but
+		 * swfw_sync retries last long enough (1s) to be almost sure
+		 * that if lock can not be taken it is due to an improper lock
+		 * of the semaphore.
+		 */
+		mask = IGC_SWFW_EEP_SM;
+		if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0)
+			PMD_DRV_LOG(DEBUG, "SWFW common locks released");
+
+		hw->mac.ops.release_swfw_sync(hw, mask);
+	}
+
+	return IGC_SUCCESS;
+}
+
 static void
 eth_igc_close(struct rte_eth_dev *dev)
 {
+	struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+
 	PMD_INIT_FUNC_TRACE();
-	 RTE_SET_USED(dev);
+
+	igc_phy_hw_reset(hw);
+	igc_hw_control_release(hw);
+
+	/* Reset any pending lock */
+	igc_reset_swfw_lock(hw);
+}
+
+static void
+igc_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
+{
+	struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+
+	hw->vendor_id = pci_dev->id.vendor_id;
+	hw->device_id = pci_dev->id.device_id;
+	hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
+	hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 }

 static int
 eth_igc_dev_init(struct rte_eth_dev *dev)
 {
 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+	struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+	int error = 0;

 	PMD_INIT_FUNC_TRACE();
 	dev->dev_ops = &eth_igc_ops;
@ -117,12 +272,90 @@ eth_igc_dev_init(struct rte_eth_dev *dev)
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 		return 0;

+	rte_eth_copy_pci_info(dev, pci_dev);
+
+	hw->back = pci_dev;
+	hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
+
+	igc_identify_hardware(dev, pci_dev);
+	if (igc_setup_init_funcs(hw, false) != IGC_SUCCESS) {
+		error = -EIO;
+		goto err_late;
+	}
+
+	igc_get_bus_info(hw);
+
+	/* Reset any pending lock */
+	if (igc_reset_swfw_lock(hw) != IGC_SUCCESS) {
+		error = -EIO;
+		goto err_late;
+	}
+
+	/* Finish initialization */
+	if (igc_setup_init_funcs(hw, true) != IGC_SUCCESS) {
+		error = -EIO;
+		goto err_late;
+	}
+
+	hw->mac.autoneg = 1;
+	hw->phy.autoneg_wait_to_complete = 0;
+	hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
+
+	/* Copper options */
+	if (hw->phy.media_type == igc_media_type_copper) {
+		hw->phy.mdix = 0; /* AUTO_ALL_MODES */
+		hw->phy.disable_polarity_correction = 0;
+		hw->phy.ms_type = igc_ms_hw_default;
+	}
+
+	/*
+	 * Start from a known state, this is important in reading the nvm
+	 * and mac from that.
+	 */
+	igc_reset_hw(hw);
+
+	/* Make sure we have a good EEPROM before we read from it */
+	if (igc_validate_nvm_checksum(hw) < 0) {
+		/*
+		 * Some PCI-E parts fail the first check due to
+		 * the link being in sleep state, call it again,
+		 * if it fails a second time its a real issue.
+		 */
+		if (igc_validate_nvm_checksum(hw) < 0) {
+			PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
+			error = -EIO;
+			goto err_late;
+		}
+	}
+
+	/* Read the permanent MAC address out of the EEPROM */
+	if (igc_read_mac_addr(hw) != 0) {
+		PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
+		error = -EIO;
+		goto err_late;
+	}
+
+	/* Allocate memory for storing MAC addresses */
 	dev->data->mac_addrs = rte_zmalloc("igc",
-		RTE_ETHER_ADDR_LEN, 0);
+		RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 	if (dev->data->mac_addrs == NULL) {
 		PMD_INIT_LOG(ERR, "Failed to allocate %d bytes for storing MAC",
-				RTE_ETHER_ADDR_LEN);
-		return -ENOMEM;
+				RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
+		error = -ENOMEM;
+		goto err_late;
+	}
+
+	/* Copy the permanent MAC address */
+	rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
+			&dev->data->mac_addrs[0]);
+
+	/* Now initialize the hardware */
+	if (igc_hardware_init(hw) != 0) {
+		PMD_INIT_LOG(ERR, "Hardware initialization failed");
+		rte_free(dev->data->mac_addrs);
+		dev->data->mac_addrs = NULL;
+		error = -ENODEV;
+		goto err_late;
 	}

 	/* Pass the information to the rte_eth_dev_close() that it should also
@ -130,11 +363,22 @@ eth_igc_dev_init(struct rte_eth_dev *dev)
 	 */
 	dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;

+	hw->mac.get_link_status = 1;
+
+	/* Indicate SOL/IDER usage */
+	if (igc_check_reset_block(hw) < 0)
+		PMD_INIT_LOG(ERR,
+			"PHY reset is blocked due to SOL/IDER session.");
+
 	PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 			dev->data->port_id, pci_dev->id.vendor_id,
 			pci_dev->id.device_id);

 	return 0;
+
+err_late:
+	igc_hw_control_release(hw);
+	return error;
 }

 static int
@ -224,7 +468,8 @@ eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	struct rte_pci_device *pci_dev)
 {
 	PMD_INIT_FUNC_TRACE();
-	return rte_eth_dev_pci_generic_probe(pci_dev, 0, eth_igc_dev_init);
+	return rte_eth_dev_pci_generic_probe(pci_dev,
+		sizeof(struct igc_adapter), eth_igc_dev_init);
 }

 static int
--- a/drivers/net/igc/igc_ethdev.h
+++ b/drivers/net/igc/igc_ethdev.h
@ -5,12 +5,31 @@
 #ifndef _IGC_ETHDEV_H_
 #define _IGC_ETHDEV_H_

+#include <rte_ethdev.h>
+
+#include "base/igc_osdep.h"
+#include "base/igc_hw.h"
+#include "base/igc_i225.h"
+#include "base/igc_api.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif

 #define IGC_QUEUE_PAIRS_NUM		4

+/*
+ * Structure to store private data for each driver instance (for each port).
+ */
+struct igc_adapter {
+	struct igc_hw		hw;
+};
+
+#define IGC_DEV_PRIVATE(_dev)	((_dev)->data->dev_private)
+
+#define IGC_DEV_PRIVATE_HW(_dev) \
+	(&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
+
 #ifdef __cplusplus
 }
 #endif
--- a/drivers/net/igc/meson.build
+++ b/drivers/net/igc/meson.build
@ -1,7 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2019-2020 Intel Corporation

+subdir('base')
+objs = [base_objs]
+
 sources = files(
 	'igc_logs.c',
 	'igc_ethdev.c'
 )
+
+includes += include_directories('base')