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common/mlx5: query sampler object capability via DevX

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Update function mlx5_devx_cmd_query_hca_attr() to add the NIC Flow
Table attributes query, then get the log_max_flow_sampler_num from
flow table properties.

Add the related structs definition in mlx5_prm.h.

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This commit is contained in:
Jiawei Wang 2020-10-13 17:11:44 +03:00 committed by Ferruh Yigit
parent a3def85479
commit 8cc34c0801
3 changed files with 79 additions and 0 deletions
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27
drivers/common/mlx5/mlx5_devx_cmds.c
View File

@ -751,6 +751,33 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
if (!attr->eth_net_offloads)
return 0;
/* Query Flow Sampler Capability From FLow Table Properties Layout. */
memset(in, 0, sizeof(in));
memset(out, 0, sizeof(out));
MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
MLX5_HCA_CAP_OPMOD_GET_CUR);
rc = mlx5_glue->devx_general_cmd(ctx,
in, sizeof(in),
out, sizeof(out));
if (rc)
goto error;
status = MLX5_GET(query_hca_cap_out, out, status);
syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
if (status) {
DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
"status %x, syndrome = %x",
status, syndrome);
attr->log_max_ft_sampler_num = 0;
return -1;
}
hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->log_max_ft_sampler_num =
MLX5_GET(flow_table_nic_cap,
hcattr, flow_table_properties.log_max_ft_sampler_num);
/* Query HCA offloads for Ethernet protocol. */
memset(in, 0, sizeof(in));
memset(out, 0, sizeof(out));

1
drivers/common/mlx5/mlx5_devx_cmds.h
View File

@ -102,6 +102,7 @@ struct mlx5_hca_attr {
uint32_t scatter_fcs_w_decap_disable:1;
uint32_t regex:1;
uint32_t regexp_num_of_engines;
uint32_t log_max_ft_sampler_num:8;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
};

51
drivers/common/mlx5/mlx5_prm.h
View File

@ -1036,6 +1036,7 @@ enum {
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
};
@ -1470,12 +1471,62 @@ struct mlx5_ifc_virtio_emulation_cap_bits {
u8 reserved_at_1c0[0x620];
};
struct mlx5_ifc_flow_table_prop_layout_bits {
u8 ft_support[0x1];
u8 flow_tag[0x1];
u8 flow_counter[0x1];
u8 flow_modify_en[0x1];
u8 modify_root[0x1];
u8 identified_miss_table[0x1];
u8 flow_table_modify[0x1];
u8 reformat[0x1];
u8 decap[0x1];
u8 reset_root_to_default[0x1];
u8 pop_vlan[0x1];
u8 push_vlan[0x1];
u8 fpga_vendor_acceleration[0x1];
u8 pop_vlan_2[0x1];
u8 push_vlan_2[0x1];
u8 reformat_and_vlan_action[0x1];
u8 modify_and_vlan_action[0x1];
u8 sw_owner[0x1];
u8 reformat_l3_tunnel_to_l2[0x1];
u8 reformat_l2_to_l3_tunnel[0x1];
u8 reformat_and_modify_action[0x1];
u8 reserved_at_15[0x9];
u8 sw_owner_v2[0x1];
u8 reserved_at_1f[0x1];
u8 reserved_at_20[0x2];
u8 log_max_ft_size[0x6];
u8 log_max_modify_header_context[0x8];
u8 max_modify_header_actions[0x8];
u8 max_ft_level[0x8];
u8 reserved_at_40[0x8];
u8 log_max_ft_sampler_num[8];
u8 metadata_reg_b_width[0x8];
u8 metadata_reg_a_width[0x8];
u8 reserved_at_60[0x18];
u8 log_max_ft_num[0x8];
u8 reserved_at_80[0x10];
u8 log_max_flow_counter[0x8];
u8 log_max_destination[0x8];
u8 reserved_at_a0[0x18];
u8 log_max_flow[0x8];
u8 reserved_at_c0[0x140];
};
struct mlx5_ifc_flow_table_nic_cap_bits {
u8 reserved_at_0[0x200];
struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
};
union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
struct mlx5_ifc_per_protocol_networking_offload_caps_bits
per_protocol_networking_offload_caps;
struct mlx5_ifc_qos_cap_bits qos_cap;
struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
u8 reserved_at_0[0x8000];
};