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net/bnxt: divide ULP template database to smaller modules

Browse Source 
The ulp template db file is broken into three parts namely the
table, class and action files.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2020-06-12 18:20:17 +05:30 committed by Ferruh Yigit
parent 9202a56745
commit 8ce17d56a1
16 changed files with 5483 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/bnxt/meson.build
View File

@ -35,7 +35,9 @@ sources = files('bnxt_cpr.c',
'tf_ulp/bnxt_ulp.c',
'tf_ulp/ulp_mark_mgr.c',
'tf_ulp/ulp_flow_db.c',
'tf_ulp/ulp_template_db.c',
'tf_ulp/ulp_template_db_tbl.c',
'tf_ulp/ulp_template_db_class.c',
'tf_ulp/ulp_template_db_act.c',
'tf_ulp/ulp_utils.c',
'tf_ulp/ulp_mapper.c',
'tf_ulp/ulp_matcher.c',

4
drivers/net/bnxt/tf_ulp/Makefile
View File

@ -4,7 +4,9 @@
# Copyright(c) Broadcom Limited.
# All rights reserved.
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_tbl.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_class.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_act.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c

2
drivers/net/bnxt/tf_ulp/bnxt_ulp.c
View File

@ -15,7 +15,7 @@
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_mark_mgr.h"
#include "ulp_flow_db.h"

2
drivers/net/bnxt/tf_ulp/ulp_flow_db.h
View File

@ -7,7 +7,7 @@
#define _ULP_FLOW_DB_H_
#include "bnxt_ulp.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 128
#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 5

18
drivers/net/bnxt/tf_ulp/ulp_mapper.c
View File

@ -6,7 +6,7 @@
#include <rte_log.h>
#include <rte_malloc.h>
#include "bnxt.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_utils.h"
@ -898,13 +898,12 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
uint64_t flow_id)
{
struct ulp_flow_db_res_params fid_parms;
uint32_t vfr_flag, mark, gfid, mark_flag;
uint32_t mark, gfid, mark_flag;
int32_t rc = 0;
vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK)))
return rc; /* no need to perform gfid process */
/* Get the mark id details from action property */
@ -914,7 +913,6 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
TF_GET_GFID_FROM_FLOW_ID(flow_id, gfid);
mark_flag = BNXT_ULP_MARK_GLOBAL_HW_FID;
mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
gfid, mark);
if (rc) {
@ -940,14 +938,13 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct ulp_flow_db_res_params fid_parms;
uint32_t vfr_flag, act_idx, mark, mark_flag;
uint32_t act_idx, mark, mark_flag;
uint64_t val64;
int32_t rc = 0;
vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK)))
return rc; /* no need to perform mark action process */
/* Get the mark id details from action property */
@ -963,7 +960,6 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
}
act_idx = tfp_be_to_cpu_64(val64);
mark_flag = BNXT_ULP_MARK_LOCAL_HW_FID;
mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
act_idx, mark);
if (rc) {

2
drivers/net/bnxt/tf_ulp/ulp_mapper.h
View File

@ -10,7 +10,7 @@
#include <rte_flow.h>
#include <rte_flow_driver.h>
#include "tf_core.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "ulp_utils.h"

2
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
View File

@ -11,7 +11,7 @@
#include "tf_ext_flow_handle.h"
#include "ulp_mark_mgr.h"
#include "bnxt_tf_common.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define ULP_MARK_DB_ENTRY_SET_VALID(mark_info) ((mark_info)->flags |=\

2
drivers/net/bnxt/tf_ulp/ulp_matcher.h
View File

@ -8,7 +8,7 @@
#include <rte_log.h>
#include "bnxt.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"

2
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
View File

@ -4,7 +4,7 @@
*/
#include "bnxt.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_rte_parser.h"

2
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
View File

@ -9,7 +9,7 @@
#include <rte_log.h>
#include <rte_flow.h>
#include <rte_flow_driver.h>
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
/* defines to be used in the tunnel header parsing */

696
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c Normal file
View File

@ -0,0 +1,696 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2020 Broadcom
* All rights reserved.
*/
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
#include "ulp_rte_parser.h"
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_00a1] = 1,
[BNXT_ULP_ACT_HID_0040] = 2,
[BNXT_ULP_ACT_HID_0029] = 3
};
struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
[1] = {
.act_hid = BNXT_ULP_ACT_HID_00a1,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_VNIC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 0
},
[2] = {
.act_hid = BNXT_ULP_ACT_HID_0040,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VPORT |
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 1
},
[3] = {
.act_hid = BNXT_ULP_ACT_HID_0029,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_VNIC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 2
}
};
struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
[((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 1,
.start_tbl_idx = 0
},
[((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 1,
.start_tbl_idx = 1
},
[((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 1,
.start_tbl_idx = 2
}
};
struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 0,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_TX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 26,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 12,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 64,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
}
};
struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
{
.field_bit_size = 14,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 14,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 0,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 0,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 32,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 0,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 14,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
}
};

3412
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c Normal file
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File diff suppressed because it is too large Load Diff

587
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h Normal file
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@ -0,0 +1,587 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2020 Broadcom
* All rights reserved.
*/
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
#define BNXT_ULP_REGFILE_MAX_SZ 15
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
#define BNXT_ULP_CLASS_HID_SHFTR 16
#define BNXT_ULP_CLASS_HID_SHFTL 23
#define BNXT_ULP_CLASS_HID_MASK 255
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
#define BNXT_ULP_ACT_HID_SHFTR 0
#define BNXT_ULP_ACT_HID_SHFTL 23
#define BNXT_ULP_ACT_HID_MASK 255
#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002,
BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004,
BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008,
BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010,
BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020,
BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000,
BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000,
BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000,
BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000,
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000,
BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000,
BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
};
enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001,
BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002,
BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004,
BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008,
BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010,
BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020,
BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040,
BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080,
BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100,
BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200,
BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400,
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800,
BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000
};
enum bnxt_ulp_act_type {
BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
BNXT_ULP_ACT_TYPE_END = 2,
BNXT_ULP_ACT_TYPE_LAST = 3
};
enum bnxt_ulp_byte_order {
BNXT_ULP_BYTE_ORDER_BE = 0,
BNXT_ULP_BYTE_ORDER_LE = 1,
BNXT_ULP_BYTE_ORDER_LAST = 2
};
enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
BNXT_ULP_CF_IDX_INCOMING_IF = 7,
BNXT_ULP_CF_IDX_DIRECTION = 8,
BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
BNXT_ULP_CF_IDX_O_L3 = 10,
BNXT_ULP_CF_IDX_I_L3 = 11,
BNXT_ULP_CF_IDX_O_L4 = 12,
BNXT_ULP_CF_IDX_I_L4 = 13,
BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
BNXT_ULP_CF_IDX_LAST = 28
};
enum bnxt_ulp_critical_resource {
BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
};
enum bnxt_ulp_device_id {
BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
BNXT_ULP_DEVICE_ID_THOR = 1,
BNXT_ULP_DEVICE_ID_STINGRAY = 2,
BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
BNXT_ULP_DEVICE_ID_LAST = 4
};
enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_INGRESS = 0,
BNXT_ULP_DIRECTION_EGRESS = 1,
BNXT_ULP_DIRECTION_LAST = 2
};
enum bnxt_ulp_glb_regfile_index {
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
};
enum bnxt_ulp_hdr_type {
BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
BNXT_ULP_HDR_TYPE_END = 2,
BNXT_ULP_HDR_TYPE_LAST = 3
};
enum bnxt_ulp_mark_enable {
BNXT_ULP_MARK_ENABLE_NO = 0,
BNXT_ULP_MARK_ENABLE_YES = 1,
BNXT_ULP_MARK_ENABLE_LAST = 2
};
enum bnxt_ulp_mask_opc {
BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
BNXT_ULP_MASK_OPC_ADD_PAD = 4,
BNXT_ULP_MASK_OPC_LAST = 5
};
enum bnxt_ulp_match_type {
BNXT_ULP_MATCH_TYPE_EM = 0,
BNXT_ULP_MATCH_TYPE_WC = 1,
BNXT_ULP_MATCH_TYPE_LAST = 2
};
enum bnxt_ulp_priority {
BNXT_ULP_PRIORITY_LEVEL_0 = 0,
BNXT_ULP_PRIORITY_LEVEL_1 = 1,
BNXT_ULP_PRIORITY_LEVEL_2 = 2,
BNXT_ULP_PRIORITY_LEVEL_3 = 3,
BNXT_ULP_PRIORITY_LEVEL_4 = 4,
BNXT_ULP_PRIORITY_LEVEL_5 = 5,
BNXT_ULP_PRIORITY_LEVEL_6 = 6,
BNXT_ULP_PRIORITY_LEVEL_7 = 7,
BNXT_ULP_PRIORITY_NOT_USED = 8,
BNXT_ULP_PRIORITY_LAST = 9
};
enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
BNXT_ULP_REGFILE_INDEX_LAST = 15
};
enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
BNXT_ULP_RESULT_OPC_LAST = 7
};
enum bnxt_ulp_search_before_alloc {
BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
};
enum bnxt_ulp_spec_opc {
BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
BNXT_ULP_SPEC_OPC_LAST = 6
};
enum bnxt_ulp_vfr_flag {
BNXT_ULP_VFR_FLAG_NO = 0,
BNXT_ULP_VFR_FLAG_YES = 1,
BNXT_ULP_VFR_FLAG_LAST = 2
};
enum bnxt_ulp_fdb_resource_flags {
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
};
enum bnxt_ulp_fdb_type {
BNXT_ULP_FDB_TYPE_DEFAULT = 1,
BNXT_ULP_FDB_TYPE_REGULAR = 0
};
enum bnxt_ulp_flow_dir_bitmask {
BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
};
enum bnxt_ulp_match_type_bitmask {
BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
};
enum bnxt_ulp_resource_func {
BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
};
enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
};
enum bnxt_ulp_sym {
BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
BNXT_ULP_SYM_AGG_ERROR_NO = 0,
BNXT_ULP_SYM_AGG_ERROR_YES = 1,
BNXT_ULP_SYM_BIG_ENDIAN = 0,
BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
BNXT_ULP_SYM_ECV_VALID_NO = 0,
BNXT_ULP_SYM_ECV_VALID_YES = 1,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
BNXT_ULP_SYM_HREC_NEXT_NO = 0,
BNXT_ULP_SYM_HREC_NEXT_YES = 1,
BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
BNXT_ULP_SYM_IP_PROTO_TCP = 6,
BNXT_ULP_SYM_IP_PROTO_UDP = 17,
BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
BNXT_ULP_SYM_NO = 0,
BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
BNXT_ULP_SYM_POP_VLAN_NO = 0,
BNXT_ULP_SYM_POP_VLAN_YES = 1,
BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
BNXT_ULP_SYM_RESERVED_IGNORE = 0,
BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_YES = 1
};
enum bnxt_ulp_act_prop_sz {
BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
BNXT_ULP_ACT_PROP_SZ_MARK = 4,
BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
BNXT_ULP_ACT_PROP_SZ_METER = 4,
BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
BNXT_ULP_ACT_PROP_SZ_LAST = 4
};
enum bnxt_ulp_act_prop_idx {
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
BNXT_ULP_ACT_PROP_IDX_MARK = 44,
BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
BNXT_ULP_ACT_PROP_IDX_METER = 52,
BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
BNXT_ULP_ACT_PROP_IDX_LAST = 268
};
enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_0080 = 0x0080,
BNXT_ULP_CLASS_HID_0000 = 0x0000,
BNXT_ULP_CLASS_HID_0087 = 0x0087
};
enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_00a1 = 0x00a1,
BNXT_ULP_ACT_HID_0040 = 0x0040,
BNXT_ULP_ACT_HID_0029 = 0x0029
};
#endif

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drivers/net/bnxt/tf_ulp/ulp_template_db_field.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2020 Broadcom
* All rights reserved.
*/
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
enum bnxt_ulp_hf0 {
BNXT_ULP_HF0_IDX_SVIF_INDEX = 0,
BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1,
BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2,
BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3,
BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4,
BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5,
BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6,
BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7,
BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8,
BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9,
BNXT_ULP_HF0_IDX_O_IPV4_VER = 10,
BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11,
BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12,
BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13,
BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14,
BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15,
BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16,
BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17,
BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18,
BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19,
BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20,
BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21,
BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22,
BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
};
enum bnxt_ulp_hf1 {
BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
};
enum bnxt_ulp_hf2 {
BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
};
enum bnxt_ulp_hf_bitmask0 {
BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000,
BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000,
BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000,
BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000,
BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
};
enum bnxt_ulp_hf_bitmask1 {
BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
};
enum bnxt_ulp_hf_bitmask2 {
BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
};
#endif

542
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c Normal file
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@ -0,0 +1,542 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2020 Broadcom
* All rights reserved.
*/
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
#include "ulp_rte_parser.h"
uint32_t ulp_act_prop_map_table[] = {
[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE,
[BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] =
BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,
[BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =
BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,
[BNXT_ULP_ACT_PROP_IDX_PORT_ID] =
BNXT_ULP_ACT_PROP_SZ_PORT_ID,
[BNXT_ULP_ACT_PROP_IDX_VNIC] =
BNXT_ULP_ACT_PROP_SZ_VNIC,
[BNXT_ULP_ACT_PROP_IDX_VPORT] =
BNXT_ULP_ACT_PROP_SZ_VPORT,
[BNXT_ULP_ACT_PROP_IDX_MARK] =
BNXT_ULP_ACT_PROP_SZ_MARK,
[BNXT_ULP_ACT_PROP_IDX_COUNT] =
BNXT_ULP_ACT_PROP_SZ_COUNT,
[BNXT_ULP_ACT_PROP_IDX_METER] =
BNXT_ULP_ACT_PROP_SZ_METER,
[BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] =
BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC,
[BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] =
BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN,
[BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP] =
BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP,
[BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID] =
BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID,
[BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] =
BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC,
[BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] =
BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST,
[BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] =
BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC,
[BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] =
BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST,
[BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] =
BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC,
[BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] =
BNXT_ULP_ACT_PROP_SZ_SET_TP_DST,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6,
[BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] =
BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP,
[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] =
BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN,
[BNXT_ULP_ACT_PROP_IDX_LAST] =
BNXT_ULP_ACT_PROP_SZ_LAST
};
struct bnxt_ulp_rte_act_info ulp_act_info[] = {
[RTE_FLOW_ACTION_TYPE_END] = {
.act_type = BNXT_ULP_ACT_TYPE_END,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_VOID] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_void_act_handler
},
[RTE_FLOW_ACTION_TYPE_PASSTHRU] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_JUMP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_MARK] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_mark_act_handler
},
[RTE_FLOW_ACTION_TYPE_FLAG] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_QUEUE] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DROP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_drop_act_handler
},
[RTE_FLOW_ACTION_TYPE_COUNT] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_count_act_handler
},
[RTE_FLOW_ACTION_TYPE_RSS] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_rss_act_handler
},
[RTE_FLOW_ACTION_TYPE_PF] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_pf_act_handler
},
[RTE_FLOW_ACTION_TYPE_VF] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vf_act_handler
},
[RTE_FLOW_ACTION_TYPE_PHY_PORT] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_phy_port_act_handler
},
[RTE_FLOW_ACTION_TYPE_PORT_ID] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_port_id_act_handler
},
[RTE_FLOW_ACTION_TYPE_METER] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SECURITY] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vxlan_encap_act_handler
},
[RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_vxlan_decap_act_handler
},
[RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_RAW_DECAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_TP_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_MAC_SWAP] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_TTL] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
}
};
struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
TF_DIR_RX] = {
.num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
TF_DIR_TX] = {
.num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
TF_DIR_RX] = {
.num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
TF_DIR_TX] = {
.num_entries = 16384
}
};
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.global_fid_enable = BNXT_ULP_SYM_YES,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.lfid_entries = 16384,
.lfid_entry_size = 4,
.gfid_entries = 65536,
.gfid_entry_size = 4,
.num_flows = 32768,
.num_resources_per_flow = 8
}
};
struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
[0] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
.direction = TF_DIR_RX
},
[1] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
.direction = TF_DIR_TX
}
};
struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
[RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_END,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VOID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_void_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_INVERT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ANY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PF] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_pf_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_VF] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vf_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_phy_port_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_PORT_ID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_port_id_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_RAW] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_eth_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_VLAN] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vlan_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_IPV4] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_ipv4_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_IPV6] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_ipv6_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_ICMP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_UDP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_udp_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_TCP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_tcp_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_SCTP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VXLAN] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_vxlan_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_E_TAG] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_NVGRE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_MPLS] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GRE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_FUZZY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTPC] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTPU] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ESP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GENEVE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_MARK] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_META] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GTP_PSC] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOES] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOED] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_NSH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_IGMP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_AH] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_HIGIG2] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
}
};
uint32_t bnxt_ulp_encap_vtag_map[] = {
[0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
[1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
[2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
};

2
drivers/net/bnxt/tf_ulp/ulp_utils.h
View File

@ -7,7 +7,7 @@
#define _ULP_UTILS_H_
#include "bnxt.h"
#include "ulp_template_db.h"
#include "ulp_template_db_enum.h"
/*
* Macros for bitmap sets and gets