net/cxgbe: implement flow query operation
Add API to query filter hit and byte counts from hardware. Signed-off-by: Shagun Agrawal <shaguna@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
This commit is contained in:
Shagun Agrawal
Ferruh Yigit
parent
da23bc9d33
commit
8d3c12e193
@ -319,6 +319,7 @@ struct adapter {
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unsigned int vpd_flag;
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int use_unpacked_mode; /* unpacked rx mode state */
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rte_spinlock_t win0_lock;
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struct tid_info tids; /* Info used to access TID related tables */
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};
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@ -18,6 +18,9 @@ extern "C" {
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#define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
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#define T4_MEMORY_WRITE 0
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#define T4_MEMORY_READ 1
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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};
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@ -47,6 +50,8 @@ enum cc_fec {
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FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
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};
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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@ -502,5 +507,15 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
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int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
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int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
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int t4_seeprom_wp(struct adapter *adapter, int enable);
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int t4_memory_rw_addr(struct adapter *adap, int win,
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u32 addr, u32 len, void *hbuf, int dir);
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int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
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u32 len, void *hbuf, int dir);
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static inline int t4_memory_rw(struct adapter *adap, int win,
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int mtype, u32 maddr, u32 len,
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void *hbuf, int dir)
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{
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return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
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}
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fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
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#endif /* __CHELSIO_COMMON_H */
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@ -5215,3 +5215,212 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
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}
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return 0;
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}
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/**
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* t4_memory_rw_addr - read/write adapter memory via PCIE memory window
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* @adap: the adapter
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* @win: PCI-E Memory Window to use
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* @addr: address within adapter memory
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* @len: amount of memory to transfer
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* @hbuf: host memory buffer
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* @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
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*
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* Reads/writes an [almost] arbitrary memory region in the firmware: the
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* firmware memory address and host buffer must be aligned on 32-bit
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* boudaries; the length may be arbitrary.
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*
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* NOTES:
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* 1. The memory is transferred as a raw byte sequence from/to the
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* firmware's memory. If this memory contains data structures which
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* contain multi-byte integers, it's the caller's responsibility to
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* perform appropriate byte order conversions.
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*
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* 2. It is the Caller's responsibility to ensure that no other code
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* uses the specified PCI-E Memory Window while this routine is
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* using it. This is typically done via the use of OS-specific
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* locks, etc.
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*/
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int t4_memory_rw_addr(struct adapter *adap, int win, u32 addr,
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u32 len, void *hbuf, int dir)
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{
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u32 pos, offset, resid;
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u32 win_pf, mem_reg, mem_aperture, mem_base;
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u32 *buf;
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/* Argument sanity checks ...*/
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if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
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return -EINVAL;
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buf = (u32 *)hbuf;
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/* It's convenient to be able to handle lengths which aren't a
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* multiple of 32-bits because we often end up transferring files to
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* the firmware. So we'll handle that by normalizing the length here
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* and then handling any residual transfer at the end.
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*/
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resid = len & 0x3;
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len -= resid;
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/* Each PCI-E Memory Window is programmed with a window size -- or
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* "aperture" -- which controls the granularity of its mapping onto
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* adapter memory. We need to grab that aperture in order to know
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* how to use the specified window. The window is also programmed
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* with the base address of the Memory Window in BAR0's address
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* space. For T4 this is an absolute PCI-E Bus Address. For T5
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* the address is relative to BAR0.
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*/
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mem_reg = t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
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win));
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mem_aperture = 1 << (G_WINDOW(mem_reg) + X_WINDOW_SHIFT);
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mem_base = G_PCIEOFST(mem_reg) << X_PCIEOFST_SHIFT;
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win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->pf);
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/* Calculate our initial PCI-E Memory Window Position and Offset into
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* that Window.
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*/
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pos = addr & ~(mem_aperture - 1);
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offset = addr - pos;
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/* Set up initial PCI-E Memory Window to cover the start of our
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* transfer. (Read it back to ensure that changes propagate before we
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* attempt to use the new value.)
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*/
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t4_write_reg(adap,
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PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win),
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pos | win_pf);
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t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win));
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/* Transfer data to/from the adapter as long as there's an integral
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* number of 32-bit transfers to complete.
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*
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* A note on Endianness issues:
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*
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* The "register" reads and writes below from/to the PCI-E Memory
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* Window invoke the standard adapter Big-Endian to PCI-E Link
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* Little-Endian "swizzel." As a result, if we have the following
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* data in adapter memory:
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*
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* Memory: ... | b0 | b1 | b2 | b3 | ...
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* Address: i+0 i+1 i+2 i+3
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*
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* Then a read of the adapter memory via the PCI-E Memory Window
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* will yield:
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*
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* x = readl(i)
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* 31 0
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* [ b3 | b2 | b1 | b0 ]
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*
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* If this value is stored into local memory on a Little-Endian system
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* it will show up correctly in local memory as:
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*
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* ( ..., b0, b1, b2, b3, ... )
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*
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* But on a Big-Endian system, the store will show up in memory
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* incorrectly swizzled as:
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*
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* ( ..., b3, b2, b1, b0, ... )
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*
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* So we need to account for this in the reads and writes to the
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* PCI-E Memory Window below by undoing the register read/write
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* swizzels.
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*/
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while (len > 0) {
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if (dir == T4_MEMORY_READ)
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*buf++ = le32_to_cpu((__le32)t4_read_reg(adap,
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mem_base +
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offset));
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else
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t4_write_reg(adap, mem_base + offset,
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(u32)cpu_to_le32(*buf++));
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offset += sizeof(__be32);
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len -= sizeof(__be32);
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/* If we've reached the end of our current window aperture,
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* move the PCI-E Memory Window on to the next. Note that
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* doing this here after "len" may be 0 allows us to set up
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* the PCI-E Memory Window for a possible final residual
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* transfer below ...
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*/
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if (offset == mem_aperture) {
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pos += mem_aperture;
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offset = 0;
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t4_write_reg(adap,
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PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET,
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win), pos | win_pf);
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t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET,
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win));
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}
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}
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/* If the original transfer had a length which wasn't a multiple of
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* 32-bits, now's where we need to finish off the transfer of the
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* residual amount. The PCI-E Memory Window has already been moved
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* above (if necessary) to cover this final transfer.
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*/
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if (resid) {
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union {
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u32 word;
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char byte[4];
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} last;
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unsigned char *bp;
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int i;
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if (dir == T4_MEMORY_READ) {
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last.word = le32_to_cpu((__le32)t4_read_reg(adap,
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mem_base +
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offset));
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for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
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bp[i] = last.byte[i];
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} else {
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last.word = *buf;
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for (i = resid; i < 4; i++)
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last.byte[i] = 0;
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t4_write_reg(adap, mem_base + offset,
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(u32)cpu_to_le32(last.word));
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}
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}
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return 0;
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}
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/**
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* t4_memory_rw_mtype -read/write EDC 0, EDC 1 or MC via PCIE memory window
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* @adap: the adapter
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* @win: PCI-E Memory Window to use
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* @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
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* @maddr: address within indicated memory type
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* @len: amount of memory to transfer
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* @hbuf: host memory buffer
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* @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
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*
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* Reads/writes adapter memory using t4_memory_rw_addr(). This routine
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* provides an (memory type, address within memory type) interface.
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*/
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int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
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u32 len, void *hbuf, int dir)
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{
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u32 mtype_offset;
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u32 edc_size, mc_size;
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/* Offset into the region of memory which is being accessed
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* MEM_EDC0 = 0
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* MEM_EDC1 = 1
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* MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
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* MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
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*/
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edc_size = G_EDRAM0_SIZE(t4_read_reg(adap, A_MA_EDRAM0_BAR));
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if (mtype != MEM_MC1) {
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mtype_offset = (mtype * (edc_size * 1024 * 1024));
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} else {
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mc_size = G_EXT_MEM0_SIZE(t4_read_reg(adap,
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A_MA_EXT_MEMORY0_BAR));
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mtype_offset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
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}
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return t4_memory_rw_addr(adap, win,
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mtype_offset + maddr, len,
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hbuf, dir);
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}
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@ -42,6 +42,10 @@ enum {
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SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,
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};
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enum {
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TCB_SIZE = 128, /* TCB size */
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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__be32 qid;
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__be16 cidx;
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@ -458,6 +458,7 @@
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#define F_CRXPKTENC V_CRXPKTENC(1U)
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#define TP_BASE_ADDR 0x7d00
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#define A_TP_CMM_TCB_BASE 0x7d10
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#define A_TP_TIMER_RESOLUTION 0x7d90
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@ -574,6 +575,21 @@
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#define S_RM_OVLAN 9
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#define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
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/* registers for module MA */
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#define A_MA_EDRAM0_BAR 0x77c0
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#define S_EDRAM0_SIZE 0
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#define M_EDRAM0_SIZE 0xfffU
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#define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
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#define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
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#define A_MA_EXT_MEMORY0_BAR 0x77c8
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#define S_EXT_MEM0_SIZE 0
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#define M_EXT_MEM0_SIZE 0xfffU
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#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
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#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
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/* registers for module MPS */
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#define MPS_BASE_ADDR 0x9000
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#define T4VF_MPS_BASE_ADDR 0x0100
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@ -545,3 +545,65 @@ void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
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t4_complete(&ctx->completion);
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}
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}
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/*
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* Retrieve the packet count for the specified filter.
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*/
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int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
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u64 *c, bool get_byte)
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{
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struct filter_entry *f;
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unsigned int tcb_base, tcbaddr;
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int ret;
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tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
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if (fidx >= adapter->tids.nftids)
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return -ERANGE;
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f = &adapter->tids.ftid_tab[fidx];
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if (!f->valid)
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return -EINVAL;
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tcbaddr = tcb_base + f->tid * TCB_SIZE;
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if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
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/*
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* For T5, the Filter Packet Hit Count is maintained as a
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* 32-bit Big Endian value in the TCB field {timestamp}.
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* Similar to the craziness above, instead of the filter hit
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* count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
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* sizeof(u32)), it actually shows up at offset 24. Whacky.
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*/
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if (get_byte) {
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unsigned int word_offset = 4;
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__be64 be64_byte_count;
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t4_os_lock(&adapter->win0_lock);
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ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
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tcbaddr +
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(word_offset * sizeof(__be32)),
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sizeof(be64_byte_count),
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&be64_byte_count,
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T4_MEMORY_READ);
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t4_os_unlock(&adapter->win0_lock);
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if (ret < 0)
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return ret;
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*c = be64_to_cpu(be64_byte_count);
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} else {
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unsigned int word_offset = 6;
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__be32 be32_count;
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t4_os_lock(&adapter->win0_lock);
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ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
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tcbaddr +
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(word_offset * sizeof(__be32)),
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sizeof(be32_count), &be32_count,
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T4_MEMORY_READ);
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t4_os_unlock(&adapter->win0_lock);
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if (ret < 0)
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return ret;
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*c = (u64)be32_to_cpu(be32_count);
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}
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}
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return 0;
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}
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@ -220,4 +220,6 @@ int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
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struct filter_ctx *ctx);
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int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family);
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int validate_filter(struct adapter *adap, struct ch_filter_specification *fs);
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int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
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u64 *c, bool get_byte);
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#endif /* _CXGBE_FILTER_H_ */
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@ -522,6 +522,66 @@ cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
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return 0;
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}
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static int __cxgbe_flow_query(struct rte_flow *flow, u64 *count,
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u64 *byte_count)
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{
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struct adapter *adap = ethdev2adap(flow->dev);
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unsigned int fidx = flow->fidx;
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int ret = 0;
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ret = cxgbe_get_filter_count(adap, fidx, count, 0);
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if (ret)
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return ret;
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return cxgbe_get_filter_count(adap, fidx, byte_count, 1);
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}
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static int
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cxgbe_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
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const struct rte_flow_action *action, void *data,
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struct rte_flow_error *e)
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{
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struct ch_filter_specification fs;
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struct rte_flow_query_count *c;
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struct filter_entry *f;
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int ret;
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RTE_SET_USED(dev);
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f = flow->f;
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fs = f->fs;
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if (action->type != RTE_FLOW_ACTION_TYPE_COUNT)
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return rte_flow_error_set(e, ENOTSUP,
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RTE_FLOW_ERROR_TYPE_ACTION, NULL,
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"only count supported for query");
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/*
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* This is a valid operation, Since we are allowed to do chelsio
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* specific operations in rte side of our code but not vise-versa
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*
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* So, fs can be queried/modified here BUT rte_flow_query_count
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* cannot be worked on by the lower layer since we want to maintain
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* it as rte_flow agnostic.
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*/
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if (!fs.hitcnts)
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return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
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&fs, "filter hit counters were not"
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" enabled during filter creation");
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c = (struct rte_flow_query_count *)data;
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ret = __cxgbe_flow_query(flow, &c->hits, &c->bytes);
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if (ret)
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return rte_flow_error_set(e, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
|
||||
f, "cxgbe pmd failed to"
|
||||
" perform query");
|
||||
|
||||
/* Query was successful */
|
||||
c->bytes_set = 1;
|
||||
c->hits_set = 1;
|
||||
|
||||
return 0; /* success / partial_success */
|
||||
}
|
||||
|
||||
static int
|
||||
cxgbe_flow_validate(struct rte_eth_dev *dev,
|
||||
const struct rte_flow_attr *attr,
|
||||
@ -577,7 +637,7 @@ static const struct rte_flow_ops cxgbe_flow_ops = {
|
||||
.create = cxgbe_flow_create,
|
||||
.destroy = cxgbe_flow_destroy,
|
||||
.flush = NULL,
|
||||
.query = NULL,
|
||||
.query = cxgbe_flow_query,
|
||||
.isolate = NULL,
|
||||
};
|
||||
|
||||
|
||||
@ -1527,6 +1527,7 @@ int cxgbe_probe(struct adapter *adapter)
|
||||
|
||||
t4_os_lock_init(&adapter->mbox_lock);
|
||||
TAILQ_INIT(&adapter->mbox_list);
|
||||
t4_os_lock_init(&adapter->win0_lock);
|
||||
|
||||
err = t4_prep_adapter(adapter);
|
||||
if (err)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user