i40e: base driver
Add shared code source files to support basic operations to be called in poll mode driver. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
This commit is contained in:
Helin Zhang
Thomas Monjalon
parent
7f9bc20792
commit
8db9e2a1b2
1103
lib/librte_pmd_i40e/i40e/i40e_adminq.c
Normal file
1103
lib/librte_pmd_i40e/i40e/i40e_adminq.c
Normal file
File diff suppressed because it is too large
Load Diff
158
lib/librte_pmd_i40e/i40e/i40e_adminq.h
Normal file
158
lib/librte_pmd_i40e/i40e/i40e_adminq.h
Normal file
@ -0,0 +1,158 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_ADMINQ_H_
|
||||
#define _I40E_ADMINQ_H_
|
||||
|
||||
#include "i40e_osdep.h"
|
||||
#include "i40e_adminq_cmd.h"
|
||||
|
||||
#define I40E_ADMINQ_DESC(R, i) \
|
||||
(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
|
||||
|
||||
#define I40E_ADMINQ_DESC_ALIGNMENT 4096
|
||||
|
||||
struct i40e_adminq_ring {
|
||||
struct i40e_virt_mem dma_head; /* space for dma structures */
|
||||
struct i40e_dma_mem desc_buf; /* descriptor ring memory */
|
||||
struct i40e_virt_mem cmd_buf; /* command buffer memory */
|
||||
|
||||
union {
|
||||
struct i40e_dma_mem *asq_bi;
|
||||
struct i40e_dma_mem *arq_bi;
|
||||
} r;
|
||||
|
||||
u16 count; /* Number of descriptors */
|
||||
u16 rx_buf_len; /* Admin Receive Queue buffer length */
|
||||
|
||||
/* used for interrupt processing */
|
||||
u16 next_to_use;
|
||||
u16 next_to_clean;
|
||||
|
||||
/* used for queue tracking */
|
||||
u32 head;
|
||||
u32 tail;
|
||||
u32 len;
|
||||
u32 bah;
|
||||
u32 bal;
|
||||
};
|
||||
|
||||
/* ASQ transaction details */
|
||||
struct i40e_asq_cmd_details {
|
||||
void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
|
||||
u64 cookie;
|
||||
u16 flags_ena;
|
||||
u16 flags_dis;
|
||||
bool async;
|
||||
bool postpone;
|
||||
};
|
||||
|
||||
#define I40E_ADMINQ_DETAILS(R, i) \
|
||||
(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
|
||||
|
||||
/* ARQ event information */
|
||||
struct i40e_arq_event_info {
|
||||
struct i40e_aq_desc desc;
|
||||
u16 msg_size;
|
||||
u8 *msg_buf;
|
||||
};
|
||||
|
||||
/* Admin Queue information */
|
||||
struct i40e_adminq_info {
|
||||
struct i40e_adminq_ring arq; /* receive queue */
|
||||
struct i40e_adminq_ring asq; /* send queue */
|
||||
u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
|
||||
u16 num_arq_entries; /* receive queue depth */
|
||||
u16 num_asq_entries; /* send queue depth */
|
||||
u16 arq_buf_size; /* receive queue buffer size */
|
||||
u16 asq_buf_size; /* send queue buffer size */
|
||||
u16 fw_maj_ver; /* firmware major version */
|
||||
u16 fw_min_ver; /* firmware minor version */
|
||||
u16 api_maj_ver; /* api major version */
|
||||
u16 api_min_ver; /* api minor version */
|
||||
bool nvm_busy;
|
||||
bool nvm_release_on_done;
|
||||
|
||||
struct i40e_spinlock asq_spinlock; /* Send queue spinlock */
|
||||
struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */
|
||||
|
||||
/* last status values on send and receive queues */
|
||||
enum i40e_admin_queue_err asq_last_status;
|
||||
enum i40e_admin_queue_err arq_last_status;
|
||||
};
|
||||
#ifdef I40E_NVMUPD_SUPPORT
|
||||
|
||||
/**
|
||||
* i40e_aq_rc_to_posix - convert errors to user-land codes
|
||||
* aq_rc: AdminQ error code to convert
|
||||
**/
|
||||
STATIC inline int i40e_aq_rc_to_posix(u16 aq_rc)
|
||||
{
|
||||
int aq_to_posix[] = {
|
||||
0, /* I40E_AQ_RC_OK */
|
||||
-EPERM, /* I40E_AQ_RC_EPERM */
|
||||
-ENOENT, /* I40E_AQ_RC_ENOENT */
|
||||
-ESRCH, /* I40E_AQ_RC_ESRCH */
|
||||
-EINTR, /* I40E_AQ_RC_EINTR */
|
||||
-EIO, /* I40E_AQ_RC_EIO */
|
||||
-ENXIO, /* I40E_AQ_RC_ENXIO */
|
||||
-E2BIG, /* I40E_AQ_RC_E2BIG */
|
||||
-EAGAIN, /* I40E_AQ_RC_EAGAIN */
|
||||
-ENOMEM, /* I40E_AQ_RC_ENOMEM */
|
||||
-EACCES, /* I40E_AQ_RC_EACCES */
|
||||
-EFAULT, /* I40E_AQ_RC_EFAULT */
|
||||
-EBUSY, /* I40E_AQ_RC_EBUSY */
|
||||
-EEXIST, /* I40E_AQ_RC_EEXIST */
|
||||
-EINVAL, /* I40E_AQ_RC_EINVAL */
|
||||
-ENOTTY, /* I40E_AQ_RC_ENOTTY */
|
||||
-ENOSPC, /* I40E_AQ_RC_ENOSPC */
|
||||
-ENOSYS, /* I40E_AQ_RC_ENOSYS */
|
||||
-ERANGE, /* I40E_AQ_RC_ERANGE */
|
||||
-EPIPE, /* I40E_AQ_RC_EFLUSHED */
|
||||
-ESPIPE, /* I40E_AQ_RC_BAD_ADDR */
|
||||
-EROFS, /* I40E_AQ_RC_EMODE */
|
||||
-EFBIG, /* I40E_AQ_RC_EFBIG */
|
||||
};
|
||||
|
||||
return aq_to_posix[aq_rc];
|
||||
}
|
||||
#endif
|
||||
|
||||
/* general information */
|
||||
#define I40E_AQ_LARGE_BUF 512
|
||||
#define I40E_ASQ_CMD_TIMEOUT 100 /* msecs */
|
||||
|
||||
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
|
||||
u16 opcode);
|
||||
|
||||
#endif /* _I40E_ADMINQ_H_ */
|
||||
2179
lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h
Normal file
2179
lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h
Normal file
File diff suppressed because it is too large
Load Diff
65
lib/librte_pmd_i40e/i40e/i40e_alloc.h
Normal file
65
lib/librte_pmd_i40e/i40e/i40e_alloc.h
Normal file
@ -0,0 +1,65 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_ALLOC_H_
|
||||
#define _I40E_ALLOC_H_
|
||||
|
||||
struct i40e_hw;
|
||||
|
||||
/* Memory allocation types */
|
||||
enum i40e_memory_type {
|
||||
i40e_mem_arq_buf = 0, /* ARQ indirect command buffer */
|
||||
i40e_mem_asq_buf = 1,
|
||||
i40e_mem_atq_buf = 2, /* ATQ indirect command buffer */
|
||||
i40e_mem_arq_ring = 3, /* ARQ descriptor ring */
|
||||
i40e_mem_atq_ring = 4, /* ATQ descriptor ring */
|
||||
i40e_mem_pd = 5, /* Page Descriptor */
|
||||
i40e_mem_bp = 6, /* Backing Page - 4KB */
|
||||
i40e_mem_bp_jumbo = 7, /* Backing Page - > 4KB */
|
||||
i40e_mem_reserved
|
||||
};
|
||||
|
||||
/* prototype for functions used for dynamic memory allocation */
|
||||
enum i40e_status_code i40e_allocate_dma_mem(struct i40e_hw *hw,
|
||||
struct i40e_dma_mem *mem,
|
||||
enum i40e_memory_type type,
|
||||
u64 size, u32 alignment);
|
||||
enum i40e_status_code i40e_free_dma_mem(struct i40e_hw *hw,
|
||||
struct i40e_dma_mem *mem);
|
||||
enum i40e_status_code i40e_allocate_virt_mem(struct i40e_hw *hw,
|
||||
struct i40e_virt_mem *mem,
|
||||
u32 size);
|
||||
enum i40e_status_code i40e_free_virt_mem(struct i40e_hw *hw,
|
||||
struct i40e_virt_mem *mem);
|
||||
|
||||
#endif /* _I40E_ALLOC_H_ */
|
||||
4846
lib/librte_pmd_i40e/i40e/i40e_common.c
Normal file
4846
lib/librte_pmd_i40e/i40e/i40e_common.c
Normal file
File diff suppressed because it is too large
Load Diff
1104
lib/librte_pmd_i40e/i40e/i40e_dcb.c
Normal file
1104
lib/librte_pmd_i40e/i40e/i40e_dcb.c
Normal file
File diff suppressed because it is too large
Load Diff
264
lib/librte_pmd_i40e/i40e/i40e_dcb.h
Normal file
264
lib/librte_pmd_i40e/i40e/i40e_dcb.h
Normal file
@ -0,0 +1,264 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_DCB_H_
|
||||
#define _I40E_DCB_H_
|
||||
|
||||
#include "i40e_type.h"
|
||||
|
||||
#define I40E_DCBX_OFFLOAD_DISABLED 0
|
||||
#define I40E_DCBX_OFFLOAD_ENABLED 1
|
||||
|
||||
#define I40E_DCBX_STATUS_NOT_STARTED 0
|
||||
#define I40E_DCBX_STATUS_IN_PROGRESS 1
|
||||
#define I40E_DCBX_STATUS_DONE 2
|
||||
#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
|
||||
#define I40E_DCBX_STATUS_DISABLED 7
|
||||
|
||||
#define I40E_TLV_TYPE_END 0
|
||||
#define I40E_TLV_TYPE_ORG 127
|
||||
|
||||
#define I40E_IEEE_8021QAZ_OUI 0x0080C2
|
||||
#define I40E_IEEE_SUBTYPE_ETS_CFG 9
|
||||
#define I40E_IEEE_SUBTYPE_ETS_REC 10
|
||||
#define I40E_IEEE_SUBTYPE_PFC_CFG 11
|
||||
#define I40E_IEEE_SUBTYPE_APP_PRI 12
|
||||
|
||||
#define I40E_LLDP_ADMINSTATUS_DISABLED 0
|
||||
#define I40E_LLDP_ADMINSTATUS_ENABLED_RX 1
|
||||
#define I40E_LLDP_ADMINSTATUS_ENABLED_TX 2
|
||||
#define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX 3
|
||||
|
||||
/* Defines for LLDP TLV header */
|
||||
#define I40E_LLDP_MIB_HLEN 14
|
||||
#define I40E_LLDP_TLV_LEN_SHIFT 0
|
||||
#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
|
||||
#define I40E_LLDP_TLV_TYPE_SHIFT 9
|
||||
#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
|
||||
#define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
|
||||
#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
|
||||
#define I40E_LLDP_TLV_OUI_SHIFT 8
|
||||
#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
|
||||
|
||||
/* Defines for IEEE ETS TLV */
|
||||
#define I40E_IEEE_ETS_MAXTC_SHIFT 0
|
||||
#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
|
||||
#define I40E_IEEE_ETS_CBS_SHIFT 6
|
||||
#define I40E_IEEE_ETS_CBS_MASK (0x1 << I40E_IEEE_ETS_CBS_SHIFT)
|
||||
#define I40E_IEEE_ETS_WILLING_SHIFT 7
|
||||
#define I40E_IEEE_ETS_WILLING_MASK (0x1 << I40E_IEEE_ETS_WILLING_SHIFT)
|
||||
#define I40E_IEEE_ETS_PRIO_0_SHIFT 0
|
||||
#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
|
||||
#define I40E_IEEE_ETS_PRIO_1_SHIFT 4
|
||||
#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
|
||||
|
||||
/* Defines for IEEE TSA types */
|
||||
#define I40E_IEEE_TSA_STRICT 0
|
||||
#define I40E_IEEE_TSA_CBS 1
|
||||
#define I40E_IEEE_TSA_ETS 2
|
||||
#define I40E_IEEE_TSA_VENDOR 255
|
||||
|
||||
/* Defines for IEEE PFC TLV */
|
||||
#define I40E_IEEE_PFC_CAP_SHIFT 0
|
||||
#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
|
||||
#define I40E_IEEE_PFC_MBC_SHIFT 6
|
||||
#define I40E_IEEE_PFC_MBC_MASK (0x1 << I40E_IEEE_PFC_MBC_SHIFT)
|
||||
#define I40E_IEEE_PFC_WILLING_SHIFT 7
|
||||
#define I40E_IEEE_PFC_WILLING_MASK (0x1 << I40E_IEEE_PFC_WILLING_SHIFT)
|
||||
|
||||
/* Defines for IEEE APP TLV */
|
||||
#define I40E_IEEE_APP_SEL_SHIFT 0
|
||||
#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)
|
||||
#define I40E_IEEE_APP_PRIO_SHIFT 5
|
||||
#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
|
||||
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
/* IEEE 802.1AB LLDP TLV structure */
|
||||
struct i40e_lldp_generic_tlv {
|
||||
__be16 typelength;
|
||||
u8 tlvinfo[1];
|
||||
};
|
||||
|
||||
/* IEEE 802.1AB LLDP Organization specific TLV */
|
||||
struct i40e_lldp_org_tlv {
|
||||
__be16 typelength;
|
||||
__be32 ouisubtype;
|
||||
u8 tlvinfo[1];
|
||||
};
|
||||
#pragma pack()
|
||||
|
||||
/*
|
||||
* TODO: The below structures related LLDP/DCBX variables
|
||||
* and statistics are defined but need to find how to get
|
||||
* the required information from the Firmware to use them
|
||||
*/
|
||||
|
||||
/* IEEE 802.1AB LLDP Agent Statistics */
|
||||
struct i40e_lldp_stats {
|
||||
u64 remtablelastchangetime;
|
||||
u64 remtableinserts;
|
||||
u64 remtabledeletes;
|
||||
u64 remtabledrops;
|
||||
u64 remtableageouts;
|
||||
u64 txframestotal;
|
||||
u64 rxframesdiscarded;
|
||||
u64 rxportframeerrors;
|
||||
u64 rxportframestotal;
|
||||
u64 rxporttlvsdiscardedtotal;
|
||||
u64 rxporttlvsunrecognizedtotal;
|
||||
u64 remtoomanyneighbors;
|
||||
};
|
||||
|
||||
/* IEEE 802.1Qaz DCBX variables */
|
||||
struct i40e_dcbx_variables {
|
||||
u32 defmaxtrafficclasses;
|
||||
u32 defprioritytcmapping;
|
||||
u32 deftcbandwidth;
|
||||
u32 deftsaassignment;
|
||||
};
|
||||
|
||||
#ifdef I40E_DCB_SW
|
||||
/* Data structures to pass for SW DCBX */
|
||||
struct i40e_rx_pb_config {
|
||||
u32 shared_pool_size;
|
||||
u32 shared_pool_high_wm;
|
||||
u32 shared_pool_low_wm;
|
||||
u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];
|
||||
u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];
|
||||
u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS];
|
||||
u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];
|
||||
u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];
|
||||
};
|
||||
|
||||
enum i40e_dcb_arbiter_mode {
|
||||
I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,
|
||||
I40E_DCB_ARB_MODE_ROUND_ROBIN = 1
|
||||
};
|
||||
|
||||
#define I40E_DEFAULT_PAUSE_TIME 0xffff
|
||||
#define I40E_MAX_FRAME_SIZE 4608 /* 4.5 KB */
|
||||
|
||||
#define I40E_DEVICE_RPB_SIZE 968000 /* 968 KB */
|
||||
|
||||
/* BitTimes (BT) conversion */
|
||||
#define I40E_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
|
||||
#define I40E_B2BT(BT) (BT * 8)
|
||||
#define I40E_BT2B(BT) ((BT + (8 - 1)) / (8))
|
||||
|
||||
/* Max Frame(TC) = MFS(max) + MFS(TC) */
|
||||
#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) I40E_B2BT(mfs_max + mfs_tc)
|
||||
|
||||
/* EEE Tx LPI Exit time in Bit Times */
|
||||
#define I40E_EEE_TX_LPI_EXIT_TIME 142500
|
||||
|
||||
/* PCI Round Trip Time in Bit Times */
|
||||
#define I40E_PCIRTT_LINK_SPEED_10G 20000
|
||||
#define I40E_PCIRTT_BYTE_LINK_SPEED_20G 40000
|
||||
#define I40E_PCIRTT_BYTE_LINK_SPEED_40G 80000
|
||||
|
||||
/* PFC Frame Delay Bit Times */
|
||||
#define I40E_PFC_FRAME_DELAY 672
|
||||
|
||||
/* Worst case Cable (10GBase-T) Delay Bit Times */
|
||||
#define I40E_CABLE_DELAY 5556
|
||||
|
||||
/* Higher Layer Delay @10G Bit Times */
|
||||
#define I40E_HIGHER_LAYER_DELAY_10G 6144
|
||||
|
||||
/* Interface Delays in Bit Times */
|
||||
/* TODO: Add for other link speeds 20G/40G/etc. */
|
||||
#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL 8192
|
||||
#define I40E_INTERFACE_DELAY_10G_MAC 8192
|
||||
#define I40E_INTERFACE_DELAY_10G_RS 8192
|
||||
|
||||
#define I40E_INTERFACE_DELAY_XGXS 2048
|
||||
#define I40E_INTERFACE_DELAY_XAUI 2048
|
||||
|
||||
#define I40E_INTERFACE_DELAY_10G_BASEX_PCS 2048
|
||||
#define I40E_INTERFACE_DELAY_10G_BASER_PCS 3584
|
||||
#define I40E_INTERFACE_DELAY_LX4_PMD 512
|
||||
#define I40E_INTERFACE_DELAY_CX4_PMD 512
|
||||
#define I40E_INTERFACE_DELAY_SERIAL_PMA 512
|
||||
#define I40E_INTERFACE_DELAY_PMD 512
|
||||
|
||||
#define I40E_INTERFACE_DELAY_10G_BASET 25600
|
||||
|
||||
/* delay values for with 10G BaseT in Bit Times */
|
||||
#define I40E_INTERFACE_DELAY_10G_COPPER \
|
||||
(I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \
|
||||
+ I40E_INTERFACE_DELAY_10G_BASET)
|
||||
#define I40E_DV_TC(mfs_max, mfs_tc) \
|
||||
((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \
|
||||
+ I40E_PFC_FRAME_DELAY \
|
||||
+ (2 * I40E_CABLE_DELAY) \
|
||||
+ (2 * I40E_INTERFACE_DELAY_10G_COPPER) \
|
||||
+ I40E_HIGHER_LAYER_DELAY_10G)
|
||||
#define I40E_STD_DV_TC(mfs_max, mfs_tc) \
|
||||
(I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max))
|
||||
|
||||
enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw,
|
||||
struct i40e_arq_event_info *e);
|
||||
/* APIs for SW DCBX */
|
||||
void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,
|
||||
enum i40e_dcb_arbiter_mode ets_mode,
|
||||
enum i40e_dcb_arbiter_mode non_ets_mode,
|
||||
u32 max_exponent, u8 lltc_map);
|
||||
void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,
|
||||
u8 num_tc, u8 num_ports);
|
||||
void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,
|
||||
u8 pfc_en, u8 *prio_tc);
|
||||
void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);
|
||||
u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);
|
||||
void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,
|
||||
u8 *mode, u8 *prio_type);
|
||||
void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);
|
||||
void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,
|
||||
u8 num_ports, bool eee_enabled,
|
||||
u8 pfc_en, u32 *mfs_tc,
|
||||
struct i40e_rx_pb_config *pb_cfg);
|
||||
void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
|
||||
struct i40e_rx_pb_config *old_pb_cfg,
|
||||
struct i40e_rx_pb_config *new_pb_cfg);
|
||||
#endif /* I40E_DCB_SW */
|
||||
enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,
|
||||
u16 *status);
|
||||
enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
|
||||
u8 bridgetype,
|
||||
struct i40e_dcbx_config *dcbcfg);
|
||||
enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw);
|
||||
#endif /* _I40E_DCB_H_ */
|
||||
188
lib/librte_pmd_i40e/i40e/i40e_diag.c
Normal file
188
lib/librte_pmd_i40e/i40e/i40e_diag.c
Normal file
@ -0,0 +1,188 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "i40e_diag.h"
|
||||
#include "i40e_prototype.h"
|
||||
|
||||
/**
|
||||
* i40e_diag_set_loopback
|
||||
* @hw: pointer to the hw struct
|
||||
* @mode: loopback mode
|
||||
*
|
||||
* Set chosen loopback mode
|
||||
**/
|
||||
enum i40e_status_code i40e_diag_set_loopback(struct i40e_hw *hw,
|
||||
enum i40e_lb_mode mode)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
|
||||
if (i40e_aq_set_lb_modes(hw, mode, NULL))
|
||||
ret_code = I40E_ERR_DIAG_TEST_FAILED;
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_diag_reg_pattern_test
|
||||
* @hw: pointer to the hw struct
|
||||
* @reg: reg to be tested
|
||||
* @mask: bits to be touched
|
||||
**/
|
||||
static enum i40e_status_code i40e_diag_reg_pattern_test(struct i40e_hw *hw,
|
||||
u32 reg, u32 mask)
|
||||
{
|
||||
const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
|
||||
u32 pat, val, orig_val;
|
||||
int i;
|
||||
|
||||
orig_val = rd32(hw, reg);
|
||||
for (i = 0; i < ARRAY_SIZE(patterns); i++) {
|
||||
pat = patterns[i];
|
||||
wr32(hw, reg, (pat & mask));
|
||||
val = rd32(hw, reg);
|
||||
if ((val & mask) != (pat & mask)) {
|
||||
#ifdef ETHTOOL_TEST
|
||||
i40e_debug(hw, I40E_DEBUG_DIAG,
|
||||
"%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
|
||||
__func__, reg, pat, val);
|
||||
#endif
|
||||
return I40E_ERR_DIAG_TEST_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
wr32(hw, reg, orig_val);
|
||||
val = rd32(hw, reg);
|
||||
if (val != orig_val) {
|
||||
#ifdef ETHTOOL_TEST
|
||||
i40e_debug(hw, I40E_DEBUG_DIAG,
|
||||
"%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
|
||||
__func__, reg, orig_val, val);
|
||||
#endif
|
||||
return I40E_ERR_DIAG_TEST_FAILED;
|
||||
}
|
||||
|
||||
return I40E_SUCCESS;
|
||||
}
|
||||
|
||||
struct i40e_diag_reg_test_info i40e_reg_list[] = {
|
||||
/* offset mask elements stride */
|
||||
{I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
|
||||
{I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
|
||||
{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
|
||||
{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
|
||||
{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
|
||||
{I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},
|
||||
{I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},
|
||||
{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
|
||||
{I40E_QINT_TQCTL(0), 0x000000FF, 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
|
||||
{I40E_QINT_RQCTL(0), 0x000000FF, 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
|
||||
{I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
/**
|
||||
* i40e_diag_reg_test
|
||||
* @hw: pointer to the hw struct
|
||||
*
|
||||
* Perform registers diagnostic test
|
||||
**/
|
||||
enum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u32 reg, mask;
|
||||
u32 i, j;
|
||||
|
||||
for (i = 0; i40e_reg_list[i].offset != 0 &&
|
||||
ret_code == I40E_SUCCESS; i++) {
|
||||
|
||||
/* set actual reg range for dynamically allocated resources */
|
||||
if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
|
||||
hw->func_caps.num_tx_qp != 0)
|
||||
i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
|
||||
if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
|
||||
i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
|
||||
i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
|
||||
i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
|
||||
i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
|
||||
hw->func_caps.num_msix_vectors != 0)
|
||||
i40e_reg_list[i].elements =
|
||||
hw->func_caps.num_msix_vectors - 1;
|
||||
|
||||
/* test register access */
|
||||
mask = i40e_reg_list[i].mask;
|
||||
for (j = 0; j < i40e_reg_list[i].elements &&
|
||||
ret_code == I40E_SUCCESS; j++) {
|
||||
reg = i40e_reg_list[i].offset
|
||||
+ (j * i40e_reg_list[i].stride);
|
||||
ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
|
||||
}
|
||||
}
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_diag_eeprom_test
|
||||
* @hw: pointer to the hw struct
|
||||
*
|
||||
* Perform EEPROM diagnostic test
|
||||
**/
|
||||
enum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw)
|
||||
{
|
||||
enum i40e_status_code ret_code;
|
||||
u16 reg_val;
|
||||
|
||||
/* read NVM control word and if NVM valid, validate EEPROM checksum*/
|
||||
ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val);
|
||||
if ((ret_code == I40E_SUCCESS) &&
|
||||
((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
|
||||
(0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {
|
||||
ret_code = i40e_validate_nvm_checksum(hw, NULL);
|
||||
} else {
|
||||
ret_code = I40E_ERR_DIAG_TEST_FAILED;
|
||||
}
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_diag_fw_alive_test
|
||||
* @hw: pointer to the hw struct
|
||||
*
|
||||
* Perform FW alive diagnostic test
|
||||
**/
|
||||
enum i40e_status_code i40e_diag_fw_alive_test(struct i40e_hw *hw)
|
||||
{
|
||||
UNREFERENCED_1PARAMETER(hw);
|
||||
return I40E_SUCCESS;
|
||||
}
|
||||
61
lib/librte_pmd_i40e/i40e/i40e_diag.h
Normal file
61
lib/librte_pmd_i40e/i40e/i40e_diag.h
Normal file
@ -0,0 +1,61 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_DIAG_H_
|
||||
#define _I40E_DIAG_H_
|
||||
|
||||
#include "i40e_type.h"
|
||||
|
||||
enum i40e_lb_mode {
|
||||
I40E_LB_MODE_NONE = 0x0,
|
||||
I40E_LB_MODE_PHY_LOCAL = I40E_AQ_LB_PHY_LOCAL,
|
||||
I40E_LB_MODE_PHY_REMOTE = I40E_AQ_LB_PHY_REMOTE,
|
||||
I40E_LB_MODE_MAC_LOCAL = I40E_AQ_LB_MAC_LOCAL,
|
||||
};
|
||||
|
||||
struct i40e_diag_reg_test_info {
|
||||
u32 offset; /* the base register */
|
||||
u32 mask; /* bits that can be tested */
|
||||
u32 elements; /* number of elements if array */
|
||||
u32 stride; /* bytes between each element */
|
||||
};
|
||||
|
||||
extern struct i40e_diag_reg_test_info i40e_reg_list[];
|
||||
|
||||
enum i40e_status_code i40e_diag_set_loopback(struct i40e_hw *hw,
|
||||
enum i40e_lb_mode mode);
|
||||
enum i40e_status_code i40e_diag_fw_alive_test(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw);
|
||||
|
||||
#endif /* _I40E_DIAG_H_ */
|
||||
373
lib/librte_pmd_i40e/i40e/i40e_hmc.c
Normal file
373
lib/librte_pmd_i40e/i40e/i40e_hmc.c
Normal file
@ -0,0 +1,373 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "i40e_osdep.h"
|
||||
#include "i40e_register.h"
|
||||
#include "i40e_status.h"
|
||||
#include "i40e_alloc.h"
|
||||
#include "i40e_hmc.h"
|
||||
#include "i40e_type.h"
|
||||
|
||||
/**
|
||||
* i40e_add_sd_table_entry - Adds a segment descriptor to the table
|
||||
* @hw: pointer to our hw struct
|
||||
* @hmc_info: pointer to the HMC configuration information struct
|
||||
* @sd_index: segment descriptor index to manipulate
|
||||
* @type: what type of segment descriptor we're manipulating
|
||||
* @direct_mode_sz: size to alloc in direct mode
|
||||
**/
|
||||
enum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
enum i40e_memory_type mem_type;
|
||||
bool dma_mem_alloc_done = false;
|
||||
struct i40e_dma_mem mem;
|
||||
u64 alloc_len;
|
||||
|
||||
if (NULL == hmc_info->sd_table.sd_entry) {
|
||||
ret_code = I40E_ERR_BAD_PTR;
|
||||
DEBUGOUT("i40e_add_sd_table_entry: bad sd_entry\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (sd_index >= hmc_info->sd_table.sd_cnt) {
|
||||
ret_code = I40E_ERR_INVALID_SD_INDEX;
|
||||
DEBUGOUT("i40e_add_sd_table_entry: bad sd_index\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[sd_index];
|
||||
if (!sd_entry->valid) {
|
||||
if (I40E_SD_TYPE_PAGED == type) {
|
||||
mem_type = i40e_mem_pd;
|
||||
alloc_len = I40E_HMC_PAGED_BP_SIZE;
|
||||
} else {
|
||||
mem_type = i40e_mem_bp_jumbo;
|
||||
alloc_len = direct_mode_sz;
|
||||
}
|
||||
|
||||
/* allocate a 4K pd page or 2M backing page */
|
||||
ret_code = i40e_allocate_dma_mem(hw, &mem, mem_type, alloc_len,
|
||||
I40E_HMC_PD_BP_BUF_ALIGNMENT);
|
||||
if (ret_code)
|
||||
goto exit;
|
||||
dma_mem_alloc_done = true;
|
||||
if (I40E_SD_TYPE_PAGED == type) {
|
||||
ret_code = i40e_allocate_virt_mem(hw,
|
||||
&sd_entry->u.pd_table.pd_entry_virt_mem,
|
||||
sizeof(struct i40e_hmc_pd_entry) * 512);
|
||||
if (ret_code)
|
||||
goto exit;
|
||||
sd_entry->u.pd_table.pd_entry =
|
||||
(struct i40e_hmc_pd_entry *)
|
||||
sd_entry->u.pd_table.pd_entry_virt_mem.va;
|
||||
i40e_memcpy(&sd_entry->u.pd_table.pd_page_addr,
|
||||
&mem, sizeof(struct i40e_dma_mem),
|
||||
I40E_NONDMA_TO_NONDMA);
|
||||
} else {
|
||||
i40e_memcpy(&sd_entry->u.bp.addr,
|
||||
&mem, sizeof(struct i40e_dma_mem),
|
||||
I40E_NONDMA_TO_NONDMA);
|
||||
sd_entry->u.bp.sd_pd_index = sd_index;
|
||||
}
|
||||
/* initialize the sd entry */
|
||||
hmc_info->sd_table.sd_entry[sd_index].entry_type = type;
|
||||
|
||||
/* increment the ref count */
|
||||
I40E_INC_SD_REFCNT(&hmc_info->sd_table);
|
||||
}
|
||||
/* Increment backing page reference count */
|
||||
if (I40E_SD_TYPE_DIRECT == sd_entry->entry_type)
|
||||
I40E_INC_BP_REFCNT(&sd_entry->u.bp);
|
||||
exit:
|
||||
if (I40E_SUCCESS != ret_code)
|
||||
if (dma_mem_alloc_done)
|
||||
i40e_free_dma_mem(hw, &mem);
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_add_pd_table_entry - Adds page descriptor to the specified table
|
||||
* @hw: pointer to our HW structure
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @pd_index: which page descriptor index to manipulate
|
||||
*
|
||||
* This function:
|
||||
* 1. Initializes the pd entry
|
||||
* 2. Adds pd_entry in the pd_table
|
||||
* 3. Mark the entry valid in i40e_hmc_pd_entry structure
|
||||
* 4. Initializes the pd_entry's ref count to 1
|
||||
* assumptions:
|
||||
* 1. The memory for pd should be pinned down, physically contiguous and
|
||||
* aligned on 4K boundary and zeroed memory.
|
||||
* 2. It should be 4K in size.
|
||||
**/
|
||||
enum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_pd_table *pd_table;
|
||||
struct i40e_hmc_pd_entry *pd_entry;
|
||||
struct i40e_dma_mem mem;
|
||||
u32 sd_idx, rel_pd_idx;
|
||||
u64 *pd_addr;
|
||||
u64 page_desc;
|
||||
|
||||
if (pd_index / I40E_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt) {
|
||||
ret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;
|
||||
DEBUGOUT("i40e_add_pd_table_entry: bad pd_index\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* find corresponding sd */
|
||||
sd_idx = (pd_index / I40E_HMC_PD_CNT_IN_SD);
|
||||
if (I40E_SD_TYPE_PAGED !=
|
||||
hmc_info->sd_table.sd_entry[sd_idx].entry_type)
|
||||
goto exit;
|
||||
|
||||
rel_pd_idx = (pd_index % I40E_HMC_PD_CNT_IN_SD);
|
||||
pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
|
||||
pd_entry = &pd_table->pd_entry[rel_pd_idx];
|
||||
if (!pd_entry->valid) {
|
||||
/* allocate a 4K backing page */
|
||||
ret_code = i40e_allocate_dma_mem(hw, &mem, i40e_mem_bp,
|
||||
I40E_HMC_PAGED_BP_SIZE,
|
||||
I40E_HMC_PD_BP_BUF_ALIGNMENT);
|
||||
if (ret_code)
|
||||
goto exit;
|
||||
|
||||
i40e_memcpy(&pd_entry->bp.addr, &mem,
|
||||
sizeof(struct i40e_dma_mem), I40E_NONDMA_TO_NONDMA);
|
||||
pd_entry->bp.sd_pd_index = pd_index;
|
||||
pd_entry->bp.entry_type = I40E_SD_TYPE_PAGED;
|
||||
/* Set page address and valid bit */
|
||||
page_desc = mem.pa | 0x1;
|
||||
|
||||
pd_addr = (u64 *)pd_table->pd_page_addr.va;
|
||||
pd_addr += rel_pd_idx;
|
||||
|
||||
/* Add the backing page physical address in the pd entry */
|
||||
i40e_memcpy(pd_addr, &page_desc, sizeof(u64),
|
||||
I40E_NONDMA_TO_DMA);
|
||||
|
||||
pd_entry->sd_index = sd_idx;
|
||||
pd_entry->valid = true;
|
||||
I40E_INC_PD_REFCNT(pd_table);
|
||||
}
|
||||
I40E_INC_BP_REFCNT(&pd_entry->bp);
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_remove_pd_bp - remove a backing page from a page descriptor
|
||||
* @hw: pointer to our HW structure
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: the page index
|
||||
* @is_pf: distinguishes a VF from a PF
|
||||
*
|
||||
* This function:
|
||||
* 1. Marks the entry in pd tabe (for paged address mode) or in sd table
|
||||
* (for direct address mode) invalid.
|
||||
* 2. Write to register PMPDINV to invalidate the backing page in FV cache
|
||||
* 3. Decrement the ref count for the pd _entry
|
||||
* assumptions:
|
||||
* 1. Caller can deallocate the memory used by backing storage after this
|
||||
* function returns.
|
||||
**/
|
||||
enum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_pd_entry *pd_entry;
|
||||
struct i40e_hmc_pd_table *pd_table;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
u32 sd_idx, rel_pd_idx;
|
||||
u64 *pd_addr;
|
||||
|
||||
/* calculate index */
|
||||
sd_idx = idx / I40E_HMC_PD_CNT_IN_SD;
|
||||
rel_pd_idx = idx % I40E_HMC_PD_CNT_IN_SD;
|
||||
if (sd_idx >= hmc_info->sd_table.sd_cnt) {
|
||||
ret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;
|
||||
DEBUGOUT("i40e_remove_pd_bp: bad idx\n");
|
||||
goto exit;
|
||||
}
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
|
||||
if (I40E_SD_TYPE_PAGED != sd_entry->entry_type) {
|
||||
ret_code = I40E_ERR_INVALID_SD_TYPE;
|
||||
DEBUGOUT("i40e_remove_pd_bp: wrong sd_entry type\n");
|
||||
goto exit;
|
||||
}
|
||||
/* get the entry and decrease its ref counter */
|
||||
pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
|
||||
pd_entry = &pd_table->pd_entry[rel_pd_idx];
|
||||
I40E_DEC_BP_REFCNT(&pd_entry->bp);
|
||||
if (pd_entry->bp.ref_cnt)
|
||||
goto exit;
|
||||
|
||||
/* mark the entry invalid */
|
||||
pd_entry->valid = false;
|
||||
I40E_DEC_PD_REFCNT(pd_table);
|
||||
pd_addr = (u64 *)pd_table->pd_page_addr.va;
|
||||
pd_addr += rel_pd_idx;
|
||||
i40e_memset(pd_addr, 0, sizeof(u64), I40E_DMA_MEM);
|
||||
I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, idx);
|
||||
|
||||
/* free memory here */
|
||||
ret_code = i40e_free_dma_mem(hw, &(pd_entry->bp.addr));
|
||||
if (I40E_SUCCESS != ret_code)
|
||||
goto exit;
|
||||
if (!pd_table->ref_cnt)
|
||||
i40e_free_virt_mem(hw, &pd_table->pd_entry_virt_mem);
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_prep_remove_sd_bp - Prepares to remove a backing page from a sd entry
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: the page index
|
||||
**/
|
||||
enum i40e_status_code i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
|
||||
/* get the entry and decrease its ref counter */
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
I40E_DEC_BP_REFCNT(&sd_entry->u.bp);
|
||||
if (sd_entry->u.bp.ref_cnt) {
|
||||
ret_code = I40E_ERR_NOT_READY;
|
||||
goto exit;
|
||||
}
|
||||
I40E_DEC_SD_REFCNT(&hmc_info->sd_table);
|
||||
|
||||
/* mark the entry invalid */
|
||||
sd_entry->valid = false;
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_remove_sd_bp_new - Removes a backing page from a segment descriptor
|
||||
* @hw: pointer to our hw struct
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: the page index
|
||||
* @is_pf: used to distinguish between VF and PF
|
||||
**/
|
||||
enum i40e_status_code i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
{
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
|
||||
/* get the entry and decrease its ref counter */
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
if (is_pf) {
|
||||
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_DIRECT);
|
||||
} else {
|
||||
ret_code = I40E_NOT_SUPPORTED;
|
||||
goto exit;
|
||||
}
|
||||
ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.bp.addr));
|
||||
if (I40E_SUCCESS != ret_code)
|
||||
goto exit;
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_prep_remove_pd_page - Prepares to remove a PD page from sd entry.
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: segment descriptor index to find the relevant page descriptor
|
||||
**/
|
||||
enum i40e_status_code i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
|
||||
if (sd_entry->u.pd_table.ref_cnt) {
|
||||
ret_code = I40E_ERR_NOT_READY;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* mark the entry invalid */
|
||||
sd_entry->valid = false;
|
||||
|
||||
I40E_DEC_SD_REFCNT(&hmc_info->sd_table);
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_remove_pd_page_new - Removes a PD page from sd entry.
|
||||
* @hw: pointer to our hw struct
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @idx: segment descriptor index to find the relevant page descriptor
|
||||
* @is_pf: used to distinguish between VF and PF
|
||||
**/
|
||||
enum i40e_status_code i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
struct i40e_hmc_sd_entry *sd_entry;
|
||||
|
||||
sd_entry = &hmc_info->sd_table.sd_entry[idx];
|
||||
if (is_pf) {
|
||||
I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_PAGED);
|
||||
} else {
|
||||
ret_code = I40E_NOT_SUPPORTED;
|
||||
goto exit;
|
||||
}
|
||||
/* free memory here */
|
||||
ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.pd_table.pd_page_addr));
|
||||
if (I40E_SUCCESS != ret_code)
|
||||
goto exit;
|
||||
exit:
|
||||
return ret_code;
|
||||
}
|
||||
244
lib/librte_pmd_i40e/i40e/i40e_hmc.h
Normal file
244
lib/librte_pmd_i40e/i40e/i40e_hmc.h
Normal file
@ -0,0 +1,244 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_HMC_H_
|
||||
#define _I40E_HMC_H_
|
||||
|
||||
#define I40E_HMC_MAX_BP_COUNT 512
|
||||
|
||||
/* forward-declare the HW struct for the compiler */
|
||||
struct i40e_hw;
|
||||
enum i40e_status_code;
|
||||
|
||||
#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
|
||||
#define I40E_HMC_PD_CNT_IN_SD 512
|
||||
#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
|
||||
#define I40E_HMC_PAGED_BP_SIZE 4096
|
||||
#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
|
||||
#define I40E_FIRST_VF_FPM_ID 16
|
||||
|
||||
struct i40e_hmc_obj_info {
|
||||
u64 base; /* base addr in FPM */
|
||||
u32 max_cnt; /* max count available for this hmc func */
|
||||
u32 cnt; /* count of objects driver actually wants to create */
|
||||
u64 size; /* size in bytes of one object */
|
||||
};
|
||||
|
||||
enum i40e_sd_entry_type {
|
||||
I40E_SD_TYPE_INVALID = 0,
|
||||
I40E_SD_TYPE_PAGED = 1,
|
||||
I40E_SD_TYPE_DIRECT = 2
|
||||
};
|
||||
|
||||
struct i40e_hmc_bp {
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
struct i40e_dma_mem addr; /* populate to be used by hw */
|
||||
u32 sd_pd_index;
|
||||
u32 ref_cnt;
|
||||
};
|
||||
|
||||
struct i40e_hmc_pd_entry {
|
||||
struct i40e_hmc_bp bp;
|
||||
u32 sd_index;
|
||||
bool valid;
|
||||
};
|
||||
|
||||
struct i40e_hmc_pd_table {
|
||||
struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */
|
||||
struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */
|
||||
struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */
|
||||
|
||||
u32 ref_cnt;
|
||||
u32 sd_index;
|
||||
};
|
||||
|
||||
struct i40e_hmc_sd_entry {
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
bool valid;
|
||||
|
||||
union {
|
||||
struct i40e_hmc_pd_table pd_table;
|
||||
struct i40e_hmc_bp bp;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct i40e_hmc_sd_table {
|
||||
struct i40e_virt_mem addr; /* used to track sd_entry allocations */
|
||||
u32 sd_cnt;
|
||||
u32 ref_cnt;
|
||||
struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */
|
||||
};
|
||||
|
||||
struct i40e_hmc_info {
|
||||
u32 signature;
|
||||
/* equals to pci func num for PF and dynamically allocated for VFs */
|
||||
u8 hmc_fn_id;
|
||||
u16 first_sd_index; /* index of the first available SD */
|
||||
|
||||
/* hmc objects */
|
||||
struct i40e_hmc_obj_info *hmc_obj;
|
||||
struct i40e_virt_mem hmc_obj_virt_mem;
|
||||
struct i40e_hmc_sd_table sd_table;
|
||||
};
|
||||
|
||||
#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
|
||||
#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
|
||||
#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
|
||||
|
||||
#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
|
||||
#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
|
||||
#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
|
||||
|
||||
/**
|
||||
* I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @pa: pointer to physical address
|
||||
* @sd_index: segment descriptor index
|
||||
* @type: if sd entry is direct or paged
|
||||
**/
|
||||
#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
|
||||
{ \
|
||||
u32 val1, val2, val3; \
|
||||
val1 = (u32)(I40E_HI_DWORD(pa)); \
|
||||
val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
|
||||
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
|
||||
(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
|
||||
val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
|
||||
wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
|
||||
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
|
||||
wr32((hw), I40E_PFHMC_SDCMD, val3); \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @sd_index: segment descriptor index
|
||||
* @type: if sd entry is direct or paged
|
||||
**/
|
||||
#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
|
||||
{ \
|
||||
u32 val2, val3; \
|
||||
val2 = (I40E_HMC_MAX_BP_COUNT << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
|
||||
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
|
||||
val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
|
||||
wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
|
||||
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
|
||||
wr32((hw), I40E_PFHMC_SDCMD, val3); \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @sd_idx: segment descriptor index
|
||||
* @pd_idx: page descriptor index
|
||||
**/
|
||||
#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
|
||||
wr32((hw), I40E_PFHMC_PDINV, \
|
||||
(((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
|
||||
((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
|
||||
|
||||
/**
|
||||
* I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @type: type of HMC resources we're searching
|
||||
* @index: starting index for the object
|
||||
* @cnt: number of objects we're trying to create
|
||||
* @sd_idx: pointer to return index of the segment descriptor in question
|
||||
* @sd_limit: pointer to return the maximum number of segment descriptors
|
||||
*
|
||||
* This function calculates the segment descriptor index and index limit
|
||||
* for the resource defined by i40e_hmc_rsrc_type.
|
||||
**/
|
||||
#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
|
||||
{ \
|
||||
u64 fpm_addr, fpm_limit; \
|
||||
fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
|
||||
(hmc_info)->hmc_obj[(type)].size * (index); \
|
||||
fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
|
||||
*(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \
|
||||
*(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \
|
||||
/* add one more to the limit to correct our range */ \
|
||||
*(sd_limit) += 1; \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
|
||||
* @hmc_info: pointer to the HMC configuration information struct
|
||||
* @type: HMC resource type we're examining
|
||||
* @idx: starting index for the object
|
||||
* @cnt: number of objects we're trying to create
|
||||
* @pd_index: pointer to return page descriptor index
|
||||
* @pd_limit: pointer to return page descriptor index limit
|
||||
*
|
||||
* Calculates the page descriptor index and index limit for the resource
|
||||
* defined by i40e_hmc_rsrc_type.
|
||||
**/
|
||||
#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
|
||||
{ \
|
||||
u64 fpm_adr, fpm_limit; \
|
||||
fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
|
||||
(hmc_info)->hmc_obj[(type)].size * (idx); \
|
||||
fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
|
||||
*(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \
|
||||
*(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \
|
||||
/* add one more to the limit to correct our range */ \
|
||||
*(pd_limit) += 1; \
|
||||
}
|
||||
enum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz);
|
||||
|
||||
enum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index);
|
||||
enum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
enum i40e_status_code i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
enum i40e_status_code i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
enum i40e_status_code i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
enum i40e_status_code i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
|
||||
#endif /* _I40E_HMC_H_ */
|
||||
1616
lib/librte_pmd_i40e/i40e/i40e_lan_hmc.c
Normal file
1616
lib/librte_pmd_i40e/i40e/i40e_lan_hmc.c
Normal file
File diff suppressed because it is too large
Load Diff
214
lib/librte_pmd_i40e/i40e/i40e_lan_hmc.h
Normal file
214
lib/librte_pmd_i40e/i40e/i40e_lan_hmc.h
Normal file
@ -0,0 +1,214 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_LAN_HMC_H_
|
||||
#define _I40E_LAN_HMC_H_
|
||||
|
||||
/* forward-declare the HW struct for the compiler */
|
||||
struct i40e_hw;
|
||||
enum i40e_status_code;
|
||||
|
||||
/* HMC element context information */
|
||||
|
||||
/* Rx queue context data
|
||||
*
|
||||
* The sizes of the variables may be larger than needed due to crossing byte
|
||||
* boundaries. If we do not have the width of the variable set to the correct
|
||||
* size then we could end up shifting bits off the top of the variable when the
|
||||
* variable is at the top of a byte and crosses over into the next byte.
|
||||
*/
|
||||
struct i40e_hmc_obj_rxq {
|
||||
u16 head;
|
||||
u16 cpuid; /* bigger than needed, see above for reason */
|
||||
u64 base;
|
||||
u16 qlen;
|
||||
#define I40E_RXQ_CTX_DBUFF_SHIFT 7
|
||||
u16 dbuff; /* bigger than needed, see above for reason */
|
||||
#define I40E_RXQ_CTX_HBUFF_SHIFT 6
|
||||
u16 hbuff; /* bigger than needed, see above for reason */
|
||||
u8 dtype;
|
||||
u8 dsize;
|
||||
u8 crcstrip;
|
||||
u8 fc_ena;
|
||||
u8 l2tsel;
|
||||
u8 hsplit_0;
|
||||
u8 hsplit_1;
|
||||
u8 showiv;
|
||||
u32 rxmax; /* bigger than needed, see above for reason */
|
||||
u8 tphrdesc_ena;
|
||||
u8 tphwdesc_ena;
|
||||
u8 tphdata_ena;
|
||||
u8 tphhead_ena;
|
||||
u16 lrxqthresh; /* bigger than needed, see above for reason */
|
||||
u8 prefena; /* NOTE: normally must be set to 1 at init */
|
||||
};
|
||||
|
||||
/* Tx queue context data
|
||||
*
|
||||
* The sizes of the variables may be larger than needed due to crossing byte
|
||||
* boundaries. If we do not have the width of the variable set to the correct
|
||||
* size then we could end up shifting bits off the top of the variable when the
|
||||
* variable is at the top of a byte and crosses over into the next byte.
|
||||
*/
|
||||
struct i40e_hmc_obj_txq {
|
||||
u16 head;
|
||||
u8 new_context;
|
||||
u64 base;
|
||||
u8 fc_ena;
|
||||
u8 timesync_ena;
|
||||
u8 fd_ena;
|
||||
u8 alt_vlan_ena;
|
||||
u16 thead_wb;
|
||||
u8 cpuid;
|
||||
u8 head_wb_ena;
|
||||
u16 qlen;
|
||||
u8 tphrdesc_ena;
|
||||
u8 tphrpacket_ena;
|
||||
u8 tphwdesc_ena;
|
||||
u64 head_wb_addr;
|
||||
u32 crc;
|
||||
u16 rdylist;
|
||||
u8 rdylist_act;
|
||||
};
|
||||
|
||||
/* for hsplit_0 field of Rx HMC context */
|
||||
enum i40e_hmc_obj_rx_hsplit_0 {
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
|
||||
};
|
||||
|
||||
/* fcoe_cntx and fcoe_filt are for debugging purpose only */
|
||||
struct i40e_hmc_obj_fcoe_cntx {
|
||||
u32 rsv[32];
|
||||
};
|
||||
|
||||
struct i40e_hmc_obj_fcoe_filt {
|
||||
u32 rsv[8];
|
||||
};
|
||||
|
||||
/* Context sizes for LAN objects */
|
||||
enum i40e_hmc_lan_object_size {
|
||||
I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
|
||||
I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
|
||||
I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
|
||||
I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
|
||||
I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
|
||||
I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
|
||||
I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
|
||||
};
|
||||
|
||||
#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
|
||||
#define I40E_HMC_OBJ_SIZE_TXQ 128
|
||||
#define I40E_HMC_OBJ_SIZE_RXQ 32
|
||||
#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 64
|
||||
#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64
|
||||
|
||||
enum i40e_hmc_lan_rsrc_type {
|
||||
I40E_HMC_LAN_FULL = 0,
|
||||
I40E_HMC_LAN_TX = 1,
|
||||
I40E_HMC_LAN_RX = 2,
|
||||
I40E_HMC_FCOE_CTX = 3,
|
||||
I40E_HMC_FCOE_FILT = 4,
|
||||
I40E_HMC_LAN_MAX = 5
|
||||
};
|
||||
|
||||
enum i40e_hmc_model {
|
||||
I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
|
||||
I40E_HMC_MODEL_DIRECT_ONLY = 1,
|
||||
I40E_HMC_MODEL_PAGED_ONLY = 2,
|
||||
I40E_HMC_MODEL_UNKNOWN,
|
||||
};
|
||||
|
||||
struct i40e_hmc_lan_create_obj_info {
|
||||
struct i40e_hmc_info *hmc_info;
|
||||
u32 rsrc_type;
|
||||
u32 start_idx;
|
||||
u32 count;
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
u64 direct_mode_sz;
|
||||
};
|
||||
|
||||
struct i40e_hmc_lan_delete_obj_info {
|
||||
struct i40e_hmc_info *hmc_info;
|
||||
u32 rsrc_type;
|
||||
u32 start_idx;
|
||||
u32 count;
|
||||
};
|
||||
|
||||
enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num);
|
||||
enum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model);
|
||||
enum i40e_status_code i40e_shutdown_lan_hmc(struct i40e_hw *hw);
|
||||
|
||||
u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
|
||||
u32 fcoe_cntx_num, u32 fcoe_filt_num);
|
||||
enum i40e_status_code i40e_get_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
enum i40e_status_code i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
enum i40e_status_code i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
enum i40e_status_code i40e_get_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
enum i40e_status_code i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
enum i40e_status_code i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
#ifdef PREBOOT_SUPPORT
|
||||
|
||||
enum i40e_status_code i40e_clear_lan_tx_queue_context_directly(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
enum i40e_status_code i40e_set_lan_tx_queue_context_directly(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
enum i40e_status_code i40e_clear_lan_rx_queue_context_directly(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
enum i40e_status_code i40e_set_lan_rx_queue_context_directly(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
#endif
|
||||
enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_create_obj_info *info);
|
||||
enum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw,
|
||||
struct i40e_hmc_lan_delete_obj_info *info);
|
||||
|
||||
#endif /* _I40E_LAN_HMC_H_ */
|
||||
942
lib/librte_pmd_i40e/i40e/i40e_nvm.c
Normal file
942
lib/librte_pmd_i40e/i40e/i40e_nvm.c
Normal file
@ -0,0 +1,942 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "i40e_prototype.h"
|
||||
|
||||
/**
|
||||
* i40e_init_nvm_ops - Initialize NVM function pointers
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Setup the function pointers and the NVM info structure. Should be called
|
||||
* once per NVM initialization, e.g. inside the i40e_init_shared_code().
|
||||
* Please notice that the NVM term is used here (& in all methods covered
|
||||
* in this file) as an equivalent of the FLASH part mapped into the SR.
|
||||
* We are accessing FLASH always thru the Shadow RAM.
|
||||
**/
|
||||
enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
|
||||
{
|
||||
struct i40e_nvm_info *nvm = &hw->nvm;
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u32 fla, gens;
|
||||
u8 sr_size;
|
||||
|
||||
DEBUGFUNC("i40e_init_nvm");
|
||||
|
||||
/* The SR size is stored regardless of the nvm programming mode
|
||||
* as the blank mode may be used in the factory line.
|
||||
*/
|
||||
gens = rd32(hw, I40E_GLNVM_GENS);
|
||||
sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
|
||||
I40E_GLNVM_GENS_SR_SIZE_SHIFT);
|
||||
/* Switching to words (sr_size contains power of 2KB) */
|
||||
nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
|
||||
|
||||
/* Check if we are in the normal or blank NVM programming mode */
|
||||
fla = rd32(hw, I40E_GLNVM_FLA);
|
||||
if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
|
||||
/* Max NVM timeout */
|
||||
nvm->timeout = I40E_MAX_NVM_TIMEOUT;
|
||||
nvm->blank_nvm_mode = false;
|
||||
} else { /* Blank programming mode */
|
||||
nvm->blank_nvm_mode = true;
|
||||
ret_code = I40E_ERR_NVM_BLANK_MODE;
|
||||
DEBUGOUT("NVM init error: unsupported blank mode.\n");
|
||||
}
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_acquire_nvm - Generic request for acquiring the NVM ownership
|
||||
* @hw: pointer to the HW structure
|
||||
* @access: NVM access type (read or write)
|
||||
*
|
||||
* This function will request NVM ownership for reading
|
||||
* via the proper Admin Command.
|
||||
**/
|
||||
enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u64 gtime, timeout;
|
||||
u64 time = 0;
|
||||
|
||||
DEBUGFUNC("i40e_acquire_nvm");
|
||||
|
||||
if (hw->nvm.blank_nvm_mode)
|
||||
goto i40e_i40e_acquire_nvm_exit;
|
||||
|
||||
ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
|
||||
0, &time, NULL);
|
||||
/* Reading the Global Device Timer */
|
||||
gtime = rd32(hw, I40E_GLVFGEN_TIMER);
|
||||
|
||||
/* Store the timeout */
|
||||
hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime;
|
||||
|
||||
if (ret_code != I40E_SUCCESS) {
|
||||
/* Set the polling timeout */
|
||||
if (time > I40E_MAX_NVM_TIMEOUT)
|
||||
timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT)
|
||||
+ gtime;
|
||||
else
|
||||
timeout = hw->nvm.hw_semaphore_timeout;
|
||||
/* Poll until the current NVM owner timeouts */
|
||||
while (gtime < timeout) {
|
||||
i40e_msec_delay(10);
|
||||
ret_code = i40e_aq_request_resource(hw,
|
||||
I40E_NVM_RESOURCE_ID,
|
||||
access, 0, &time,
|
||||
NULL);
|
||||
if (ret_code == I40E_SUCCESS) {
|
||||
hw->nvm.hw_semaphore_timeout =
|
||||
I40E_MS_TO_GTIME(time) + gtime;
|
||||
break;
|
||||
}
|
||||
gtime = rd32(hw, I40E_GLVFGEN_TIMER);
|
||||
}
|
||||
if (ret_code != I40E_SUCCESS) {
|
||||
hw->nvm.hw_semaphore_timeout = 0;
|
||||
hw->nvm.hw_semaphore_wait =
|
||||
I40E_MS_TO_GTIME(time) + gtime;
|
||||
DEBUGOUT1("NVM acquire timed out, wait %llu ms before trying again.\n",
|
||||
time);
|
||||
}
|
||||
}
|
||||
|
||||
i40e_i40e_acquire_nvm_exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_release_nvm - Generic request for releasing the NVM ownership
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* This function will release NVM resource via the proper Admin Command.
|
||||
**/
|
||||
void i40e_release_nvm(struct i40e_hw *hw)
|
||||
{
|
||||
DEBUGFUNC("i40e_release_nvm");
|
||||
|
||||
if (!hw->nvm.blank_nvm_mode)
|
||||
i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Polls the SRCTL Shadow RAM register done bit.
|
||||
**/
|
||||
static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
|
||||
u32 srctl, wait_cnt;
|
||||
|
||||
DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
|
||||
|
||||
/* Poll the I40E_GLNVM_SRCTL until the done bit is set */
|
||||
for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
|
||||
srctl = rd32(hw, I40E_GLNVM_SRCTL);
|
||||
if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
|
||||
ret_code = I40E_SUCCESS;
|
||||
break;
|
||||
}
|
||||
i40e_usec_delay(5);
|
||||
}
|
||||
if (ret_code == I40E_ERR_TIMEOUT)
|
||||
DEBUGOUT("Done bit in GLNVM_SRCTL not set");
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_read_nvm_word - Reads Shadow RAM
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
|
||||
* @data: word read from the Shadow RAM
|
||||
*
|
||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
|
||||
**/
|
||||
enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
|
||||
u32 sr_reg;
|
||||
|
||||
DEBUGFUNC("i40e_read_nvm_srctl");
|
||||
|
||||
if (offset >= hw->nvm.sr_size) {
|
||||
DEBUGOUT("NVM read error: Offset beyond Shadow RAM limit.\n");
|
||||
ret_code = I40E_ERR_PARAM;
|
||||
goto read_nvm_exit;
|
||||
}
|
||||
|
||||
/* Poll the done bit first */
|
||||
ret_code = i40e_poll_sr_srctl_done_bit(hw);
|
||||
if (ret_code == I40E_SUCCESS) {
|
||||
/* Write the address and start reading */
|
||||
sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
|
||||
(1 << I40E_GLNVM_SRCTL_START_SHIFT);
|
||||
wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
|
||||
|
||||
/* Poll I40E_GLNVM_SRCTL until the done bit is set */
|
||||
ret_code = i40e_poll_sr_srctl_done_bit(hw);
|
||||
if (ret_code == I40E_SUCCESS) {
|
||||
sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
|
||||
*data = (u16)((sr_reg &
|
||||
I40E_GLNVM_SRDATA_RDDATA_MASK)
|
||||
>> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
|
||||
}
|
||||
}
|
||||
if (ret_code != I40E_SUCCESS)
|
||||
DEBUGOUT1("NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
|
||||
offset);
|
||||
|
||||
read_nvm_exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_read_nvm_buffer - Reads Shadow RAM buffer
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
|
||||
* @words: (in) number of words to read; (out) number of words actually read
|
||||
* @data: words read from the Shadow RAM
|
||||
*
|
||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
|
||||
* method. The buffer read is preceded by the NVM ownership take
|
||||
* and followed by the release.
|
||||
**/
|
||||
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u16 index, word;
|
||||
|
||||
DEBUGFUNC("i40e_read_nvm_buffer");
|
||||
|
||||
/* Loop thru the selected region */
|
||||
for (word = 0; word < *words; word++) {
|
||||
index = offset + word;
|
||||
ret_code = i40e_read_nvm_word(hw, index, &data[word]);
|
||||
if (ret_code != I40E_SUCCESS)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the number of words read from the Shadow RAM */
|
||||
*words = word;
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
/**
|
||||
* i40e_write_nvm_aq - Writes Shadow RAM.
|
||||
* @hw: pointer to the HW structure.
|
||||
* @module_pointer: module pointer location in words from the NVM beginning
|
||||
* @offset: offset in words from module start
|
||||
* @words: number of words to write
|
||||
* @data: buffer with words to write to the Shadow RAM
|
||||
* @last_command: tells the AdminQ that this is the last command
|
||||
*
|
||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
|
||||
**/
|
||||
enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 words, void *data,
|
||||
bool last_command)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_ERR_NVM;
|
||||
|
||||
DEBUGFUNC("i40e_write_nvm_aq");
|
||||
|
||||
/* Here we are checking the SR limit only for the flat memory model.
|
||||
* We cannot do it for the module-based model, as we did not acquire
|
||||
* the NVM resource yet (we cannot get the module pointer value).
|
||||
* Firmware will check the module-based model.
|
||||
*/
|
||||
if ((offset + words) > hw->nvm.sr_size)
|
||||
DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
|
||||
else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
|
||||
/* We can write only up to 4KB (one sector), in one AQ write */
|
||||
DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
|
||||
else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
|
||||
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
|
||||
/* A single write cannot spread over two sectors */
|
||||
DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
|
||||
else
|
||||
ret_code = i40e_aq_update_nvm(hw, module_pointer,
|
||||
2 * offset, /*bytes*/
|
||||
2 * words, /*bytes*/
|
||||
data, last_command, NULL);
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_write_nvm_word - Writes Shadow RAM word
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset of the Shadow RAM word to write
|
||||
* @data: word to write to the Shadow RAM
|
||||
*
|
||||
* Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
|
||||
* NVM ownership have to be acquired and released (on ARQ completion event
|
||||
* reception) by caller. To commit SR to NVM update checksum function
|
||||
* should be called.
|
||||
**/
|
||||
enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
|
||||
void *data)
|
||||
{
|
||||
DEBUGFUNC("i40e_write_nvm_word");
|
||||
|
||||
/* Value 0x00 below means that we treat SR as a flat mem */
|
||||
return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_write_nvm_buffer - Writes Shadow RAM buffer
|
||||
* @hw: pointer to the HW structure
|
||||
* @module_pointer: module pointer location in words from the NVM beginning
|
||||
* @offset: offset of the Shadow RAM buffer to write
|
||||
* @words: number of words to write
|
||||
* @data: words to write to the Shadow RAM
|
||||
*
|
||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
|
||||
* NVM ownership must be acquired before calling this function and released
|
||||
* on ARQ completion event reception by caller. To commit SR to NVM update
|
||||
* checksum function should be called.
|
||||
**/
|
||||
enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
|
||||
u8 module_pointer, u32 offset,
|
||||
u16 words, void *data)
|
||||
{
|
||||
DEBUGFUNC("i40e_write_nvm_buffer");
|
||||
|
||||
/* Here we will only write one buffer as the size of the modules
|
||||
* mirrored in the Shadow RAM is always less than 4K.
|
||||
*/
|
||||
return i40e_write_nvm_aq(hw, module_pointer, offset, words,
|
||||
data, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_calc_nvm_checksum - Calculates and returns the checksum
|
||||
* @hw: pointer to hardware structure
|
||||
* @checksum: pointer to the checksum
|
||||
*
|
||||
* This function calculates SW Checksum that covers the whole 64kB shadow RAM
|
||||
* except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
|
||||
* is customer specific and unknown. Therefore, this function skips all maximum
|
||||
* possible size of VPD (1kB).
|
||||
**/
|
||||
enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u16 pcie_alt_module = 0;
|
||||
u16 checksum_local = 0;
|
||||
u16 vpd_module = 0;
|
||||
u16 word = 0;
|
||||
u32 i = 0;
|
||||
|
||||
DEBUGFUNC("i40e_calc_nvm_checksum");
|
||||
|
||||
/* read pointer to VPD area */
|
||||
ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
|
||||
if (ret_code != I40E_SUCCESS) {
|
||||
ret_code = I40E_ERR_NVM_CHECKSUM;
|
||||
goto i40e_calc_nvm_checksum_exit;
|
||||
}
|
||||
|
||||
/* read pointer to PCIe Alt Auto-load module */
|
||||
ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
|
||||
&pcie_alt_module);
|
||||
if (ret_code != I40E_SUCCESS) {
|
||||
ret_code = I40E_ERR_NVM_CHECKSUM;
|
||||
goto i40e_calc_nvm_checksum_exit;
|
||||
}
|
||||
|
||||
/* Calculate SW checksum that covers the whole 64kB shadow RAM
|
||||
* except the VPD and PCIe ALT Auto-load modules
|
||||
*/
|
||||
for (i = 0; i < hw->nvm.sr_size; i++) {
|
||||
/* Skip Checksum word */
|
||||
if (i == I40E_SR_SW_CHECKSUM_WORD)
|
||||
i++;
|
||||
/* Skip VPD module (convert byte size to word count) */
|
||||
if (i == (u32)vpd_module) {
|
||||
i += (I40E_SR_VPD_MODULE_MAX_SIZE / 2);
|
||||
if (i >= hw->nvm.sr_size)
|
||||
break;
|
||||
}
|
||||
/* Skip PCIe ALT module (convert byte size to word count) */
|
||||
if (i == (u32)pcie_alt_module) {
|
||||
i += (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2);
|
||||
if (i >= hw->nvm.sr_size)
|
||||
break;
|
||||
}
|
||||
|
||||
ret_code = i40e_read_nvm_word(hw, (u16)i, &word);
|
||||
if (ret_code != I40E_SUCCESS) {
|
||||
ret_code = I40E_ERR_NVM_CHECKSUM;
|
||||
goto i40e_calc_nvm_checksum_exit;
|
||||
}
|
||||
checksum_local += word;
|
||||
}
|
||||
|
||||
*checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
|
||||
|
||||
i40e_calc_nvm_checksum_exit:
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_update_nvm_checksum - Updates the NVM checksum
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* NVM ownership must be acquired before calling this function and released
|
||||
* on ARQ completion event reception by caller.
|
||||
* This function will commit SR to NVM.
|
||||
**/
|
||||
enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u16 checksum;
|
||||
|
||||
DEBUGFUNC("i40e_update_nvm_checksum");
|
||||
|
||||
ret_code = i40e_calc_nvm_checksum(hw, &checksum);
|
||||
if (ret_code == I40E_SUCCESS)
|
||||
ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
|
||||
1, &checksum, true);
|
||||
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_validate_nvm_checksum - Validate EEPROM checksum
|
||||
* @hw: pointer to hardware structure
|
||||
* @checksum: calculated checksum
|
||||
*
|
||||
* Performs checksum calculation and validates the NVM SW checksum. If the
|
||||
* caller does not need checksum, the value can be NULL.
|
||||
**/
|
||||
enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum)
|
||||
{
|
||||
enum i40e_status_code ret_code = I40E_SUCCESS;
|
||||
u16 checksum_sr = 0;
|
||||
u16 checksum_local = 0;
|
||||
|
||||
DEBUGFUNC("i40e_validate_nvm_checksum");
|
||||
|
||||
ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
|
||||
if (ret_code != I40E_SUCCESS)
|
||||
goto i40e_validate_nvm_checksum_exit;
|
||||
|
||||
/* Do not use i40e_read_nvm_word() because we do not want to take
|
||||
* the synchronization semaphores twice here.
|
||||
*/
|
||||
i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
|
||||
|
||||
/* Verify read checksum from EEPROM is the same as
|
||||
* calculated checksum
|
||||
*/
|
||||
if (checksum_local != checksum_sr)
|
||||
ret_code = I40E_ERR_NVM_CHECKSUM;
|
||||
|
||||
/* If the user cares, return the calculated checksum */
|
||||
if (checksum)
|
||||
*checksum = checksum_local;
|
||||
|
||||
i40e_validate_nvm_checksum_exit:
|
||||
return ret_code;
|
||||
}
|
||||
#ifdef I40E_NVMUPD_SUPPORT
|
||||
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *errno);
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *errno);
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno);
|
||||
STATIC inline u8 i40e_nvmupd_get_module(u32 val)
|
||||
{
|
||||
return (u8)(val & I40E_NVM_MOD_PNT_MASK);
|
||||
}
|
||||
STATIC inline u8 i40e_nvmupd_get_transaction(u32 val)
|
||||
{
|
||||
return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_command - Process an NVM update command
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* Dispatches command depending on what update state is current
|
||||
**/
|
||||
enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status;
|
||||
|
||||
DEBUGFUNC("i40e_nvmupd_command");
|
||||
|
||||
/* assume success */
|
||||
*errno = 0;
|
||||
|
||||
switch (hw->nvmupd_state) {
|
||||
case I40E_NVMUPD_STATE_INIT:
|
||||
status = i40e_nvmupd_state_init(hw, cmd, bytes, errno);
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_STATE_READING:
|
||||
status = i40e_nvmupd_state_reading(hw, cmd, bytes, errno);
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_STATE_WRITING:
|
||||
status = i40e_nvmupd_state_writing(hw, cmd, bytes, errno);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* invalid state, should never happen */
|
||||
status = I40E_NOT_SUPPORTED;
|
||||
*errno = -ESRCH;
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_state_init - Handle NVM update state Init
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* Process legitimate commands of the Init state and conditionally set next
|
||||
* state. Reject all other commands.
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status = I40E_SUCCESS;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
|
||||
DEBUGFUNC("i40e_nvmupd_state_init");
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
|
||||
|
||||
switch (upd_cmd) {
|
||||
case I40E_NVMUPD_READ_SA:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
|
||||
i40e_release_nvm(hw);
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_READ_SNT:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_WRITE_ERA:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_nvmupd_nvm_erase(hw, cmd, errno);
|
||||
if (status)
|
||||
i40e_release_nvm(hw);
|
||||
else
|
||||
hw->aq.nvm_release_on_done = true;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_WRITE_SA:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
|
||||
if (status)
|
||||
i40e_release_nvm(hw);
|
||||
else
|
||||
hw->aq.nvm_release_on_done = true;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_WRITE_SNT:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_CSUM_SA:
|
||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
|
||||
if (status) {
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
} else {
|
||||
status = i40e_update_nvm_checksum(hw);
|
||||
if (status) {
|
||||
*errno = hw->aq.asq_last_status ?
|
||||
i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
|
||||
-EIO;
|
||||
i40e_release_nvm(hw);
|
||||
} else {
|
||||
hw->aq.nvm_release_on_done = true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
status = I40E_ERR_NVM;
|
||||
*errno = -ESRCH;
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_state_reading - Handle NVM update state Reading
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* NVM ownership is already held. Process legitimate commands and set any
|
||||
* change in state; reject all other commands.
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
|
||||
DEBUGFUNC("i40e_nvmupd_state_reading");
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
|
||||
|
||||
switch (upd_cmd) {
|
||||
case I40E_NVMUPD_READ_SA:
|
||||
case I40E_NVMUPD_READ_CON:
|
||||
status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_READ_LCB:
|
||||
status = i40e_nvmupd_nvm_read(hw, cmd, bytes, errno);
|
||||
i40e_release_nvm(hw);
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = I40E_NOT_SUPPORTED;
|
||||
*errno = -ESRCH;
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_state_writing - Handle NVM update state Writing
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* NVM ownership is already held. Process legitimate commands and set any
|
||||
* change in state; reject all other commands
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status;
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
|
||||
DEBUGFUNC("i40e_nvmupd_state_writing");
|
||||
|
||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, errno);
|
||||
|
||||
switch (upd_cmd) {
|
||||
case I40E_NVMUPD_WRITE_CON:
|
||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_WRITE_LCB:
|
||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, errno);
|
||||
if (!status) {
|
||||
hw->aq.nvm_release_on_done = true;
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_CSUM_CON:
|
||||
status = i40e_update_nvm_checksum(hw);
|
||||
if (status)
|
||||
*errno = hw->aq.asq_last_status ?
|
||||
i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
|
||||
-EIO;
|
||||
break;
|
||||
|
||||
case I40E_NVMUPD_CSUM_LCB:
|
||||
status = i40e_update_nvm_checksum(hw);
|
||||
if (status) {
|
||||
*errno = hw->aq.asq_last_status ?
|
||||
i40e_aq_rc_to_posix(hw->aq.asq_last_status) :
|
||||
-EIO;
|
||||
} else {
|
||||
hw->aq.nvm_release_on_done = true;
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
status = I40E_NOT_SUPPORTED;
|
||||
*errno = -ESRCH;
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_validate_command - Validate given command
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* Return one of the valid command types or I40E_NVMUPD_INVALID
|
||||
**/
|
||||
STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *errno)
|
||||
{
|
||||
enum i40e_nvmupd_cmd upd_cmd;
|
||||
u8 transaction, module;
|
||||
|
||||
DEBUGFUNC("i40e_nvmupd_validate_command\n");
|
||||
|
||||
/* anything that doesn't match a recognized case is an error */
|
||||
upd_cmd = I40E_NVMUPD_INVALID;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
module = i40e_nvmupd_get_module(cmd->config);
|
||||
|
||||
/* limits on data size */
|
||||
if ((cmd->data_size < 1) ||
|
||||
(cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
|
||||
DEBUGOUT1("i40e_nvmupd_validate_command data_size %d\n",
|
||||
cmd->data_size);
|
||||
*errno = -EFAULT;
|
||||
return I40E_NVMUPD_INVALID;
|
||||
}
|
||||
|
||||
switch (cmd->command) {
|
||||
case I40E_NVM_READ:
|
||||
switch (transaction) {
|
||||
case I40E_NVM_CON:
|
||||
upd_cmd = I40E_NVMUPD_READ_CON;
|
||||
break;
|
||||
case I40E_NVM_SNT:
|
||||
upd_cmd = I40E_NVMUPD_READ_SNT;
|
||||
break;
|
||||
case I40E_NVM_LCB:
|
||||
upd_cmd = I40E_NVMUPD_READ_LCB;
|
||||
break;
|
||||
case I40E_NVM_SA:
|
||||
upd_cmd = I40E_NVMUPD_READ_SA;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case I40E_NVM_WRITE:
|
||||
switch (transaction) {
|
||||
case I40E_NVM_CON:
|
||||
upd_cmd = I40E_NVMUPD_WRITE_CON;
|
||||
break;
|
||||
case I40E_NVM_SNT:
|
||||
upd_cmd = I40E_NVMUPD_WRITE_SNT;
|
||||
break;
|
||||
case I40E_NVM_LCB:
|
||||
upd_cmd = I40E_NVMUPD_WRITE_LCB;
|
||||
break;
|
||||
case I40E_NVM_SA:
|
||||
upd_cmd = I40E_NVMUPD_WRITE_SA;
|
||||
break;
|
||||
case I40E_NVM_ERA:
|
||||
upd_cmd = I40E_NVMUPD_WRITE_ERA;
|
||||
break;
|
||||
case I40E_NVM_CSUM:
|
||||
upd_cmd = I40E_NVMUPD_CSUM_CON;
|
||||
break;
|
||||
case (I40E_NVM_CSUM|I40E_NVM_SA):
|
||||
upd_cmd = I40E_NVMUPD_CSUM_SA;
|
||||
break;
|
||||
case (I40E_NVM_CSUM|I40E_NVM_LCB):
|
||||
upd_cmd = I40E_NVMUPD_CSUM_LCB;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (upd_cmd == I40E_NVMUPD_INVALID) {
|
||||
*errno = -EFAULT;
|
||||
DEBUGOUT2(
|
||||
"i40e_nvmupd_validate_command returns %d errno: %d\n",
|
||||
upd_cmd, *errno);
|
||||
}
|
||||
return upd_cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_nvm_read - Read NVM
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* cmd structure contains identifiers and data buffer
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status;
|
||||
u8 module, transaction;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
module = i40e_nvmupd_get_module(cmd->config);
|
||||
last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
|
||||
DEBUGOUT3("i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
|
||||
module, cmd->offset, cmd->data_size);
|
||||
|
||||
status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
|
||||
bytes, last, NULL);
|
||||
DEBUGOUT1("i40e_nvmupd_nvm_read status %d\n", status);
|
||||
if (status != I40E_SUCCESS)
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_nvm_erase - Erase an NVM module
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* module, offset, data_size and data are in cmd structure
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
int *errno)
|
||||
{
|
||||
enum i40e_status_code status = I40E_SUCCESS;
|
||||
u8 module, transaction;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
module = i40e_nvmupd_get_module(cmd->config);
|
||||
last = (transaction & I40E_NVM_LCB);
|
||||
DEBUGOUT3("i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
|
||||
module, cmd->offset, cmd->data_size);
|
||||
status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
|
||||
last, NULL);
|
||||
DEBUGOUT1("i40e_nvmupd_nvm_erase status %d\n", status);
|
||||
if (status != I40E_SUCCESS)
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_nvmupd_nvm_write - Write NVM
|
||||
* @hw: pointer to hardware structure
|
||||
* @cmd: pointer to nvm update command buffer
|
||||
* @bytes: pointer to the data buffer
|
||||
* @errno: pointer to return error code
|
||||
*
|
||||
* module, offset, data_size and data are in cmd structure
|
||||
**/
|
||||
STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *errno)
|
||||
{
|
||||
enum i40e_status_code status = I40E_SUCCESS;
|
||||
u8 module, transaction;
|
||||
bool last;
|
||||
|
||||
transaction = i40e_nvmupd_get_transaction(cmd->config);
|
||||
module = i40e_nvmupd_get_module(cmd->config);
|
||||
last = (transaction & I40E_NVM_LCB);
|
||||
DEBUGOUT3("i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
|
||||
module, cmd->offset, cmd->data_size);
|
||||
status = i40e_aq_update_nvm(hw, module, cmd->offset,
|
||||
(u16)cmd->data_size, bytes, last, NULL);
|
||||
DEBUGOUT1("i40e_nvmupd_nvm_write status %d\n", status);
|
||||
if (status != I40E_SUCCESS)
|
||||
*errno = i40e_aq_rc_to_posix(hw->aq.asq_last_status);
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
435
lib/librte_pmd_i40e/i40e/i40e_prototype.h
Normal file
435
lib/librte_pmd_i40e/i40e/i40e_prototype.h
Normal file
@ -0,0 +1,435 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_PROTOTYPE_H_
|
||||
#define _I40E_PROTOTYPE_H_
|
||||
|
||||
#include "i40e_type.h"
|
||||
#include "i40e_alloc.h"
|
||||
#include "i40e_virtchnl.h"
|
||||
|
||||
/* Prototypes for shared code functions that are not in
|
||||
* the standard function pointer structures. These are
|
||||
* mostly because they are needed even before the init
|
||||
* has happened and will assist in the early SW and FW
|
||||
* setup.
|
||||
*/
|
||||
|
||||
/* adminq functions */
|
||||
enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_init_asq(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_init_arq(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw);
|
||||
u16 i40e_clean_asq(struct i40e_hw *hw);
|
||||
void i40e_free_adminq_asq(struct i40e_hw *hw);
|
||||
void i40e_free_adminq_arq(struct i40e_hw *hw);
|
||||
void i40e_adminq_init_ring_data(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
|
||||
struct i40e_arq_event_info *e,
|
||||
u16 *events_pending);
|
||||
enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
|
||||
struct i40e_aq_desc *desc,
|
||||
void *buff, /* can be NULL */
|
||||
u16 buff_size,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
bool i40e_asq_done(struct i40e_hw *hw);
|
||||
|
||||
/* debug function for adminq */
|
||||
void i40e_debug_aq(struct i40e_hw *hw,
|
||||
enum i40e_debug_mask mask,
|
||||
void *desc,
|
||||
void *buffer);
|
||||
|
||||
void i40e_idle_aq(struct i40e_hw *hw);
|
||||
void i40e_resume_aq(struct i40e_hw *hw);
|
||||
bool i40e_check_asq_alive(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
|
||||
|
||||
#ifndef VF_DRIVER
|
||||
|
||||
u32 i40e_led_get(struct i40e_hw *hw);
|
||||
void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);
|
||||
|
||||
/* admin send queue commands */
|
||||
|
||||
enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
|
||||
u16 *fw_major_version, u16 *fw_minor_version,
|
||||
u16 *api_major_version, u16 *api_minor_version,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
|
||||
bool qualified_modules, bool report_init,
|
||||
struct i40e_aq_get_phy_abilities_resp *abilities,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
|
||||
struct i40e_aq_set_phy_config *config,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
|
||||
bool atomic_reset);
|
||||
enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
|
||||
u16 max_frame_size, bool crc_en, u16 pacing,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
|
||||
u64 *advt_reg,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
|
||||
u64 *advt_reg,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, u16 lb_modes,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
|
||||
bool enable_link, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
|
||||
bool enable_lse, struct i40e_link_status *link,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw,
|
||||
bool enable_lse);
|
||||
enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
|
||||
u64 advt_reg,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
|
||||
struct i40e_driver_version *dv,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set_filter,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
|
||||
u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_vsi_context *vsi_ctx,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
|
||||
u16 downlink_seid, u8 enabled_tc,
|
||||
bool default_port, bool enable_l2_filtering,
|
||||
u16 *pveb_seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
|
||||
u16 veb_seid, u16 *switch_id, bool *floating,
|
||||
u16 *statistic_index, u16 *vebs_used,
|
||||
u16 *vebs_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_add_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_remove_macvlan_element_data *mv_list,
|
||||
u16 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_add_remove_vlan_element_data *v_list,
|
||||
u8 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 vsi_id,
|
||||
struct i40e_aqc_add_remove_vlan_element_data *v_list,
|
||||
u8 count, struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
|
||||
u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
|
||||
struct i40e_aqc_get_switch_config_resp *buf,
|
||||
u16 buf_size, u16 *start_seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
enum i40e_aq_resource_access_type access,
|
||||
u8 sdp_number, u64 *timeout,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
|
||||
enum i40e_aq_resources_ids resource,
|
||||
u8 sdp_number,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
|
||||
void *buff, u16 buff_size, u16 *data_size,
|
||||
enum i40e_admin_queue_opc list_type_opc,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
|
||||
u8 mib_type, void *buff, u16 buff_size,
|
||||
u16 *local_len, u16 *remote_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
|
||||
bool enable_update,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
|
||||
void *buff, u16 buff_size, u16 tlv_len,
|
||||
u16 *mib_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
|
||||
u8 bridge_type, void *buff, u16 buff_size,
|
||||
u16 old_len, u16 new_len, u16 offset,
|
||||
u16 *mib_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
|
||||
u8 bridge_type, void *buff, u16 buff_size,
|
||||
u16 tlv_len, u16 *mib_len,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
|
||||
u16 udp_port, u8 protocol_index,
|
||||
u8 *filter_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
|
||||
u8 *num_entries,
|
||||
struct i40e_aqc_switch_resource_alloc_element_resp *buf,
|
||||
u16 count,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
|
||||
u16 mac_seid, u16 vsi_seid,
|
||||
u16 *ret_seid);
|
||||
enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
|
||||
u16 vsi_seid, u16 tag, u16 queue_num,
|
||||
u16 *tags_used, u16 *tags_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
|
||||
u16 tag, u16 *tags_used, u16 *tags_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pe_seid,
|
||||
u16 etag, u8 num_tags_in_buf, void *buf,
|
||||
u16 *tags_used, u16 *tags_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pe_seid,
|
||||
u16 etag, u16 *tags_used, u16 *tags_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
|
||||
u16 old_tag, u16 new_tag, u16 *tags_used,
|
||||
u16 *tags_free,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
|
||||
u16 vlan_id, u16 *stat_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
|
||||
u16 vlan_id, u16 stat_index,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
|
||||
u16 bad_frame_vsi, bool save_bad_pac,
|
||||
bool pad_short_pac, bool double_vlan,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
|
||||
u16 flags, u8 *mac_addr,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid, u16 credit, u8 max_credit,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw,
|
||||
u8 tcmap, bool request, u8 *tcmap_ret,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
|
||||
enum i40e_aq_hmc_profile *profile,
|
||||
u8 *pe_vf_enabled_count,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
|
||||
struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
|
||||
enum i40e_aq_hmc_profile profile,
|
||||
u8 pe_vf_enabled_count,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
|
||||
u16 seid, u16 credit, u8 max_bw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_port_ets_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
|
||||
u16 seid,
|
||||
struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
#ifdef I40E_DCB_SW
|
||||
enum i40e_status_code i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,
|
||||
struct i40e_lldp_variables *lldp_cfg);
|
||||
#endif /* I40E_DCB_SW */
|
||||
enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
|
||||
u16 vsi,
|
||||
struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
|
||||
u8 filter_count);
|
||||
|
||||
enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
|
||||
u16 vsi,
|
||||
struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
|
||||
u8 filter_count);
|
||||
|
||||
enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
|
||||
u32 reg_addr0, u32 *reg_val0,
|
||||
u32 reg_addr1, u32 *reg_val1);
|
||||
enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
|
||||
u32 addr, u32 dw_count, void *buffer);
|
||||
enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
|
||||
u32 reg_addr0, u32 reg_val0,
|
||||
u32 reg_addr1, u32 reg_val1);
|
||||
enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
|
||||
u32 addr, u32 dw_count, void *buffer);
|
||||
enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
|
||||
u8 bios_mode, bool *reset_needed);
|
||||
enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
|
||||
u8 oem_mode);
|
||||
|
||||
/* i40e_common */
|
||||
enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw);
|
||||
void i40e_clear_hw(struct i40e_hw *hw);
|
||||
void i40e_clear_pxe_mode(struct i40e_hw *hw);
|
||||
bool i40e_get_link_status(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
|
||||
u32 *max_bw, u32 *min_bw, bool *min_valid, bool *max_valid);
|
||||
enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
|
||||
struct i40e_aqc_configure_partition_bw_data *bw_data,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
|
||||
void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);
|
||||
enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);
|
||||
enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw);
|
||||
/* prototype for functions used for NVM access */
|
||||
enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
|
||||
enum i40e_aq_resource_access_type access);
|
||||
void i40e_release_nvm(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_read_nvm_srrd(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
|
||||
u16 *words, u16 *data);
|
||||
enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module,
|
||||
u32 offset, u16 words, void *data,
|
||||
bool last_command);
|
||||
enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
|
||||
void *data);
|
||||
enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw, u8 module,
|
||||
u32 offset, u16 words, void *data);
|
||||
enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum);
|
||||
enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
||||
u16 *checksum);
|
||||
enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
struct i40e_nvm_access *cmd,
|
||||
u8 *bytes, int *);
|
||||
void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);
|
||||
#endif /* VF_DRIVER */
|
||||
|
||||
#if defined(I40E_QV) || defined(VF_DRIVER)
|
||||
enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw);
|
||||
|
||||
#endif
|
||||
extern struct i40e_rx_ptype_decoded i40e_ptype_lookup[];
|
||||
|
||||
STATIC INLINE struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)
|
||||
{
|
||||
return i40e_ptype_lookup[ptype];
|
||||
}
|
||||
|
||||
/* prototype for functions used for SW spinlocks */
|
||||
void i40e_init_spinlock(struct i40e_spinlock *sp);
|
||||
void i40e_acquire_spinlock(struct i40e_spinlock *sp);
|
||||
void i40e_release_spinlock(struct i40e_spinlock *sp);
|
||||
void i40e_destroy_spinlock(struct i40e_spinlock *sp);
|
||||
|
||||
/* i40e_common for VF drivers*/
|
||||
void i40e_vf_parse_hw_config(struct i40e_hw *hw,
|
||||
struct i40e_virtchnl_vf_resource *msg);
|
||||
enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw);
|
||||
enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
|
||||
enum i40e_virtchnl_ops v_opcode,
|
||||
enum i40e_status_code v_retval,
|
||||
u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
|
||||
struct i40e_filter_control_settings *settings);
|
||||
enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
|
||||
u8 *mac_addr, u16 ethtype, u16 flags,
|
||||
u16 vsi_seid, u16 queue, bool is_add,
|
||||
struct i40e_control_filter_stats *stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
#endif /* _I40E_PROTOTYPE_H_ */
|
||||
3377
lib/librte_pmd_i40e/i40e/i40e_register.h
Normal file
3377
lib/librte_pmd_i40e/i40e/i40e_register.h
Normal file
File diff suppressed because it is too large
Load Diff
10712
lib/librte_pmd_i40e/i40e/i40e_register_x710_int.h
Normal file
10712
lib/librte_pmd_i40e/i40e/i40e_register_x710_int.h
Normal file
File diff suppressed because it is too large
Load Diff
107
lib/librte_pmd_i40e/i40e/i40e_status.h
Normal file
107
lib/librte_pmd_i40e/i40e/i40e_status.h
Normal file
@ -0,0 +1,107 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_STATUS_H_
|
||||
#define _I40E_STATUS_H_
|
||||
|
||||
/* Error Codes */
|
||||
enum i40e_status_code {
|
||||
I40E_SUCCESS = 0,
|
||||
I40E_ERR_NVM = -1,
|
||||
I40E_ERR_NVM_CHECKSUM = -2,
|
||||
I40E_ERR_PHY = -3,
|
||||
I40E_ERR_CONFIG = -4,
|
||||
I40E_ERR_PARAM = -5,
|
||||
I40E_ERR_MAC_TYPE = -6,
|
||||
I40E_ERR_UNKNOWN_PHY = -7,
|
||||
I40E_ERR_LINK_SETUP = -8,
|
||||
I40E_ERR_ADAPTER_STOPPED = -9,
|
||||
I40E_ERR_INVALID_MAC_ADDR = -10,
|
||||
I40E_ERR_DEVICE_NOT_SUPPORTED = -11,
|
||||
I40E_ERR_MASTER_REQUESTS_PENDING = -12,
|
||||
I40E_ERR_INVALID_LINK_SETTINGS = -13,
|
||||
I40E_ERR_AUTONEG_NOT_COMPLETE = -14,
|
||||
I40E_ERR_RESET_FAILED = -15,
|
||||
I40E_ERR_SWFW_SYNC = -16,
|
||||
I40E_ERR_NO_AVAILABLE_VSI = -17,
|
||||
I40E_ERR_NO_MEMORY = -18,
|
||||
I40E_ERR_BAD_PTR = -19,
|
||||
I40E_ERR_RING_FULL = -20,
|
||||
I40E_ERR_INVALID_PD_ID = -21,
|
||||
I40E_ERR_INVALID_QP_ID = -22,
|
||||
I40E_ERR_INVALID_CQ_ID = -23,
|
||||
I40E_ERR_INVALID_CEQ_ID = -24,
|
||||
I40E_ERR_INVALID_AEQ_ID = -25,
|
||||
I40E_ERR_INVALID_SIZE = -26,
|
||||
I40E_ERR_INVALID_ARP_INDEX = -27,
|
||||
I40E_ERR_INVALID_FPM_FUNC_ID = -28,
|
||||
I40E_ERR_QP_INVALID_MSG_SIZE = -29,
|
||||
I40E_ERR_QP_TOOMANY_WRS_POSTED = -30,
|
||||
I40E_ERR_INVALID_FRAG_COUNT = -31,
|
||||
I40E_ERR_QUEUE_EMPTY = -32,
|
||||
I40E_ERR_INVALID_ALIGNMENT = -33,
|
||||
I40E_ERR_FLUSHED_QUEUE = -34,
|
||||
I40E_ERR_INVALID_PUSH_PAGE_INDEX = -35,
|
||||
I40E_ERR_INVALID_IMM_DATA_SIZE = -36,
|
||||
I40E_ERR_TIMEOUT = -37,
|
||||
I40E_ERR_OPCODE_MISMATCH = -38,
|
||||
I40E_ERR_CQP_COMPL_ERROR = -39,
|
||||
I40E_ERR_INVALID_VF_ID = -40,
|
||||
I40E_ERR_INVALID_HMCFN_ID = -41,
|
||||
I40E_ERR_BACKING_PAGE_ERROR = -42,
|
||||
I40E_ERR_NO_PBLCHUNKS_AVAILABLE = -43,
|
||||
I40E_ERR_INVALID_PBLE_INDEX = -44,
|
||||
I40E_ERR_INVALID_SD_INDEX = -45,
|
||||
I40E_ERR_INVALID_PAGE_DESC_INDEX = -46,
|
||||
I40E_ERR_INVALID_SD_TYPE = -47,
|
||||
I40E_ERR_MEMCPY_FAILED = -48,
|
||||
I40E_ERR_INVALID_HMC_OBJ_INDEX = -49,
|
||||
I40E_ERR_INVALID_HMC_OBJ_COUNT = -50,
|
||||
I40E_ERR_INVALID_SRQ_ARM_LIMIT = -51,
|
||||
I40E_ERR_SRQ_ENABLED = -52,
|
||||
I40E_ERR_ADMIN_QUEUE_ERROR = -53,
|
||||
I40E_ERR_ADMIN_QUEUE_TIMEOUT = -54,
|
||||
I40E_ERR_BUF_TOO_SHORT = -55,
|
||||
I40E_ERR_ADMIN_QUEUE_FULL = -56,
|
||||
I40E_ERR_ADMIN_QUEUE_NO_WORK = -57,
|
||||
I40E_ERR_BAD_IWARP_CQE = -58,
|
||||
I40E_ERR_NVM_BLANK_MODE = -59,
|
||||
I40E_ERR_NOT_IMPLEMENTED = -60,
|
||||
I40E_ERR_PE_DOORBELL_NOT_ENABLED = -61,
|
||||
I40E_ERR_DIAG_TEST_FAILED = -62,
|
||||
I40E_ERR_NOT_READY = -63,
|
||||
I40E_NOT_SUPPORTED = -64,
|
||||
I40E_ERR_FIRMWARE_API_VERSION = -65,
|
||||
};
|
||||
|
||||
#endif /* _I40E_STATUS_H_ */
|
||||
1462
lib/librte_pmd_i40e/i40e/i40e_type.h
Normal file
1462
lib/librte_pmd_i40e/i40e/i40e_type.h
Normal file
File diff suppressed because it is too large
Load Diff
373
lib/librte_pmd_i40e/i40e/i40e_virtchnl.h
Normal file
373
lib/librte_pmd_i40e/i40e/i40e_virtchnl.h
Normal file
@ -0,0 +1,373 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _I40E_VIRTCHNL_H_
|
||||
#define _I40E_VIRTCHNL_H_
|
||||
|
||||
#include "i40e_type.h"
|
||||
|
||||
/* Description:
|
||||
* This header file describes the VF-PF communication protocol used
|
||||
* by the various i40e drivers.
|
||||
*
|
||||
* Admin queue buffer usage:
|
||||
* desc->opcode is always i40e_aqc_opc_send_msg_to_pf
|
||||
* flags, retval, datalen, and data addr are all used normally.
|
||||
* Firmware copies the cookie fields when sending messages between the PF and
|
||||
* VF, but uses all other fields internally. Due to this limitation, we
|
||||
* must send all messages as "indirect", i.e. using an external buffer.
|
||||
*
|
||||
* All the vsi indexes are relative to the VF. Each VF can have maximum of
|
||||
* three VSIs. All the queue indexes are relative to the VSI. Each VF can
|
||||
* have a maximum of sixteen queues for all of its VSIs.
|
||||
*
|
||||
* The PF is required to return a status code in v_retval for all messages
|
||||
* except RESET_VF, which does not require any response. The return value is of
|
||||
* i40e_status_code type, defined in the i40e_type.h.
|
||||
*
|
||||
* In general, VF driver initialization should roughly follow the order of these
|
||||
* opcodes. The VF driver must first validate the API version of the PF driver,
|
||||
* then request a reset, then get resources, then configure queues and
|
||||
* interrupts. After these operations are complete, the VF driver may start
|
||||
* its queues, optionally add MAC and VLAN filters, and process traffic.
|
||||
*/
|
||||
|
||||
/* Opcodes for VF-PF communication. These are placed in the v_opcode field
|
||||
* of the virtchnl_msg structure.
|
||||
*/
|
||||
enum i40e_virtchnl_ops {
|
||||
/* VF sends req. to pf for the following
|
||||
* ops.
|
||||
*/
|
||||
I40E_VIRTCHNL_OP_UNKNOWN = 0,
|
||||
I40E_VIRTCHNL_OP_VERSION = 1, /* must ALWAYS be 1 */
|
||||
I40E_VIRTCHNL_OP_RESET_VF,
|
||||
I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
|
||||
I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE,
|
||||
I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE,
|
||||
I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
|
||||
I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
|
||||
I40E_VIRTCHNL_OP_ENABLE_QUEUES,
|
||||
I40E_VIRTCHNL_OP_DISABLE_QUEUES,
|
||||
I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
|
||||
I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
|
||||
I40E_VIRTCHNL_OP_ADD_VLAN,
|
||||
I40E_VIRTCHNL_OP_DEL_VLAN,
|
||||
I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
|
||||
I40E_VIRTCHNL_OP_GET_STATS,
|
||||
I40E_VIRTCHNL_OP_FCOE,
|
||||
/* PF sends status change events to vfs using
|
||||
* the following op.
|
||||
*/
|
||||
I40E_VIRTCHNL_OP_EVENT,
|
||||
};
|
||||
|
||||
/* Virtual channel message descriptor. This overlays the admin queue
|
||||
* descriptor. All other data is passed in external buffers.
|
||||
*/
|
||||
|
||||
struct i40e_virtchnl_msg {
|
||||
u8 pad[8]; /* AQ flags/opcode/len/retval fields */
|
||||
enum i40e_virtchnl_ops v_opcode; /* avoid confusion with desc->opcode */
|
||||
enum i40e_status_code v_retval; /* ditto for desc->retval */
|
||||
u32 vfid; /* used by PF when sending to VF */
|
||||
};
|
||||
|
||||
/* Message descriptions and data structures.*/
|
||||
|
||||
/* I40E_VIRTCHNL_OP_VERSION
|
||||
* VF posts its version number to the PF. PF responds with its version number
|
||||
* in the same format, along with a return code.
|
||||
* Reply from PF has its major/minor versions also in param0 and param1.
|
||||
* If there is a major version mismatch, then the VF cannot operate.
|
||||
* If there is a minor version mismatch, then the VF can operate but should
|
||||
* add a warning to the system log.
|
||||
*
|
||||
* This enum element MUST always be specified as == 1, regardless of other
|
||||
* changes in the API. The PF must always respond to this message without
|
||||
* error regardless of version mismatch.
|
||||
*/
|
||||
#define I40E_VIRTCHNL_VERSION_MAJOR 1
|
||||
#define I40E_VIRTCHNL_VERSION_MINOR 0
|
||||
struct i40e_virtchnl_version_info {
|
||||
u32 major;
|
||||
u32 minor;
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_RESET_VF
|
||||
* VF sends this request to PF with no parameters
|
||||
* PF does NOT respond! VF driver must delay then poll VFGEN_RSTAT register
|
||||
* until reset completion is indicated. The admin queue must be reinitialized
|
||||
* after this operation.
|
||||
*
|
||||
* When reset is complete, PF must ensure that all queues in all VSIs associated
|
||||
* with the VF are stopped, all queue configurations in the HMC are set to 0,
|
||||
* and all MAC and VLAN filters (except the default MAC address) on all VSIs
|
||||
* are cleared.
|
||||
*/
|
||||
|
||||
/* I40E_VIRTCHNL_OP_GET_VF_RESOURCES
|
||||
* VF sends this request to PF with no parameters
|
||||
* PF responds with an indirect message containing
|
||||
* i40e_virtchnl_vf_resource and one or more
|
||||
* i40e_virtchnl_vsi_resource structures.
|
||||
*/
|
||||
|
||||
struct i40e_virtchnl_vsi_resource {
|
||||
u16 vsi_id;
|
||||
u16 num_queue_pairs;
|
||||
enum i40e_vsi_type vsi_type;
|
||||
u16 qset_handle;
|
||||
u8 default_mac_addr[I40E_ETH_LENGTH_OF_ADDRESS];
|
||||
};
|
||||
/* VF offload flags */
|
||||
#define I40E_VIRTCHNL_VF_OFFLOAD_L2 0x00000001
|
||||
#define I40E_VIRTCHNL_VF_OFFLOAD_IWARP 0x00000002
|
||||
#define I40E_VIRTCHNL_VF_OFFLOAD_FCOE 0x00000004
|
||||
#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
|
||||
|
||||
struct i40e_virtchnl_vf_resource {
|
||||
u16 num_vsis;
|
||||
u16 num_queue_pairs;
|
||||
u16 max_vectors;
|
||||
u16 max_mtu;
|
||||
|
||||
u32 vf_offload_flags;
|
||||
u32 max_fcoe_contexts;
|
||||
u32 max_fcoe_filters;
|
||||
|
||||
struct i40e_virtchnl_vsi_resource vsi_res[1];
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE
|
||||
* VF sends this message to set up parameters for one TX queue.
|
||||
* External data buffer contains one instance of i40e_virtchnl_txq_info.
|
||||
* PF configures requested queue and returns a status code.
|
||||
*/
|
||||
|
||||
/* Tx queue config info */
|
||||
struct i40e_virtchnl_txq_info {
|
||||
u16 vsi_id;
|
||||
u16 queue_id;
|
||||
u16 ring_len; /* number of descriptors, multiple of 8 */
|
||||
u16 headwb_enabled;
|
||||
u64 dma_ring_addr;
|
||||
u64 dma_headwb_addr;
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE
|
||||
* VF sends this message to set up parameters for one RX queue.
|
||||
* External data buffer contains one instance of i40e_virtchnl_rxq_info.
|
||||
* PF configures requested queue and returns a status code.
|
||||
*/
|
||||
|
||||
/* Rx queue config info */
|
||||
struct i40e_virtchnl_rxq_info {
|
||||
u16 vsi_id;
|
||||
u16 queue_id;
|
||||
u32 ring_len; /* number of descriptors, multiple of 32 */
|
||||
u16 hdr_size;
|
||||
u16 splithdr_enabled;
|
||||
u32 databuffer_size;
|
||||
u32 max_pkt_size;
|
||||
u64 dma_ring_addr;
|
||||
enum i40e_hmc_obj_rx_hsplit_0 rx_split_pos;
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES
|
||||
* VF sends this message to set parameters for all active TX and RX queues
|
||||
* associated with the specified VSI.
|
||||
* PF configures queues and returns status.
|
||||
* If the number of queues specified is greater than the number of queues
|
||||
* associated with the VSI, an error is returned and no queues are configured.
|
||||
*/
|
||||
struct i40e_virtchnl_queue_pair_info {
|
||||
/* NOTE: vsi_id and queue_id should be identical for both queues. */
|
||||
struct i40e_virtchnl_txq_info txq;
|
||||
struct i40e_virtchnl_rxq_info rxq;
|
||||
};
|
||||
|
||||
struct i40e_virtchnl_vsi_queue_config_info {
|
||||
u16 vsi_id;
|
||||
u16 num_queue_pairs;
|
||||
struct i40e_virtchnl_queue_pair_info qpair[1];
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP
|
||||
* VF uses this message to map vectors to queues.
|
||||
* The rxq_map and txq_map fields are bitmaps used to indicate which queues
|
||||
* are to be associated with the specified vector.
|
||||
* The "other" causes are always mapped to vector 0.
|
||||
* PF configures interrupt mapping and returns status.
|
||||
*/
|
||||
struct i40e_virtchnl_vector_map {
|
||||
u16 vsi_id;
|
||||
u16 vector_id;
|
||||
u16 rxq_map;
|
||||
u16 txq_map;
|
||||
u16 rxitr_idx;
|
||||
u16 txitr_idx;
|
||||
};
|
||||
|
||||
struct i40e_virtchnl_irq_map_info {
|
||||
u16 num_vectors;
|
||||
struct i40e_virtchnl_vector_map vecmap[1];
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_ENABLE_QUEUES
|
||||
* I40E_VIRTCHNL_OP_DISABLE_QUEUES
|
||||
* VF sends these message to enable or disable TX/RX queue pairs.
|
||||
* The queues fields are bitmaps indicating which queues to act upon.
|
||||
* (Currently, we only support 16 queues per VF, but we make the field
|
||||
* u32 to allow for expansion.)
|
||||
* PF performs requested action and returns status.
|
||||
*/
|
||||
struct i40e_virtchnl_queue_select {
|
||||
u16 vsi_id;
|
||||
u16 pad;
|
||||
u32 rx_queues;
|
||||
u32 tx_queues;
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS
|
||||
* VF sends this message in order to add one or more unicast or multicast
|
||||
* address filters for the specified VSI.
|
||||
* PF adds the filters and returns status.
|
||||
*/
|
||||
|
||||
/* I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS
|
||||
* VF sends this message in order to remove one or more unicast or multicast
|
||||
* filters for the specified VSI.
|
||||
* PF removes the filters and returns status.
|
||||
*/
|
||||
|
||||
struct i40e_virtchnl_ether_addr {
|
||||
u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
|
||||
u8 pad[2];
|
||||
};
|
||||
|
||||
struct i40e_virtchnl_ether_addr_list {
|
||||
u16 vsi_id;
|
||||
u16 num_elements;
|
||||
struct i40e_virtchnl_ether_addr list[1];
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_ADD_VLAN
|
||||
* VF sends this message to add one or more VLAN tag filters for receives.
|
||||
* PF adds the filters and returns status.
|
||||
* If a port VLAN is configured by the PF, this operation will return an
|
||||
* error to the VF.
|
||||
*/
|
||||
|
||||
/* I40E_VIRTCHNL_OP_DEL_VLAN
|
||||
* VF sends this message to remove one or more VLAN tag filters for receives.
|
||||
* PF removes the filters and returns status.
|
||||
* If a port VLAN is configured by the PF, this operation will return an
|
||||
* error to the VF.
|
||||
*/
|
||||
|
||||
struct i40e_virtchnl_vlan_filter_list {
|
||||
u16 vsi_id;
|
||||
u16 num_elements;
|
||||
u16 vlan_id[1];
|
||||
};
|
||||
|
||||
/* I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE
|
||||
* VF sends VSI id and flags.
|
||||
* PF returns status code in retval.
|
||||
* Note: we assume that broadcast accept mode is always enabled.
|
||||
*/
|
||||
struct i40e_virtchnl_promisc_info {
|
||||
u16 vsi_id;
|
||||
u16 flags;
|
||||
};
|
||||
|
||||
#define I40E_FLAG_VF_UNICAST_PROMISC 0x00000001
|
||||
#define I40E_FLAG_VF_MULTICAST_PROMISC 0x00000002
|
||||
|
||||
/* I40E_VIRTCHNL_OP_GET_STATS
|
||||
* VF sends this message to request stats for the selected VSI. VF uses
|
||||
* the i40e_virtchnl_queue_select struct to specify the VSI. The queue_id
|
||||
* field is ignored by the PF.
|
||||
*
|
||||
* PF replies with struct i40e_eth_stats in an external buffer.
|
||||
*/
|
||||
|
||||
/* I40E_VIRTCHNL_OP_EVENT
|
||||
* PF sends this message to inform the VF driver of events that may affect it.
|
||||
* No direct response is expected from the VF, though it may generate other
|
||||
* messages in response to this one.
|
||||
*/
|
||||
enum i40e_virtchnl_event_codes {
|
||||
I40E_VIRTCHNL_EVENT_UNKNOWN = 0,
|
||||
I40E_VIRTCHNL_EVENT_LINK_CHANGE,
|
||||
I40E_VIRTCHNL_EVENT_RESET_IMPENDING,
|
||||
I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE,
|
||||
};
|
||||
#define I40E_PF_EVENT_SEVERITY_INFO 0
|
||||
#define I40E_PF_EVENT_SEVERITY_ATTENTION 1
|
||||
#define I40E_PF_EVENT_SEVERITY_ACTION_REQUIRED 2
|
||||
#define I40E_PF_EVENT_SEVERITY_CERTAIN_DOOM 255
|
||||
|
||||
struct i40e_virtchnl_pf_event {
|
||||
enum i40e_virtchnl_event_codes event;
|
||||
union {
|
||||
struct {
|
||||
enum i40e_aq_link_speed link_speed;
|
||||
bool link_status;
|
||||
} link_event;
|
||||
} event_data;
|
||||
|
||||
int severity;
|
||||
};
|
||||
|
||||
/* VF reset states - these are written into the RSTAT register:
|
||||
* I40E_VFGEN_RSTAT1 on the PF
|
||||
* I40E_VFGEN_RSTAT on the VF
|
||||
* When the PF initiates a reset, it writes 0
|
||||
* When the reset is complete, it writes 1
|
||||
* When the PF detects that the VF has recovered, it writes 2
|
||||
* VF checks this register periodically to determine if a reset has occurred,
|
||||
* then polls it to know when the reset is complete.
|
||||
* If either the PF or VF reads the register while the hardware
|
||||
* is in a reset state, it will return DEADBEEF, which, when masked
|
||||
* will result in 3.
|
||||
*/
|
||||
enum i40e_vfr_states {
|
||||
I40E_VFR_INPROGRESS = 0,
|
||||
I40E_VFR_COMPLETED,
|
||||
I40E_VFR_VFACTIVE,
|
||||
I40E_VFR_UNKNOWN,
|
||||
};
|
||||
|
||||
#endif /* _I40E_VIRTCHNL_H_ */
|
||||
Loading…
Reference in New Issue
Block a user