net/txgbe: add module identify
Add sfp anf qsfp module identify, i2c start and stop. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Jiawen Wu
Ferruh Yigit
parent
5364a1ce30
commit
8f09fb4642
@ -23,6 +23,7 @@
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#define TXGBE_EEPROM_VERSION_H 0x1E
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#define TXGBE_ISCSI_BOOT_CONFIG 0x07
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#define TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
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s32 txgbe_init_eeprom_params(struct txgbe_hw *hw);
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s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);
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@ -291,6 +291,10 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
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/* PHY */
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phy->identify = txgbe_identify_phy;
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phy->init = txgbe_init_phy_raptor;
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phy->read_i2c_byte = txgbe_read_i2c_byte;
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phy->write_i2c_byte = txgbe_write_i2c_byte;
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phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
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phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
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/* MAC */
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mac->init_hw = txgbe_init_hw;
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@ -7,6 +7,9 @@
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#include "txgbe_mng.h"
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#include "txgbe_phy.h"
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static void txgbe_i2c_start(struct txgbe_hw *hw);
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static void txgbe_i2c_stop(struct txgbe_hw *hw);
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/**
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* txgbe_identify_extphy - Identify a single address for a PHY
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* @hw: pointer to hardware structure
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@ -234,8 +237,204 @@ s32 txgbe_identify_module(struct txgbe_hw *hw)
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**/
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s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
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{
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RTE_SET_USED(hw);
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s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
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u32 vendor_oui = 0;
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enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
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u8 identifier = 0;
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u8 comp_codes_1g = 0;
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u8 comp_codes_10g = 0;
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u8 oui_bytes[3] = {0, 0, 0};
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u8 cable_tech = 0;
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u8 cable_spec = 0;
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u16 enforce_sfp = 0;
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DEBUGFUNC("txgbe_identify_sfp_module");
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if (hw->phy.media_type != txgbe_media_type_fiber) {
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hw->phy.sfp_type = txgbe_sfp_type_not_present;
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return TXGBE_ERR_SFP_NOT_PRESENT;
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}
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
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&identifier);
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if (err != 0) {
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ERR_I2C:
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hw->phy.sfp_type = txgbe_sfp_type_not_present;
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if (hw->phy.type != txgbe_phy_nl) {
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hw->phy.id = 0;
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hw->phy.type = txgbe_phy_unknown;
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}
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return TXGBE_ERR_SFP_NOT_PRESENT;
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}
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if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
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hw->phy.type = txgbe_phy_sfp_unsupported;
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return TXGBE_ERR_SFP_NOT_SUPPORTED;
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}
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
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&comp_codes_1g);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
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&comp_codes_10g);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
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&cable_tech);
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if (err != 0)
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goto ERR_I2C;
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/* ID Module
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* =========
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* 0 SFP_DA_CU
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* 1 SFP_SR
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* 2 SFP_LR
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* 3 SFP_DA_CORE0 - chip-specific
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* 4 SFP_DA_CORE1 - chip-specific
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* 5 SFP_SR/LR_CORE0 - chip-specific
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* 6 SFP_SR/LR_CORE1 - chip-specific
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* 7 SFP_act_lmt_DA_CORE0 - chip-specific
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* 8 SFP_act_lmt_DA_CORE1 - chip-specific
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* 9 SFP_1g_cu_CORE0 - chip-specific
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* 10 SFP_1g_cu_CORE1 - chip-specific
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* 11 SFP_1g_sx_CORE0 - chip-specific
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* 12 SFP_1g_sx_CORE1 - chip-specific
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*/
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if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
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if (hw->bus.lan_id == 0)
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hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
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else
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hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
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} else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
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if (err != 0)
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goto ERR_I2C;
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if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
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hw->phy.sfp_type = (hw->bus.lan_id == 0
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? txgbe_sfp_type_da_act_lmt_core0
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: txgbe_sfp_type_da_act_lmt_core1);
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} else {
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hw->phy.sfp_type = txgbe_sfp_type_unknown;
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}
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} else if (comp_codes_10g &
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(TXGBE_SFF_10GBASESR_CAPABLE |
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TXGBE_SFF_10GBASELR_CAPABLE)) {
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hw->phy.sfp_type = (hw->bus.lan_id == 0
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? txgbe_sfp_type_srlr_core0
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: txgbe_sfp_type_srlr_core1);
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} else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
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hw->phy.sfp_type = (hw->bus.lan_id == 0
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? txgbe_sfp_type_1g_cu_core0
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: txgbe_sfp_type_1g_cu_core1);
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} else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
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hw->phy.sfp_type = (hw->bus.lan_id == 0
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? txgbe_sfp_type_1g_sx_core0
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: txgbe_sfp_type_1g_sx_core1);
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} else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
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hw->phy.sfp_type = (hw->bus.lan_id == 0
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? txgbe_sfp_type_1g_lx_core0
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: txgbe_sfp_type_1g_lx_core1);
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} else {
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hw->phy.sfp_type = txgbe_sfp_type_unknown;
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}
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if (hw->phy.sfp_type != stored_sfp_type)
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hw->phy.sfp_setup_needed = true;
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/* Determine if the SFP+ PHY is dual speed or not. */
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hw->phy.multispeed_fiber = false;
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if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
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(comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
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((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
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(comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
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hw->phy.multispeed_fiber = true;
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/* Determine PHY vendor */
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if (hw->phy.type != txgbe_phy_nl) {
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hw->phy.id = identifier;
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
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if (err != 0)
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goto ERR_I2C;
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vendor_oui = ((u32)oui_bytes[0] << 24) |
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((u32)oui_bytes[1] << 16) |
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((u32)oui_bytes[2] << 8);
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switch (vendor_oui) {
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case TXGBE_SFF_VENDOR_OUI_TYCO:
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if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
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hw->phy.type = txgbe_phy_sfp_tyco_passive;
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break;
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case TXGBE_SFF_VENDOR_OUI_FTL:
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if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
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hw->phy.type = txgbe_phy_sfp_ftl_active;
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else
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hw->phy.type = txgbe_phy_sfp_ftl;
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break;
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case TXGBE_SFF_VENDOR_OUI_AVAGO:
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hw->phy.type = txgbe_phy_sfp_avago;
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break;
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case TXGBE_SFF_VENDOR_OUI_INTEL:
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hw->phy.type = txgbe_phy_sfp_intel;
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break;
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default:
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if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
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hw->phy.type = txgbe_phy_sfp_unknown_passive;
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else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
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hw->phy.type = txgbe_phy_sfp_unknown_active;
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else
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hw->phy.type = txgbe_phy_sfp_unknown;
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break;
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}
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}
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/* Allow any DA cable vendor */
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if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
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TXGBE_SFF_CABLE_DA_ACTIVE)) {
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return 0;
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}
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/* Verify supported 1G SFP modules */
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if (comp_codes_10g == 0 &&
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!(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
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hw->phy.type = txgbe_phy_sfp_unsupported;
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return TXGBE_ERR_SFP_NOT_SUPPORTED;
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}
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hw->mac.get_device_caps(hw, &enforce_sfp);
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if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
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!hw->allow_unsupported_sfp &&
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!(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
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hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
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DEBUGOUT("SFP+ module not supported\n");
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hw->phy.type = txgbe_phy_sfp_unsupported;
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return TXGBE_ERR_SFP_NOT_SUPPORTED;
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}
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return err;
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}
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/**
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@ -246,7 +445,390 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
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**/
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s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
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{
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RTE_SET_USED(hw);
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s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
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u32 vendor_oui = 0;
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enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
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u8 identifier = 0;
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u8 comp_codes_1g = 0;
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u8 comp_codes_10g = 0;
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u8 oui_bytes[3] = {0, 0, 0};
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u16 enforce_sfp = 0;
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u8 connector = 0;
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u8 cable_length = 0;
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u8 device_tech = 0;
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bool active_cable = false;
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DEBUGFUNC("txgbe_identify_qsfp_module");
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if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
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hw->phy.sfp_type = txgbe_sfp_type_not_present;
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err = TXGBE_ERR_SFP_NOT_PRESENT;
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goto out;
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}
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
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&identifier);
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ERR_I2C:
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if (err != 0) {
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hw->phy.sfp_type = txgbe_sfp_type_not_present;
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hw->phy.id = 0;
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hw->phy.type = txgbe_phy_unknown;
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return TXGBE_ERR_SFP_NOT_PRESENT;
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}
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if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
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hw->phy.type = txgbe_phy_sfp_unsupported;
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err = TXGBE_ERR_SFP_NOT_SUPPORTED;
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goto out;
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}
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hw->phy.id = identifier;
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
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&comp_codes_10g);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
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&comp_codes_1g);
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if (err != 0)
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goto ERR_I2C;
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if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
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hw->phy.type = txgbe_phy_qsfp_unknown_passive;
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if (hw->bus.lan_id == 0)
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hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
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else
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hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
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} else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
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TXGBE_SFF_10GBASELR_CAPABLE)) {
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if (hw->bus.lan_id == 0)
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hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
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else
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hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
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} else {
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if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
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active_cable = true;
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if (!active_cable) {
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hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_CONNECTOR,
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&connector);
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hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_CABLE_LENGTH,
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&cable_length);
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hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_DEVICE_TECH,
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&device_tech);
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if (connector ==
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TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
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cable_length > 0 &&
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((device_tech >> 4) ==
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TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
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active_cable = true;
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}
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if (active_cable) {
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hw->phy.type = txgbe_phy_qsfp_unknown_active;
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if (hw->bus.lan_id == 0)
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hw->phy.sfp_type =
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txgbe_sfp_type_da_act_lmt_core0;
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else
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hw->phy.sfp_type =
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txgbe_sfp_type_da_act_lmt_core1;
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} else {
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/* unsupported module type */
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hw->phy.type = txgbe_phy_sfp_unsupported;
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err = TXGBE_ERR_SFP_NOT_SUPPORTED;
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goto out;
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}
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}
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if (hw->phy.sfp_type != stored_sfp_type)
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hw->phy.sfp_setup_needed = true;
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/* Determine if the QSFP+ PHY is dual speed or not. */
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hw->phy.multispeed_fiber = false;
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if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
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(comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
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((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
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(comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
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hw->phy.multispeed_fiber = true;
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/* Determine PHY vendor for optical modules */
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if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
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TXGBE_SFF_10GBASELR_CAPABLE)) {
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
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&oui_bytes[0]);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
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&oui_bytes[1]);
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if (err != 0)
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goto ERR_I2C;
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err = hw->phy.read_i2c_eeprom(hw,
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TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
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&oui_bytes[2]);
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if (err != 0)
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goto ERR_I2C;
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vendor_oui =
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((oui_bytes[0] << 24) |
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(oui_bytes[1] << 16) |
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(oui_bytes[2] << 8));
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|
||||
if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
|
||||
hw->phy.type = txgbe_phy_qsfp_intel;
|
||||
else
|
||||
hw->phy.type = txgbe_phy_qsfp_unknown;
|
||||
|
||||
hw->mac.get_device_caps(hw, &enforce_sfp);
|
||||
if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
|
||||
/* Make sure we're a supported PHY type */
|
||||
if (hw->phy.type == txgbe_phy_qsfp_intel) {
|
||||
err = 0;
|
||||
} else {
|
||||
if (hw->allow_unsupported_sfp) {
|
||||
DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
|
||||
"Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
|
||||
"Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
|
||||
err = 0;
|
||||
} else {
|
||||
DEBUGOUT("QSFP module not supported\n");
|
||||
hw->phy.type =
|
||||
txgbe_phy_sfp_unsupported;
|
||||
err = TXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
err = 0;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: EEPROM byte offset to read
|
||||
* @eeprom_data: value read
|
||||
*
|
||||
* Performs byte read operation to SFP module's EEPROM over I2C interface.
|
||||
**/
|
||||
s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 *eeprom_data)
|
||||
{
|
||||
DEBUGFUNC("txgbe_read_i2c_eeprom");
|
||||
|
||||
return hw->phy.read_i2c_byte(hw, byte_offset,
|
||||
TXGBE_I2C_EEPROM_DEV_ADDR,
|
||||
eeprom_data);
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: EEPROM byte offset to write
|
||||
* @eeprom_data: value to write
|
||||
*
|
||||
* Performs byte write operation to SFP module's EEPROM over I2C interface.
|
||||
**/
|
||||
s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 eeprom_data)
|
||||
{
|
||||
DEBUGFUNC("txgbe_write_i2c_eeprom");
|
||||
|
||||
return hw->phy.write_i2c_byte(hw, byte_offset,
|
||||
TXGBE_I2C_EEPROM_DEV_ADDR,
|
||||
eeprom_data);
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: byte offset to read
|
||||
* @dev_addr: address to read from
|
||||
* @data: value read
|
||||
*
|
||||
* Performs byte read operation to SFP module's EEPROM over I2C interface at
|
||||
* a specified device address.
|
||||
**/
|
||||
s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data)
|
||||
{
|
||||
UNREFERENCED_PARAMETER(dev_addr);
|
||||
|
||||
DEBUGFUNC("txgbe_read_i2c_byte");
|
||||
|
||||
txgbe_i2c_start(hw);
|
||||
|
||||
/* wait tx empty */
|
||||
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
|
||||
TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
|
||||
return -TERR_TIMEOUT;
|
||||
}
|
||||
|
||||
/* read data */
|
||||
wr32(hw, TXGBE_I2CDATA,
|
||||
byte_offset | TXGBE_I2CDATA_STOP);
|
||||
wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
|
||||
|
||||
/* wait for read complete */
|
||||
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
|
||||
TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
|
||||
return -TERR_TIMEOUT;
|
||||
}
|
||||
|
||||
txgbe_i2c_stop(hw);
|
||||
|
||||
*data = 0xFF & rd32(hw, TXGBE_I2CDATA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_read_i2c_byte - Reads 8 bit word over I2C
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: byte offset to read
|
||||
* @dev_addr: address to read from
|
||||
* @data: value read
|
||||
*
|
||||
* Performs byte read operation to SFP module's EEPROM over I2C interface at
|
||||
* a specified device address.
|
||||
**/
|
||||
s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data)
|
||||
{
|
||||
u32 swfw_mask = hw->phy.phy_semaphore_mask;
|
||||
int err = 0;
|
||||
|
||||
if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
|
||||
return TXGBE_ERR_SWFW_SYNC;
|
||||
err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
|
||||
hw->mac.release_swfw_sync(hw, swfw_mask);
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: byte offset to write
|
||||
* @dev_addr: address to write to
|
||||
* @data: value to write
|
||||
*
|
||||
* Performs byte write operation to SFP module's EEPROM over I2C interface at
|
||||
* a specified device address.
|
||||
**/
|
||||
s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data)
|
||||
{
|
||||
UNREFERENCED_PARAMETER(dev_addr);
|
||||
|
||||
DEBUGFUNC("txgbe_write_i2c_byte");
|
||||
|
||||
txgbe_i2c_start(hw);
|
||||
|
||||
/* wait tx empty */
|
||||
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
|
||||
TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
|
||||
return -TERR_TIMEOUT;
|
||||
}
|
||||
|
||||
wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
|
||||
wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
|
||||
|
||||
/* wait for write complete */
|
||||
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
|
||||
TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
|
||||
return -TERR_TIMEOUT;
|
||||
}
|
||||
txgbe_i2c_stop(hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_write_i2c_byte - Writes 8 bit word over I2C
|
||||
* @hw: pointer to hardware structure
|
||||
* @byte_offset: byte offset to write
|
||||
* @dev_addr: address to write to
|
||||
* @data: value to write
|
||||
*
|
||||
* Performs byte write operation to SFP module's EEPROM over I2C interface at
|
||||
* a specified device address.
|
||||
**/
|
||||
s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data)
|
||||
{
|
||||
u32 swfw_mask = hw->phy.phy_semaphore_mask;
|
||||
int err = 0;
|
||||
|
||||
if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
|
||||
return TXGBE_ERR_SWFW_SYNC;
|
||||
err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
|
||||
hw->mac.release_swfw_sync(hw, swfw_mask);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_i2c_start - Sets I2C start condition
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Sets I2C start condition (High -> Low on SDA while SCL is High)
|
||||
**/
|
||||
static void txgbe_i2c_start(struct txgbe_hw *hw)
|
||||
{
|
||||
DEBUGFUNC("txgbe_i2c_start");
|
||||
|
||||
wr32(hw, TXGBE_I2CENA, 0);
|
||||
|
||||
wr32(hw, TXGBE_I2CCON,
|
||||
(TXGBE_I2CCON_MENA |
|
||||
TXGBE_I2CCON_SPEED(1) |
|
||||
TXGBE_I2CCON_RESTART |
|
||||
TXGBE_I2CCON_SDIA));
|
||||
wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
|
||||
wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
|
||||
wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
|
||||
wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
|
||||
wr32(hw, TXGBE_I2CTXTL, 4);
|
||||
wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
|
||||
wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
|
||||
|
||||
wr32(hw, TXGBE_I2CICM, 0);
|
||||
wr32(hw, TXGBE_I2CENA, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_i2c_stop - Sets I2C stop condition
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
|
||||
**/
|
||||
static void txgbe_i2c_stop(struct txgbe_hw *hw)
|
||||
{
|
||||
DEBUGFUNC("txgbe_i2c_stop");
|
||||
|
||||
/* wait for completion */
|
||||
if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
|
||||
0, NULL, 100, 100)) {
|
||||
DEBUGFUNC("i2c stop timeout.");
|
||||
}
|
||||
|
||||
wr32(hw, TXGBE_I2CENA, 0);
|
||||
}
|
||||
|
||||
|
||||
@ -332,5 +332,17 @@ s32 txgbe_identify_phy(struct txgbe_hw *hw);
|
||||
s32 txgbe_identify_module(struct txgbe_hw *hw);
|
||||
s32 txgbe_identify_sfp_module(struct txgbe_hw *hw);
|
||||
s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw);
|
||||
s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data);
|
||||
s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 *data);
|
||||
s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data);
|
||||
s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 dev_addr, u8 data);
|
||||
s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 *eeprom_data);
|
||||
s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
|
||||
u8 eeprom_data);
|
||||
|
||||
#endif /* _TXGBE_PHY_H_ */
|
||||
|
||||
@ -358,6 +358,7 @@ struct txgbe_phy_info {
|
||||
u32 media_type;
|
||||
u32 phy_semaphore_mask;
|
||||
bool reset_disable;
|
||||
bool multispeed_fiber;
|
||||
bool qsfp_shared_i2c_bus;
|
||||
u32 nw_mng_if_sel;
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user