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common/mlx5: share CQ entry check

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The CQE has owner bit to indicate if it is in SW control or HW.

Share a CQE check for all the mlx5 drivers.

Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit is contained in:
Matan Azrad 2020-01-29 12:38:31 +00:00 committed by Ferruh Yigit
parent e415f348e3
commit 8fc7421759
2 changed files with 42 additions and 38 deletions
drivers
common/mlx5
mlx5_common.h
net/mlx5
mlx5_rxtx.h

41
drivers/common/mlx5/mlx5_common.h

@ -9,8 +9,11 @@
#include <stdio.h>
#include <rte_pci.h>
#include <rte_atomic.h>
#include <rte_log.h>
#include "mlx5_prm.h"
/*
* Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
@ -107,6 +110,44 @@ enum {
PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
};
/* CQE status. */
enum mlx5_cqe_status {
MLX5_CQE_STATUS_SW_OWN = -1,
MLX5_CQE_STATUS_HW_OWN = -2,
MLX5_CQE_STATUS_ERR = -3,
};
/**
* Check whether CQE is valid.
*
* @param cqe
* Pointer to CQE.
* @param cqes_n
* Size of completion queue.
* @param ci
* Consumer index.
*
* @return
* The CQE status.
*/
static __rte_always_inline enum mlx5_cqe_status
check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
const uint16_t ci)
{
const uint16_t idx = ci & cqes_n;
const uint8_t op_own = cqe->op_own;
const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
return MLX5_CQE_STATUS_HW_OWN;
rte_cio_rmb();
if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
op_code == MLX5_CQE_REQ_ERR))
return MLX5_CQE_STATUS_ERR;
return MLX5_CQE_STATUS_SW_OWN;
}
int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
#endif /* RTE_PMD_MLX5_COMMON_H_ */

39
drivers/net/mlx5/mlx5_rxtx.h

@ -33,6 +33,7 @@
#include <mlx5_glue.h>
#include <mlx5_prm.h>
#include <mlx5_common.h>
#include "mlx5_defs.h"
#include "mlx5_utils.h"
@ -549,44 +550,6 @@ __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
#define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
#endif
/* CQE status. */
enum mlx5_cqe_status {
MLX5_CQE_STATUS_SW_OWN = -1,
MLX5_CQE_STATUS_HW_OWN = -2,
MLX5_CQE_STATUS_ERR = -3,
};
/**
* Check whether CQE is valid.
*
* @param cqe
* Pointer to CQE.
* @param cqes_n
* Size of completion queue.
* @param ci
* Consumer index.
*
* @return
* The CQE status.
*/
static __rte_always_inline enum mlx5_cqe_status
check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
const uint16_t ci)
{
const uint16_t idx = ci & cqes_n;
const uint8_t op_own = cqe->op_own;
const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
return MLX5_CQE_STATUS_HW_OWN;
rte_cio_rmb();
if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
op_code == MLX5_CQE_REQ_ERR))
return MLX5_CQE_STATUS_ERR;
return MLX5_CQE_STATUS_SW_OWN;
}
/**
* Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
* cloned mbuf is allocated is returned instead.